CN110212014A - Superjunction devices terminal structure and preparation method thereof - Google Patents
Superjunction devices terminal structure and preparation method thereof Download PDFInfo
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- CN110212014A CN110212014A CN201910361189.XA CN201910361189A CN110212014A CN 110212014 A CN110212014 A CN 110212014A CN 201910361189 A CN201910361189 A CN 201910361189A CN 110212014 A CN110212014 A CN 110212014A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The present invention provides a kind of superjunction devices terminal structure and preparation method thereof, the superjunction devices terminal structure includes: the semiconductor substrate of the first conduction type；The epitaxial layer of first conduction type is formed in the semiconductor substrate；Multiple rod structures of second conduction type, are formed in the epitaxial layer, and extend along the thickness direction of the epitaxial layer；Multiple rod structures are in the epitaxial layer along the direction arrangement for being parallel to the semiconductor substrate surface；The pressure-resistant enhancement region of second conduction type, is formed in the epitaxial layer；The lower part of the epitaxial layer of the pressure resistance enhancement region between two adjacent rod structures.The present invention while realizing superjunction termination area charge balance, improves terminal field distribution and depletion layer curvature, makes pressure-resistant raising by concatenating multiple rod structures with the pressure-resistant enhancement region.Preparation method preparation process provided by the invention is simple and cost is relatively low, is suitable for producing in enormous quantities.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing fields, more particularly to a kind of superjunction devices terminal structure and its system
Preparation Method.
Background technique
In power electronics field, power device plays irreplaceable role.Wherein, superjunction devices (super
Junction) due to being concerned with high voltage endurance capability and excellent conductive capability, for superjunction devices new construction
Research and development just become industry research hot spot.
Currently, the high voltage characteristic of super junction power device is one of the important directions of superjunction devices research and development.Wherein, with superjunction
The cellular plot structure of device is the same, and the terminal structure of superjunction devices termination environment is also to be alternately arranged realization charge using p column and n column
Balance, to obtain higher breakdown voltage.Since the breakdown voltage of superjunction devices is very sensitive for charge unbalance, termination environment
The process deviations such as width, spacing and the concentration of doped column may cause the increase of terminal end surface electric field, and then generating device terminal
The phenomenon that puncturing in advance and damaging.Not only manufacture craft difficulty is larger for existing super-junction terminal structure, but also its reliability is by electricity
Lotus imbalance is affected, it is difficult to obtain the super-junction terminal structure of high voltage high reliability.
Therefore, it is necessary to propose a kind of new superjunction devices terminal structure and preparation method thereof, solve the above problems.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of superjunction devices terminal structure and
Preparation method, the super-junction terminal structure for solving the problems, such as to be difficult to obtain high voltage high reliability in the prior art.
To achieve the above object and other related purposes, the present invention provides a kind of superjunction devices terminal structures, comprising:
The semiconductor substrate of first conduction type；
The epitaxial layer of first conduction type is formed in the semiconductor substrate；
Multiple rod structures of second conduction type, are formed in the epitaxial layer, and along the thickness direction of the epitaxial layer
Extend；Multiple rod structures have been arranged as interval along the direction for being parallel to the semiconductor substrate surface in the epitaxial layer
Array；
The pressure-resistant enhancement region of second conduction type, is formed in the epitaxial layer, and along the arrangement of multiple rod structures
Direction extends to concatenate at least partly described rod structure.
As a preferred solution of the present invention, the spacing between the pressure-resistant enhancement region and the bottom of the rod structure is small
In the one third for being equal to the rod structure height.
As a preferred solution of the present invention, the material of the epitaxial layer, the rod structure and the pressure-resistant enhancement region
Include silicon.
As a preferred solution of the present invention, the semiconductor substrate silicon-containing substrate.
As a preferred solution of the present invention, multiple rod structures have same widths, and in the epitaxial layer
Equidistant arrangement.
As a preferred solution of the present invention, first conduction type is N-shaped and second conduction type is p
Type；Or first conduction type is p-type and second conduction type is N-shaped.
The present invention also provides a kind of preparation methods of superjunction devices terminal structure, include the following steps:
The semiconductor substrate of first conduction type is provided；
The epitaxial layer of the first conduction type of epitaxial growth on the semiconductor substrate forms pressure resistance in the epitaxial layer
Enhancement region；
Multiple rod structures with the second conduction type are formed in the epitaxial layer, multiple rod structures are along described outer
The thickness direction for prolonging layer extends；Multiple rod structures are in the epitaxial layer along the side for being parallel to the semiconductor substrate surface
To being arranged as spaced array；The pressure resistance enhancement region extends along the orientation of multiple rod structures with will at least partly
The rod structure concatenation.
As a preferred solution of the present invention, the spacing between the pressure-resistant enhancement region and the bottom of the rod structure is small
In the one third for being equal to the rod structure height.
As a preferred solution of the present invention, the material of the epitaxial layer, the rod structure and the pressure-resistant enhancement region
Include silicon.
As a preferred solution of the present invention, the semiconductor substrate silicon-containing substrate.
As a preferred solution of the present invention, multiple rod structures have same widths, and in the epitaxial layer
Equidistant arrangement.
As a preferred solution of the present invention, first conduction type is N-shaped and second conduction type is p
Type；Or first conduction type is p-type and second conduction type is N-shaped.
As a preferred solution of the present invention, the epitaxial layer includes stacked up and down lower layer's epitaxial layer and upper layer extension
Layer, on the semiconductor substrate when epitaxial layer described in epitaxial growth, the process for forming the pressure-resistant enhancement region includes following step
It is rapid:
Lower layer's epitaxial layer described in epitaxial growth on the semiconductor substrate；
The pressure-resistant enhancement region is formed in lower layer's epitaxial layer by ion implanting；
The upper layer epitaxial layer described in epitaxial growth on lower layer's epitaxial layer, to form the epitaxial layer.
As a preferred solution of the present invention, the process for forming the rod structure includes the following steps:
Groove, the groove perforation pressure-resistant enhancement region are formed by lithography and etching on said epitaxial layer there；
Epitaxial growth filled layer in the trench, and the groove is filled up to form the rod structure.
As a preferred solution of the present invention, be formed by the groove be it is multiple, multiple grooves have it is identical
Width, and in the medium spacing arrangement of the epitaxial layer.
As described above, the present invention provides a kind of superjunction devices terminal structure and preparation method thereof, by being increased with the pressure resistance
Strong area concatenates multiple rod structures, while realizing superjunction termination area charge balance, improves terminal field distribution and exhausts
Layer curvature, makes pressure-resistant raising.Preparation method preparation process provided by the invention is simple and cost is relatively low, is suitable for producing in enormous quantities.
Detailed description of the invention
Fig. 1 is shown as a kind of process of the preparation method of the superjunction devices terminal structure provided in the embodiment of the present invention one
Figure.
Fig. 2 is shown as the schematic cross-section of the semiconductor substrate provided in the embodiment of the present invention one.
Fig. 3 is shown as in the embodiment of the present invention one epitaxial growth lower layer epitaxial layer on a semiconductor substrate, and passes through ion
It is infused in the schematic cross-section that pressure-resistant enhancement region is formed in lower layer's epitaxial layer.
Fig. 4 is shown as in the embodiment of the present invention one spreading injection region to obtain by high-temperature annealing process after ion implantation
Obtain the schematic cross-section of suitably pressure-resistant enhancement region.
The section that Fig. 5 is shown as continuing on lower layer's epitaxial layer in the embodiment of the present invention one epitaxial growth upper layer epitaxial layer shows
It is intended to.
Fig. 6 is shown as in the embodiment of the present invention one epitaxial growth epitaxial layer on a semiconductor substrate and forms pressure-resistant enhancement region
Schematic cross-section after 103.
Fig. 7 is shown as the schematic cross-section of the groove formed in epitaxial layer in the embodiment of the present invention one.
Fig. 8 is shown as the schematic cross-section of the rod structure formed in epitaxial layer in the embodiment of the present invention one.
Fig. 9 is shown as the partial top view of the rod structure formed in epitaxial layer in the embodiment of the present invention one.
Figure 10 is shown as a kind of schematic cross-section of the superjunction devices terminal structure provided in the embodiment of the present invention one.
Depletion region boundary is illustrated in superjunction devices terminal structure when Figure 11 is shown as superjunction devices shutdown in the prior art
Figure.
Figure 12 is shown as depletion region edge in superjunction devices terminal structure when superjunction devices turns off in the embodiment of the present invention one
Boundary's schematic diagram.
Component label instructions
101 semiconductor substrates
102 epitaxial layers
102a lower layer epitaxial layer
The upper layer 102b epitaxial layer
103 pressure-resistant enhancement regions
104 rod structures
104a groove
105 dielectric layers
The width of l rod structure
Spacing between s rod structure
Step 1)~3 S1~S3)
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Disclosed content understands further advantage and effect of the invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Fig. 1 is please referred to Figure 12.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though only show in diagram with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation form, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout form may also be increasingly complex.
Embodiment one
Fig. 1 to Figure 12 is please referred to, the present invention provides a kind of preparation methods of superjunction devices terminal structure, including walk as follows
It is rapid:
1) semiconductor substrate 101 of the first conduction type is provided；
2) epitaxial layer 102 of the epitaxial growth with the first conduction type in the semiconductor substrate 101, in the extension
Pressure-resistant enhancement region 103 is formed in layer 102；
3) multiple rod structures 104 with the second conduction type, multiple rod structures are formed in the epitaxial layer 102
104 along the epitaxial layer 102 thickness direction extend；Multiple rod structures 104 edge in the epitaxial layer 102 is parallel to institute
The direction for stating 101 surface of semiconductor substrate is arranged as spaced array；The pressure resistance enhancement region 103 is along multiple rod structures
104 orientation extends to concatenate at least partly described rod structure 104.
In step 1), the S1 step and Fig. 2 of Fig. 1 are please referred to, the semiconductor substrate 101 of the first conduction type is provided.Fig. 2
It is the schematic cross-section of the semiconductor substrate 101.Optionally, in the present embodiment, first conduction type is N-shaped, institute
Stating semiconductor substrate 101 is n-type silicon substrate.In other case study on implementation of the invention, the semiconductor substrate 101 can also be selected
For p-type silicon substrate or other semiconductor substrates.
In step 2), the S2 step and Fig. 3 to Fig. 6 of Fig. 1, the epitaxial growth in the semiconductor substrate 101 are please referred to
Epitaxial layer 102 with the first conduction type forms pressure-resistant enhancement region 103 in the epitaxial layer 102.Fig. 6 is described half
Epitaxial layer 102 described in epitaxial growth and the schematic cross-section behind the pressure-resistant enhancement region 103 is formed on conductor substrate 101.It is optional
Ground, in the present embodiment, the epitaxial layer 102 are silicon materials, have first conductive-type identical with the semiconductor substrate 101
Type, i.e. N-shaped.The silicon layer of N-shaped can be by being doped to obtain in epitaxial process.The thickness model of the epitaxial layer 102
It encloses and is chosen as between 10 microns to 60 microns, can be changed according to the design requirement of superjunction devices.The pressure resistance increases
Strong area 103 is formed in the region in the epitaxial layer 102 close to the semiconductor substrate 101, that is, is embedded in the epitaxial layer 102
In.
As an example, as shown in Figures 3 to 6, the epitaxial layer 102 includes stacked up and down lower layer epitaxial layer 102a and upper
Layer epitaxial layer 102b when the epitaxial layer 102 described in epitaxial growth in the semiconductor substrate 101, forms the pressure-resistant enhancement region
103 process includes the following steps:
A) the lower layer epitaxial layer 102a described in epitaxial growth in the semiconductor substrate 101；
B) the pressure-resistant enhancement region 103 is formed in lower layer's epitaxial layer 102a by ion implanting；
C) the upper layer epitaxial layer 102b described in epitaxial growth on lower layer's epitaxial layer 102a, to form the epitaxial layer
102。
Specifically, in the present embodiment, the lower layer's epitaxial layer 102a and upper layer epitaxial layer 102b is silicon materials.
As shown in figure 3, the lower layer epitaxial layer 102a described in epitaxial growth in the semiconductor substrate 101, and by ion implanting in institute
It states and forms the pressure-resistant enhancement region 103 in lower layer epitaxial layer 102a.Optionally, as shown in figure 4, after ion implantation, Ke Yitong
Crossing high-temperature annealing process spreads injection region to obtain the suitable pressure-resistant enhancement region 103.As shown in figure 5, in the lower layer
Continue upper layer epitaxial layer 102b described in epitaxial growth on epitaxial layer 102a, ultimately forms the complete extension shown in Fig. 6
Layer 102, the pressure resistance enhancement region 103 are embedded in the epitaxial layer 102.
In step 3), the S3 step and Fig. 7 to Fig. 9 of Fig. 1 are please referred to, being formed in the epitaxial layer 102 has second
Multiple rod structures 104 of conduction type, multiple rod structures 104 extend along the thickness direction of the epitaxial layer 102；Multiple institutes
State rod structure 104 be arranged as in the epitaxial layer 102 along the direction for being parallel to 101 surface of semiconductor substrate it is spaced
Array；The pressure resistance enhancement region 103 extends along the orientation of multiple rod structures 104 with will at least partly described rod structure
104 concatenations.Specifically, in the present embodiment, the material of the rod structure 104 includes silicon, has the second conduction type, i.e. p-type.
As shown in Figure 8 and Figure 9, the rod structure 104 is multiple, and multiple rod structures 104 have same widths, and in the extension
It is equidistantly arranged in layer 102.Fig. 8 is the schematic cross-section of the rod structure 104 formed in the epitaxial layer 102, and Fig. 9 is
Its partial top view.Wherein, Fig. 9 illustrates the equidistant array being arranged in by two rod structures 104, and actual
In superjunction devices, equidistant array generally is lined up by hundreds of to thousands of rod structures 104.Due in superjunction devices,
Distance s between the width l and the rod structure 104 of the rod structure 104 have the performances such as the pressure resistance of superjunction devices important
It influences, the rod structure 104 can be generally designed as to identical width and identical spacing, that is, there is unified pitch (pitch
size).For example, the width l can be set as 5 microns, and the distance s can be set in the array that the rod structure 104 is arranged in
It is 6 microns.
As an example, as shown in Figure 7 and Figure 8, the superjunction devices in the present embodiment uses slot type structure, i.e., the described column knot
Structure 104 on the epitaxial layer 102 by forming groove 104a, and epitaxial growth filled layer obtains institute in the groove 104a
State rod structure 104.Specifically, in Fig. 7, patterned photoresist is formed by photoetching process on the epitaxial layer 102 and is covered
Film layer forms the hard mask layer that dielectric layer is constituted by chemical wet etching, using the photoresist mask layer or hard mask layer as quarter
Barrier layer is lost, dry etching is carried out to the epitaxial layer 102, if DRIE is etched, and forms the groove 104a.Optionally, institute
The depth bounds of groove 104a are stated between 5 microns to 55 microns, such as 42 microns, it can be according to the epitaxial layer 102
Thickness and superjunction devices design requirement are changed.In fig. 8, by the groove 104a epitaxial growth have and second lead
The filled layer of electric type, the i.e. silicon materials of p-type fill up the groove 104a, to form the rod structure 104.In the groove
It further include remaining in the epitaxial layer using the removal of the methods of chemical mechanical grinding in 104a after the complete filled layer of epitaxial growth
The step of extra filled layer on 102 surfaces.
As an example, in the present embodiment, first conduction type is N-shaped and second conduction type is p-type.And
In other case study on implementation of the invention, it also can choose and first conduction type be set as p-type, and second conductive-type
Type is set as N-shaped.For example, on the silicon substrate of p-type epitaxial growth p-type silicon materials, and form n-type silicon rod structure.
As an example, as shown in figure 8, the spacing between the pressure resistance enhancement region 103 and the bottom of the rod structure 104 is small
In the one third for being equal to 104 height of rod structure.The i.e. described pressure-resistant enhancement region 103 is located at the bottom of the rod structure 104
Near, it is concatenated near bottom between multiple rod structures 104 by the pressure-resistant enhancement region 103, this will be significantly improved
The field distribution of termination environment.It should be pointed out that the pressure resistance enhancement region 103 has only concatenated in termination environment in the present embodiment
The part rod structure 104, in other case study on implementation of the invention, the pressure resistance enhancement region 103 can also concatenate end completely
All rod structures 104 in petiolarea.
As an example, further including the upper table in the epitaxial layer 102 after forming the rod structure 104 as shown in Figure 10
The step of face blanket dielectric layer 105.Optionally, the dielectric layer 105 includes the group of silicon dioxide layer, silicon nitride layer or both
It closes.It should be pointed out that the present embodiment is only described in detail the structure of the termination environment of superjunction devices, and superjunction devices
The structure of cellular region has no influence for the implementation of the present embodiment, and the present embodiment is not construed as limiting the structure of cellular region, in cellular
Area can also form the structures such as source region, grid and metal electrode.In addition, the rod structure 104 and the pressure-resistant enhancement region 103 1
As be all that same type material is constituted, and doping type having the same, therefore can regard as integrated.
In addition, each step of the present embodiment preparation method for a clear description, has carried out label sequence, but this to each step
The specific implementation sequence of each step of preparation method of the present invention is not limited, those skilled in the art can be according to practical feelings
Condition is adjusted implementation sequence.
As shown in Figure 10, the present invention also provides a kind of superjunction devices terminal structures, comprising:
The semiconductor substrate 101 of first conduction type；
The epitaxial layer 102 of first conduction type is formed in the semiconductor substrate 101；
Multiple rod structures 104 of second conduction type are formed in the epitaxial layer 102, and along the epitaxial layer 102
Thickness direction extends；Multiple rod structures 104 edge in the epitaxial layer 102 is parallel to 101 surface of semiconductor substrate
Direction be arranged as spaced array；
The pressure-resistant enhancement region 103 of second conduction type is formed in the epitaxial layer 102, and along multiple rod structures
104 orientation extends to concatenate at least partly described rod structure 104.
As an example, the spacing between the pressure resistance enhancement region 103 and the bottom of the rod structure 104 is less than or equal to described
The one third of 104 height of rod structure.
As an example, the semiconductor substrate 101 includes silicon substrate.Optionally, the semiconductor substrate 101 is n-type silicon
Substrate.The epitaxial layer 102 is silicon materials, has first conduction type identical with the semiconductor substrate 101, i.e. N-shaped.Institute
The material for stating rod structure 104 includes silicon.The rod structure 104 be it is multiple, multiple rod structures 104 have same widths, and
It is equidistantly arranged in the epitaxial layer 102, as shown in Figure 8 and Figure 9.The pressure resistance enhancement region 103 is formed in the epitaxial layer
Close to the region of the semiconductor substrate 101 in 102, that is, it is embedded in the epitaxial layer 102, and along multiple rod structures
104 orientation extends to concatenate at least partly described rod structure 104.
As an example, first conduction type is N-shaped and second conduction type is p-type in the present embodiment.At this
In other case study on implementation of invention, it is also possible to that first conduction type is p-type and second conduction type is N-shaped.
As an example, as shown in Figure 10, the superjunction devices terminal structure further includes dielectric layer 105, it is covered in described outer
Prolong the upper surface of layer 102.
The present invention concatenates the pressure-resistant enhancement region 103 of multiple rod structures 104 by introducing, and is realizing superjunction charge
While balance, improves terminal field distribution and depletion layer curvature, make pressure-resistant raising.It is the prior art as shown in phantom in Figure 11
Depletion region boundary in superjunction devices terminal structure when middle superjunction devices turns off is as shown in figure 12 the present embodiment shown in middle dotted line
Depletion region boundary in superjunction devices terminal structure when middle superjunction devices turns off.By the drift of superjunction devices in this present embodiment
The pressure-resistant enhancement region 103 is also introduced in area, optimizes terminal field distribution and depletion layer curvature, compared to the prior art
Super-junction structure, depletion region when superjunction devices shutdown in the present embodiment is substantially extended, thus the pressure resistance of terminal structure is special
Property is been significantly enhanced.
Embodiment two
A kind of superjunction devices terminal structure and preparation method thereof is present embodiments provided, with the superjunction devices in embodiment one
Terminal structure is compared, difference in this case is that, the pressure-resistant enhancement region in the present embodiment can be multilayered structure.
As an example, on the basis of based on the pressure-resistant enhancement region introduced in embodiment one, in the pressure resistance enhancing
The lower section in area is re-introduced into another floor with interval has the mutually isostructural pressure-resistant enhancement region, and equally concatenates multiple columns
Structure.
Other compositions and preparation method of the provided superjunction devices terminal structure of the present embodiment are the same as example 1, this
Place repeats no more.
Compared to the superjunction devices terminal structure in embodiment one, superjunction devices terminal structure provided by the present embodiment is introduced
Double-deck pressure-resistant enhancement region can strengthen terminal field distribution, expand depletion layer range, to further promote superjunction devices
The voltage endurance of terminal structure.
In conclusion the superjunction devices is whole the present invention provides a kind of superjunction devices terminal structure and preparation method thereof
End structure includes: the semiconductor substrate of the first conduction type；The epitaxial layer of first conduction type is formed in the semiconductor substrate
On；Multiple rod structures of second conduction type, are formed in the epitaxial layer, and extend along the thickness direction of the epitaxial layer；
Multiple rod structures are arranged as spaced battle array along the direction for being parallel to the semiconductor substrate surface in the epitaxial layer
Column；The pressure-resistant enhancement region of second conduction type, is formed in the epitaxial layer, and prolongs along the orientation of multiple rod structures
It stretches to concatenate at least partly described rod structure.The preparation method of the superjunction devices terminal structure, includes the following steps: to provide
The semiconductor substrate of first conduction type；The epitaxial layer of the first conduction type of epitaxial growth on the semiconductor substrate, in institute
It states and forms pressure-resistant enhancement region in epitaxial layer；Multiple rod structures with the second conduction type are formed in the epitaxial layer, it is multiple
The rod structure extends along the thickness direction of the epitaxial layer；Multiple rod structures are described along being parallel in the epitaxial layer
The direction of semiconductor substrate surface is arranged as spaced array；The pressure resistance enhancement region is along the arrangement side of multiple rod structures
To extension to concatenate at least partly described rod structure.The present invention is by concatenating multiple column knots with the pressure-resistant enhancement region
Structure improves terminal field distribution and depletion layer curvature, makes pressure-resistant raising while realizing superjunction termination area charge balance.This
It invents the preparation method preparation process provided simply and cost is relatively low, be suitable for producing in enormous quantities.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (15)
1. a kind of superjunction devices terminal structure characterized by comprising
The semiconductor substrate of first conduction type；
The epitaxial layer of first conduction type is formed in the semiconductor substrate；
Multiple rod structures of second conduction type, are formed in the epitaxial layer, and extend along the thickness direction of the epitaxial layer；
Multiple rod structures are arranged as spaced battle array along the direction for being parallel to the semiconductor substrate surface in the epitaxial layer
Column；
The pressure-resistant enhancement region of second conduction type, is formed in the epitaxial layer, and along the orientation of multiple rod structures
Extend to concatenate at least partly described rod structure.
2. a kind of superjunction devices terminal structure according to claim 1, which is characterized in that it is described pressure resistance enhancement region with it is described
Spacing between the bottom of rod structure is less than or equal to the one third of the rod structure height.
3. a kind of superjunction devices terminal structure according to claim 1, which is characterized in that the epitaxial layer, the column knot
Structure and the material of the pressure-resistant enhancement region include silicon.
4. a kind of superjunction devices terminal structure according to claim 1, which is characterized in that the semiconductor substrate is siliceous
Substrate.
5. a kind of superjunction devices terminal structure according to claim 1, which is characterized in that multiple rod structures have phase
Same width, and in the medium spacing arrangement of the epitaxial layer.
6. a kind of superjunction devices terminal structure according to claim 1, which is characterized in that first conduction type is n
Type and second conduction type are p-type；Or first conduction type is p-type and second conduction type is N-shaped.
7. a kind of preparation method of superjunction devices terminal structure, which comprises the steps of:
The semiconductor substrate of first conduction type is provided；
The epitaxial layer of the first conduction type of epitaxial growth on the semiconductor substrate forms pressure resistance enhancing in the epitaxial layer
Area；
Multiple rod structures with the second conduction type are formed in the epitaxial layer, multiple rod structures are along the epitaxial layer
Thickness direction extend；Multiple rod structures are in the epitaxial layer along the direction row for being parallel to the semiconductor substrate surface
It is classified as spaced array；The pressure resistance enhancement region extends along the orientation of multiple rod structures with will be at least partly described
Rod structure concatenation.
8. the preparation method of superjunction devices terminal structure according to claim 7, which is characterized in that the pressure resistance enhancement region
Spacing between the bottom of the rod structure is less than or equal to the one third of the rod structure height.
9. the preparation method of superjunction devices terminal structure according to claim 7, which is characterized in that the epitaxial layer, institute
The material for stating rod structure and the pressure-resistant enhancement region includes silicon.
10. the preparation method of superjunction devices terminal structure according to claim 7, which is characterized in that the semiconductor lining
Bottom includes silicon substrate.
11. the preparation method of superjunction devices terminal structure according to claim 7, which is characterized in that multiple column knots
Structure has same widths, and in the medium spacing arrangement of the epitaxial layer.
12. the preparation method of superjunction devices terminal structure according to claim 7, which is characterized in that described first is conductive
Type is N-shaped and second conduction type is p-type；Or first conduction type is p-type and second conduction type is n
Type.
13. the preparation method of superjunction devices terminal structure according to claim 7, which is characterized in that the epitaxial layer packet
Include stacked up and down lower layer's epitaxial layer and upper layer epitaxial layer, on the semiconductor substrate when epitaxial layer described in epitaxial growth, shape
Process at the pressure-resistant enhancement region includes the following steps:
Lower layer's epitaxial layer described in epitaxial growth on the semiconductor substrate；
The pressure-resistant enhancement region is formed in lower layer's epitaxial layer by ion implanting；
The upper layer epitaxial layer described in epitaxial growth on lower layer's epitaxial layer, to form the epitaxial layer.
14. the preparation method of superjunction devices terminal structure according to claim 7, which is characterized in that form the column knot
The process of structure includes the following steps:
Groove, the groove perforation pressure-resistant enhancement region are formed by lithography and etching on said epitaxial layer there；
Epitaxial growth filled layer in the trench, and the groove is filled up to form the rod structure.
15. the preparation method of superjunction devices terminal structure according to claim 14, which is characterized in that be formed by described
Groove be it is multiple, multiple grooves have same widths, and in the medium spacing arrangement of the epitaxial layer.
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