CN104022032B - The method that vertical bipolar transistor is formed in FinFET processing procedures - Google Patents
The method that vertical bipolar transistor is formed in FinFET processing procedures Download PDFInfo
- Publication number
- CN104022032B CN104022032B CN201410218419.4A CN201410218419A CN104022032B CN 104022032 B CN104022032 B CN 104022032B CN 201410218419 A CN201410218419 A CN 201410218419A CN 104022032 B CN104022032 B CN 104022032B
- Authority
- CN
- China
- Prior art keywords
- bipolar transistor
- fin structure
- conduction type
- ion
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 90
- 238000012545 processing Methods 0.000 title claims abstract description 34
- 238000002955 isolation Methods 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 21
- 230000004888 barrier function Effects 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 6
- 238000004528 spin coating Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000002360 preparation method Methods 0.000 claims description 4
- 230000005669 field effect Effects 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 8
- 230000006870 function Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000008280 blood Substances 0.000 description 2
- 210000004369 blood Anatomy 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000012958 reprocessing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6625—Lateral transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
Abstract
The invention discloses a kind of method that vertical bipolar structure is formed in FinFET processing procedures, using existing FinFET structure, forms vertical PNP bipolar transistor, so as to increased the function of integrated circuit by selectively in the method for zones of different doping.
Description
Technical field
The present invention relates to it is brilliant that vertical bipolar is formed in technical field of manufacturing semiconductors, more particularly to a kind of FinFET processing procedures
The method of body pipe.
Background technology
At present, fin formula field effect transistor (FinFET) is as a kind of brand-new semiconductor device structure, mutual to improve
The performance of MOS memory (CMOS) is mended, the prevailing technology of less than 20 nanometers technology nodes will be become.Should
The manufacturing process of structure is complicated, so that the vertical bipolar transistor being readily available in traditional planar technology is applied to fin
Formula field-effect transistor is but difficult to realize, and bipolar transistor is prerequisite device in Analog Circuit Design, therefore
Bipolar transistor can not be formed in FinFET processing procedures can reduce the function of integrated circuit.
Therefore, a kind of method that bipolar transistor is formed in fin formula field effect transistor processing procedure how is found, and then
The function of increasing integrated circuit becomes the direction that those skilled in the art endeavour to study.
Chinese patent (publication number：CN103515282A a kind of fin formula field effect transistor and forming method thereof) is disclosed,
The fin formula field effect transistor that the invention is provided, the side wall of formed shallow trench isolation have gradient, that is, avoid to be formed
Shallow trench isolation there is vertical portion, be unfavorable for the filling of oxide so as to also avoid vertical portion, cause shallow channel
There is the problem in space in isolation.Carry out reprocessing afterwards to the first fin structure and form the second fin structure so that the second fin
The side wall of the Part I of structure meets fin formula field effect transistor institute perpendicular to the surface place plane of the shallow trench isolation
The structure of needs.Finally, greatly improve the stability of device.
Chinese patent (publication number：CN103515282A a kind of fin field-effect transistor (FinFET) and its system) are disclosed
Method, the transistor manufacture method include：Extend first and second fin for forming fin field-effect transistor from semiconductor substrate, wherein
Shallow trench isolation region is located between first and second fin, and has a distance between first, second fin upper surface；There is provided first
With the upper surface and side surface of first and second fin of the second fin extension on the upper surface higher than shallow trench isolation region
On；Portion of material is removed from shallow trench isolation region, to increase between shallow trench isolation region upper surface and first, second fin upper table
The distance between face；Deposition compliance stress dielectric material is on first, second fin with shallow trench isolation region；Reflow compliance
Stress dielectric material.The invention can reduce bridge joint phenomenon and improve the selective epitaxial growth techniques effect of fin field-effect transistor
Rate.
Above-mentioned two pieces patent is not recorded the present invention and realizes forming vertical bipolar in fin formula field effect transistor processing procedure
The technical scheme taken by transistor.
The content of the invention
For above-mentioned problem, the present invention forms the side of vertical bipolar transistor in disclosing a kind of FinFET processing procedures
Method, forms vertical bipolar transistor in FinFET processing procedures to overcome, and then affects integrated circuit
The problem of function.
To achieve these goals, the application forms the side of vertical bipolar transistor in describing a kind of FinFET processing procedures
Method, comprises the steps：
A substrate with the first conduction type is provided, the substrate surface is formed with some strip fins being parallel to each other
There is between structure, and the adjacent fin structure isolation channel, some strip fin structures being parallel to each other are divided
For first set fin structure and second set of fin structure；
Some transverse concave grooves being parallel to each other are prepared, by the first set fin structure along perpendicular to strip fin knot
The direction of structure length is blocked to form first area and be located at the first area both sides along the isolation channel length direction
Second area；
After insulating barrier is prepared in the isolation channel and the transverse concave groove, in the lining below the first area
The well region with the second conduction type is formed in bottom；
Second set of fin structure, the fin structure positioned at part in the first area are carried out the first conduction type from
After son doping, continuing to be pointed to remaining fin structure in the first area carries out the ion doping of the second conduction type；
Continue follow-up preparation technology, form the bipolar transistor；
Wherein, the emitter structure of the bipolar transistor includes conductive doped with first in the first area
The fin structure of the ion of type, the base structure of the bipolar transistor include the fin of the ion doped with the second conduction type
Structure, the collector structure of the bipolar transistor include the fin structure of the remaining ion doped with the first conduction type.
The method that vertical bipolar transistor is formed in above-mentioned FinFET processing procedures, wherein, the material of the substrate is P
Type silicon.
The method that vertical bipolar transistor is formed in above-mentioned FinFET processing procedures, wherein, it is described that there is the first conductive-type
The ion of type is p-type ion, and the ion with the second conduction type is N-type ion.
The method that vertical bipolar transistor is formed in above-mentioned FinFET processing procedures, wherein, the bipolar transistor base
Fin structure of the fin structure in the structure of pole in the emitter bipolar transistor structure.
The method that vertical bipolar transistor is formed in above-mentioned FinFET processing procedures, wherein, methods described also includes, to institute
State second set of fin structure, the fin structure positioned at part in the first area carry out the first conduction type ion doping it is same
When, the ion doping of the first conduction type is also carried out to the fin structure in the second area.
The method that vertical bipolar transistor is formed in above-mentioned FinFET processing procedures, wherein, spin coating photoresist simultaneously carries out light
Carving technology is adopted and is inclined to expose second set of fin structure, after the upper surface of the fin structure of part in the first area
Oblique ion injection technique carries out the ion doping of the first conduction type to the exposed region.
The method that vertical bipolar transistor is formed in above-mentioned FinFET processing procedures, wherein, spin coating photoresist simultaneously carries out light
Carving technology to expose in the first area after the upper surface of remaining fin structure, using angle-tilt ion injection technique to this
Exposed region carries out the ion doping of the second conduction type.
The method that vertical bipolar transistor is formed in above-mentioned FinFET processing procedures, wherein, prepare the side of the insulating barrier
Method includes：
The fill insulant in the isolation channel and the transverse concave groove；
Adopt dry etch process to return the insulant is carved with by the part side of the lateral channel and the transverse concave groove
Wall is exposed, and the remaining insulant forms the insulating barrier.
The method that vertical bipolar transistor is formed in above-mentioned FinFET processing procedures, wherein, the bipolar transistor
Emitter structure does not form the region of the well region with the second conduction type in also including the substrate.
The method that vertical bipolar transistor is formed in above-mentioned FinFET processing procedures, wherein, the substrate is tied with the fin
Structure is integral type structure.
Foregoing invention has the advantage that or beneficial effect：
The invention discloses a kind of method that vertical bipolar transistor is formed in FinFET processing procedures, by selectively existing
The method of zones of different doping, using existing FinFET structure, forms vertical bipolar transistor, so as to increased integrated electricity
The function on road.
It is concrete to illustrate
By reading the detailed description made to non-limiting example with reference to the following drawings, the present invention and its feature, outward
Shape and advantage will become more apparent.In whole accompanying drawings, identical labelling indicates identical part.Not can according to than
Example draws accompanying drawing, it is preferred that emphasis is illustrate the purport of the present invention.
Fig. 1-12 is that the flowage structure for forming vertical bipolar transistor in the embodiment of the present invention in FinFET processing procedures is illustrated
Figure；
Fig. 3 is the generalized section in Fig. 2 at AA；
Fig. 5 is the generalized section in Fig. 4 at BB；
Fig. 7 is the generalized section in Fig. 6 at CC；
Figure 10 is the generalized section in Fig. 9 at DD；
Figure 11 is the generalized section in Figure 10 at EE.
Specific embodiment
The present invention is further illustrated with specific embodiment below in conjunction with the accompanying drawings, but not as the limit of the present invention
It is fixed.
Fig. 1-12 is that the flowage structure for forming vertical bipolar transistor in the embodiment of the present invention in FinFET processing procedures is illustrated
Figure；As shown in figs. 1-12：
A kind of the present embodiment forms vertical bipolar transistor method in being related to FinFET processing procedures, comprises the steps：
Step S1, there is provided one has the semiconductor base 100 of the first conduction type, in an embodiment of the present invention, above-mentioned
The material of semiconductor base 100 is that P-type silicon, i.e. the first conduction type are p-type, structure as shown in Figure 1.
Step S2, the above-mentioned semiconductor base 100 of partial etching form substrate 101 and positioned at the several of 101 surface of substrate
Strip fin structure 102, as above-mentioned substrate 100 and fin structure 102 are that the etching of semiconductor base 100 is formed, therefore above-mentioned lining
Bottom 100 is have isolation channel 103 between integral type structure, and adjacent fin structure 102 with fin structure 102, will be above-mentioned some
The strip fin structure 102 being parallel to each other be divided into first set fin structure 1021 (first set fin structure is not conveniently identified in figure,
Braces covers part isolation channel, but actually only includes fin structure) and second set of fin structure 1022 (in figure, do not facilitate mark
Go out second set of fin structure, braces covers part isolation channel, but actually only includes fin structure), second set of fin structure 1022
Positioned at the both sides of first set fin structure 1021, in an embodiment of the present invention, above-mentioned some strip fin structures being parallel to each other
102 can be divided into including the first set fin structure of some fin structures and including remaining fin structure according to concrete technology demand
Second set of fin structure, structure as shown in Figures 2 and 3.
In an embodiment of the present invention, as the material of semiconductor base 100 is P-type silicon, therefore some fin structures 102
P-type silicon is with the material of substrate 101.
In an embodiment of the present invention, first set fin structure 1021 includes 3 fin structures 102, second set of fin structure 1022
Including 4 fin structures 102, and second set of fin structure 1022 is divided into two parts by first set fin structure 1021, this two parts
Respectively positioned at the both sides of first set fin structure 1021.
Step S3, partial etching first set fin structure 102 form some transverse concave grooves 104 being parallel to each other, by residue
1021 ＇ of first set fin structure to form first area (in Fig. 4 along blocking perpendicular to the direction of 102 length of strip fin structure
The region enclosed by dotted line 1) and along 103 length direction of isolation channel be located at the first area both sides second area (in Fig. 4
The region enclosed by dotted line 2), in an embodiment of the present invention, first area is between outermost two transverse concave grooves
Region, second area are the region outside outermost two transverse concave grooves, that is to say, that the second area is above-mentioned surplus
Regions of remaining 1021 ＇ of first set fin structure in addition to the region being located between outermost two transverse concave grooves, such as Figure 4 and 5
Shown structure.
Step S4, is continued at fill insulant in above-mentioned isolation channel 103 and transverse concave groove 104, and is carved using dry method
Etching technique is returned after carving the insulant so that the partial sidewall of isolation channel 103 and transverse concave groove 104 to be exposed, remaining institute
State insulant formed insulating barrier 105 cover above-mentioned isolation channel 103 and transverse concave groove 104 bottom and partial sidewall (by
Accompanying drawing in this step is that, based on above-mentioned accompanying drawing 5 and 6, therefore the mark of accompanying drawing 5 and 6 is seen in the position of transverse concave groove and isolation channel
Know, here is just not identified), structure as shown in Figures 6 and 7.
Preferably, the material of above-mentioned insulant be silicon dioxide, return carve the insulant a purpose be easy for after
Ion doping in continuous step S5.
Step S5, continues to carrying out height in positioned at the substrate below first area (region that dotted line 1 is surrounded in such as Fig. 4)
The ion doping of the second conduction type of concentration has the second conduction type to be formed in the substrate below the first area
Well region 106, in an embodiment of the present invention, the ion of the second conduction type is N-type ion, the i.e. well region of second conduction type
For N traps, in this step or before this step is carried out, also including the grid polycrystalline silicon in other regions is removed the step of, such as
Structure shown in Fig. 8.
Step S6, spin coating photoresist simultaneously carry out photoetching process to expose second set of fin structure 1022, in first area
After the upper surface of partial fin structure, using angle-tilt ion injection technique the exposed region is carried out the first conduction type from
Son doping, wherein, have doped with not formed in second set of 1022 ＇ of fin structure and 101 ＇ of substrate of the ion of the first conduction type
The region of the well region 106 of the second conduction type constitutes collector area, doped with the first conduction type ion positioned at the firstth area
In domain, the fin structure of part is (i.e. in remaining 1021 ＇ of first set fin structure most between two transverse concave grooves of inner side
Fin structure) emitter region is constituted, in an embodiment of the present invention, the residue being only pointed to most between two transverse concave grooves of inner side
1021 ＇ of first set fin structure in a fin structure carry out the first conduction type ion doping formed emitter region, in figure
1021 ＇ ＇ for the first set fin structure after the ion of the first conduction type is doped with this step, as shown in Figure 9 and Figure 10
Structure.
Preferably, to above-mentioned second set of fin structure 1022, that the fin structure positioned at part in first area carries out first is conductive
While the ion doping of type, the ion doping of the first conduction type is also carried out to the fin structure in second area, after doping
Second set of 1022 ＇ of fin structure, 101 ＇ of substrate in do not formed the well region 106 with the second conduction type region and doping after
Second set of 1022 ＇ of fin structure constitute collector area.
Step S7, spin coating photoresist simultaneously carry out photoetching process to expose the remaining fin structure in above-mentioned first area
After the upper surface of (i.e. undoped in first area fin structure), the exposed region is entered using angle-tilt ion injection technique
The ion doping of the second conduction type of row, wherein, it is doped with the fin in first area after the ion of the second conduction type
Structure and the above-mentioned well region 106 with the second conduction type constitute base region, and in figure, 1023 lead to be doped with second in this step
First set fin structure after the ion of electric type, structure as is illustrated by figs. 11 and 12.
Step S8, continues follow-up preparation technology, forms PNP bipolar transistors, and this step includes drawing metal electrode
Etc. preparation technology, as the present invention is not related to the improvement of the part, therefore will not be described here.
Wherein, the emitter structure of bipolar transistor include in first area doped with the first conduction type from
The fin structure of son, the base structure of bipolar transistor includes the fin structure of the ion doped with the second conduction type, ambipolar
The collector structure of transistor includes the fin structure of the remaining ion doped with the first conduction type, and bipolar transistor base
Fin structure of the fin structure in the structure of pole in emitter bipolar transistor structure, it is in an embodiment of the present invention, bipolar
The emitter structure of transistor npn npn does not form the region of the well region with the second conduction type in also including above-mentioned substrate.
In sum, the invention discloses a kind of method that vertical bipolar transistor is formed in FinFET processing procedures, passes through
Selectively in the method for zones of different doping, using existing FinFET structure, vertical bipolar transistor is formed (for example
PNP bipolar transistors), so as to increased the function of integrated circuit.
It should be appreciated by those skilled in the art that those skilled in the art are can be with reference to prior art and above-described embodiment
The change case is realized, be will not be described here.Such change case has no effect on the flesh and blood of the present invention, and here is not superfluous
State.
Above presently preferred embodiments of the present invention is described.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment and structure that do not describe in detail to the greatest extent are construed as giving reality with the common mode in this area
Apply；Any those of ordinary skill in the art, under without departing from technical solution of the present invention ambit, all using the disclosure above
Methods and techniques content make many possible variations and modification to technical solution of the present invention, or be revised as equivalent variations etc.
Effect embodiment, this has no effect on the flesh and blood of the present invention.Therefore, every content without departing from technical solution of the present invention, foundation
The technical spirit of the present invention still falls within the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification
In the range of technical scheme protection.
Claims (10)
1. a kind of method that vertical bipolar transistor is formed in FinFET processing procedures, it is characterised in that comprise the steps：
A substrate with the first conduction type is provided, the substrate surface is formed with some strip fin knots being parallel to each other
There is between structure, and the adjacent fin structure isolation channel, some strip fin structures being parallel to each other are divided into
First set fin structure and second set of fin structure；
Some transverse concave grooves being parallel to each other are prepared, by the first set fin structure along long perpendicular to the strip fin structure
The direction of degree is blocked to form first area and the second of the first area both sides are located at along the isolation channel length direction
Region；
After insulating barrier is prepared in the isolation channel and the transverse concave groove, in the substrate below the first area
Form the well region with the second conduction type；
The ion that second set of fin structure, the fin structure positioned at part in the first area carry out the first conduction type is mixed
After miscellaneous, continuing to be pointed to remaining fin structure in the first area carries out the ion doping of the second conduction type；
Continue follow-up preparation technology, form the bipolar transistor；
Wherein, the emitter structure of the bipolar transistor is included in the first area doped with the first conduction type
Ion fin structure, the base structure of the bipolar transistor include the ion doped with the second conduction type fin knot
Structure, the collector structure of the bipolar transistor include the fin structure of the remaining ion doped with the first conduction type.
2. the method that vertical bipolar transistor is formed in FinFET processing procedures as claimed in claim 1, it is characterised in that described
The material of substrate is P-type silicon.
3. the method that vertical bipolar transistor is formed in FinFET processing procedures as claimed in claim 1, it is characterised in that described
Ion with the first conduction type is p-type ion, and the ion with the second conduction type is N-type ion.
4. the method that vertical bipolar transistor is formed in FinFET processing procedures as claimed in claim 1, it is characterised in that described
Fin structure of the fin structure in bipolar transistor base structure in the emitter bipolar transistor structure.
5. the method that vertical bipolar transistor is formed in FinFET processing procedures as claimed in claim 1, it is characterised in that described
Method also includes, carries out the first conduction type to second set of fin structure, the fin structure positioned at part in the first area
Ion doping while, the ion doping of the first conduction type is also carried out to the fin structure in the second area.
6. the method that vertical bipolar transistor is formed in FinFET processing procedures as claimed in claim 1, it is characterised in that spin coating
Photoresist and carry out photoetching process with expose second set of fin structure, positioned in the first area fin structure of part it is upper
Behind surface, the ion doping of the first conduction type is carried out using angle-tilt ion injection technique to the exposed region.
7. the method that vertical bipolar transistor is formed in FinFET processing procedures as claimed in claim 1, it is characterised in that spin coating
Photoresist simultaneously carries out photoetching process to expose in the first area after the upper surface of remaining fin structure, using incline from
Sub- injection technique carries out the ion doping of the second conduction type to the exposed region.
8. the method that vertical bipolar transistor is formed in FinFET processing procedures as claimed in claim 1, it is characterised in that prepare
The method of the insulating barrier includes：
The fill insulant in the isolation channel and the transverse concave groove；
Adopt dry etch process to return the insulant is carved so that the partial sidewall of the lateral channel and the transverse concave groove to be given
To expose, the remaining insulant forms the insulating barrier.
9. the method that vertical bipolar transistor is formed in FinFET processing procedures as claimed in claim 1, it is characterised in that described
The emitter structure of bipolar transistor does not form the area of the well region with the second conduction type in also including the substrate
Domain.
10. the method that vertical bipolar transistor is formed in FinFET processing procedures as claimed in claim 1, it is characterised in that institute
It is integral type structure that substrate is stated with the fin structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410218419.4A CN104022032B (en) | 2014-05-22 | 2014-05-22 | The method that vertical bipolar transistor is formed in FinFET processing procedures |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410218419.4A CN104022032B (en) | 2014-05-22 | 2014-05-22 | The method that vertical bipolar transistor is formed in FinFET processing procedures |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104022032A CN104022032A (en) | 2014-09-03 |
| CN104022032B true CN104022032B (en) | 2017-04-05 |
Family
ID=51438729
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410218419.4A Active CN104022032B (en) | 2014-05-22 | 2014-05-22 | The method that vertical bipolar transistor is formed in FinFET processing procedures |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104022032B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI726155B (en) * | 2017-09-14 | 2021-05-01 | 聯華電子股份有限公司 | Bipolar junction transistor |
| US10665702B2 (en) | 2017-12-27 | 2020-05-26 | Samsung Electronics Co., Ltd. | Vertical bipolar transistors |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8258602B2 (en) * | 2009-01-28 | 2012-09-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bipolar junction transistors having a fin |
| CN103187438A (en) * | 2011-12-28 | 2013-07-03 | 台湾积体电路制造股份有限公司 | Fin-like BJT |
| CN103378160A (en) * | 2012-04-25 | 2013-10-30 | 国际商业机器公司 | Device structures compatible with fin-type field-effect transistor technologies |
| CN103489863A (en) * | 2012-06-12 | 2014-01-01 | 台湾积体电路制造股份有限公司 | Homo-junction diode structures using fin field effect transistor processing |
| CN103811484A (en) * | 2012-11-15 | 2014-05-21 | 台湾积体电路制造股份有限公司 | ESD Devices Comprising Semiconductor Fins |
-
2014
- 2014-05-22 CN CN201410218419.4A patent/CN104022032B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8258602B2 (en) * | 2009-01-28 | 2012-09-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bipolar junction transistors having a fin |
| CN103187438A (en) * | 2011-12-28 | 2013-07-03 | 台湾积体电路制造股份有限公司 | Fin-like BJT |
| CN103378160A (en) * | 2012-04-25 | 2013-10-30 | 国际商业机器公司 | Device structures compatible with fin-type field-effect transistor technologies |
| CN103489863A (en) * | 2012-06-12 | 2014-01-01 | 台湾积体电路制造股份有限公司 | Homo-junction diode structures using fin field effect transistor processing |
| CN103811484A (en) * | 2012-11-15 | 2014-05-21 | 台湾积体电路制造股份有限公司 | ESD Devices Comprising Semiconductor Fins |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104022032A (en) | 2014-09-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105103294B (en) | For improving the device architecture of the encapsulation of vertical field-effect device and method | |
| US9780003B2 (en) | Bipolar junction transistor formed on fin structures | |
| CN104576743B (en) | Power MOS (Metal Oxide Semiconductor) device with groove and its manufacture method | |
| CN104733531A (en) | Dual oxide trench gate power mosfet using oxide filled trench | |
| US10516018B2 (en) | Super junction MOSFET device and semiconductor chip | |
| US20140264586A1 (en) | Bootstrap fet and method of manufacturing the same | |
| JPWO2014013618A1 (en) | Semiconductor device and manufacturing method thereof | |
| CN104637821A (en) | Manufacturing method of super junction device | |
| CN102593178B (en) | Semiconductor device with super junction structure and manufacturing method thereof | |
| JP6608461B2 (en) | Insulated gate bipolar transistor and manufacturing method thereof | |
| CN105118852A (en) | Super junction structure, super junction MOSFET and manufacturing method thereof | |
| CN107170688B (en) | A kind of slot type power device and preparation method thereof | |
| CN108010963B (en) | Vertical channel semiconductor device with reduced saturation voltage | |
| CN104022032B (en) | The method that vertical bipolar transistor is formed in FinFET processing procedures | |
| CN104282739A (en) | Bipolar Transistor and a Method for Manufacturing a Bipolar Transistor | |
| CN105977285A (en) | Semiconductor device and method of manufacturing the same | |
| CN106409890B (en) | The forming method of fin bipolar junction transistor | |
| CN104319284A (en) | Semiconductor device structure and manufacturing method thereof | |
| CN104332488B (en) | Semiconductor devices terminal, semiconductor devices and its manufacture method | |
| TW201409692A (en) | Semiconductor device and fabricating method thereof | |
| CN108063159A (en) | The terminal structure of semiconductor power device, semiconductor power device and preparation method thereof | |
| CN107994067A (en) | The terminal structure and preparation method thereof of semiconductor power device, semiconductor power device | |
| CN103779416B (en) | The power MOSFET device of a kind of low VF and manufacture method thereof | |
| CN108091575B (en) | Junction field effect transistor and manufacturing method thereof | |
| CN206976352U (en) | A kind of power semiconductor for reducing conducting resistance |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |