CN104022032A - Method for forming vertical bipolar transistor in FinFET manufacturing process - Google Patents
Method for forming vertical bipolar transistor in FinFET manufacturing process Download PDFInfo
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- CN104022032A CN104022032A CN201410218419.4A CN201410218419A CN104022032A CN 104022032 A CN104022032 A CN 104022032A CN 201410218419 A CN201410218419 A CN 201410218419A CN 104022032 A CN104022032 A CN 104022032A
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- 238000000034 method Methods 0.000 title claims abstract description 89
- 238000004519 manufacturing process Methods 0.000 title abstract description 5
- 238000012545 processing Methods 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 23
- 238000002955 isolation Methods 0.000 claims description 20
- 230000008569 process Effects 0.000 claims description 9
- 238000005516 engineering process Methods 0.000 claims description 8
- 239000011810 insulating material Substances 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000004528 spin coating Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000002360 preparation method Methods 0.000 claims description 4
- 230000005669 field effect Effects 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 9
- 239000000243 solution Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000008280 blood Substances 0.000 description 2
- 210000004369 blood Anatomy 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6625—Lateral transistors
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Abstract
The invention discloses a method for forming a vertical bipolar structure in the FinFET manufacturing process. By a method of selectively doping in different areas and by the utilization of an existed FinFET structure, a vertical PNP bipolar transistor is formed, thus increasing functions of an integrated circuit.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of method that forms vertical bipolar transistor in FinFET processing procedure.
Background technology
At present, fin formula field effect transistor (FinFET), as a kind of brand-new semiconductor device structure, in order to improve the performance of CMOS (Complementary Metal Oxide Semiconductor) field-effect transistor (CMOS), is about to become the main flow technique of the following technology node of 20 nanometer.The manufacturing process of this structure is complicated, so that the vertical bipolar transistor that is easy to obtain in traditional planar technique is applied to fin formula field effect transistor and is but difficult to realize, and bipolar transistor is prerequisite device in Analog Circuit Design, therefore can not in FinFET processing procedure, form the function that bipolar transistor can reduce integrated circuit.
Therefore, how to find a kind of method that forms bipolar transistor in fin formula field effect transistor processing procedure, and then the function of increase integrated circuit becomes the direction that those skilled in the art endeavour research.
Chinese patent (publication number: CN103515282A) disclose a kind of fin formula field effect transistor and forming method thereof, the fin formula field effect transistor that this invention provides, the sidewall of the shallow trench isolation that forms has gradient, avoided formed shallow trench isolation to there is vertical portion, thereby also just avoided vertical portion to be unfavorable for the filling of oxide, caused the problem that has space in shallow trench isolation.Afterwards the first fin formula structure is reprocessed and formed the second fin formula structure, make the sidewall of first of the second fin formula structure perpendicular to the surperficial place plane of described shallow trench isolation, meet the needed structure of fin formula field effect transistor.Finally, improved greatly the stability of device.
Chinese patent (publication number: CN103515282A) disclose a kind of fin formula field-effect transistor (FinFET) and method for making thereof, this transistor manufacture method comprises: from extending to form first and second fin of fin formula field-effect transistor on semiconductor substrate, wherein shallow isolating trough region is between first and second fin, and and first, second fin upper surface between there is a distance; Provide on the upper surface and side surface of first and second first and second fin of fin extension on the upper surface higher than shallow isolating trough region; From shallow isolating trough region, remove part material, to increase the distance between shallow isolating trough region upper surface and first, second fin upper surface; Deposition compliance stress dielectric material is on first, second fin and shallow isolating trough region; Reflow compliance stress dielectric material.This invention can reduce bridge joint phenomenon and improve the selective epitaxial growth technical efficiency of fin formula field-effect transistor.
Above-mentioned two patents all not notebook invention realize and in fin formula field effect transistor processing procedure, form the technical scheme that vertical bipolar transistor is taked.
Summary of the invention
For the problem of above-mentioned existence, the present invention discloses a kind of method that forms vertical bipolar transistor in FinFET processing procedure, is difficult for forming vertical bipolar transistor in FinFET processing procedure, and then affects the problem of the function of integrated circuit to overcome in prior art.
To achieve these goals, the application has recorded a kind of method that forms vertical bipolar transistor in FinFET processing procedure, comprises the steps:
One substrate with the first conduction type is provided, described substrate surface is formed with some strip fin structures that are parallel to each other, and between adjacent described fin structure, there is isolation channel, described some strip fin structures that are parallel to each other are divided into first set fin structure and the second cover fin structure;
Prepare some transverse concave grooves that are parallel to each other, so that the second area that forms first area and be positioned at both sides, described first area along described isolation channel length direction is blocked in described first set fin structure edge perpendicular to the direction of described strip fin structure length;
In described isolation channel and described transverse concave groove, prepare after insulating barrier, at the substrate being arranged in below described first area, form the well region with the second conduction type;
Described the second cover fin structure, the fin structure that is arranged in described first area part are carried out after the ion doping of the first conduction type, continue to carry out being arranged in the remaining fin structure in described first area the ion doping of the second conduction type;
Continue follow-up preparation technology, form described bipolar transistor;
Wherein, the emitter structure of described bipolar transistor comprises and is arranged in described first area doped with the fin structure of the ion of the first conduction type, the base structure of described bipolar transistor comprises the fin structure doped with the ion of the second conduction type, and the collector structure of described bipolar transistor comprises the fin structure of the remaining ion doped with the first conduction type.
In above-mentioned FinFET processing procedure, form the method for vertical bipolar transistor, wherein, the material of described substrate is P type silicon.
In above-mentioned FinFET processing procedure, form the method for vertical bipolar transistor, wherein, described in there is the first conduction type ion be P type ion, described in there is the second conduction type ion be N-type ion.
In above-mentioned FinFET processing procedure, form the method for vertical bipolar transistor, wherein, the fin structure in described bipolar transistor base structure is around the fin structure in described emitter bipolar transistor structure.
In above-mentioned FinFET processing procedure, form the method for vertical bipolar transistor, wherein, described method also comprises, when described the second cover fin structure, the fin structure that is arranged in described first area part are carried out to the ion doping of the first conduction type, the fin structure in described second area is also carried out to the ion doping of the first conduction type.
In above-mentioned FinFET processing procedure, form the method for vertical bipolar transistor, wherein, spin coating photoresist also carries out photoetching process to expose described the second cover fin structure, to be arranged in after the upper surface of described first area fin structure partly, adopts angle-tilt ion injection technique the region of this exposure to be carried out to the ion doping of the first conduction type.
In above-mentioned FinFET processing procedure, form the method for vertical bipolar transistor, wherein, spin coating photoresist also carries out photoetching process and is arranged in after the upper surface of the remaining fin structure in described first area to expose, and adopts angle-tilt ion injection technique the region of this exposure to be carried out to the ion doping of the second conduction type.
In above-mentioned FinFET processing procedure, form the method for vertical bipolar transistor, wherein, the method for preparing described insulating barrier comprises:
Fill insulant in described isolation channel and described transverse concave groove;
Adopt dry etch process to return and carve this insulating material so that the partial sidewall of described lateral channel and described transverse concave groove is exposed, remaining described insulating material forms described insulating barrier.
In above-mentioned FinFET processing procedure, form the method for vertical bipolar transistor, wherein, the emitter structure of described bipolar transistor also comprises in described substrate the region described in not forming with the well region of the second conduction type.
In above-mentioned FinFET processing procedure, form the method for vertical bipolar transistor, wherein, described substrate and described fin structure are integral type structure.
Foregoing invention tool has the following advantages or beneficial effect:
The invention discloses a kind of method that forms vertical bipolar transistor in FinFET processing procedure, by selectively, in the method for zones of different doping, utilize existing FinFET structure, form vertical bipolar transistor, thereby increased the function of integrated circuit.
Concrete accompanying drawing explanation
By reading the detailed description of non-limiting example being done with reference to the following drawings, the present invention and feature thereof, profile and advantage will become more apparent.In whole accompanying drawings, identical mark is indicated identical part.Can proportionally not draw accompanying drawing, focus on illustrating purport of the present invention.
Fig. 1-12nd, forms the flowage structure schematic diagram of vertical bipolar transistor in FinFET processing procedure in the embodiment of the present invention;
Fig. 3 is the generalized section at AA place in Fig. 2;
Fig. 5 is the generalized section at BB place in Fig. 4;
Fig. 7 is the generalized section at CC place in Fig. 6;
Figure 10 is the generalized section at DD place in Fig. 9;
Figure 11 is the generalized section at EE place in Figure 10.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment, the present invention is further illustrated, but not as limiting to the invention.
Fig. 1-12nd, forms the flowage structure schematic diagram of vertical bipolar transistor in FinFET processing procedure in the embodiment of the present invention; As shown in Fig. 1-12:
The present embodiment relates to a kind of method that forms vertical bipolar transistor in FinFET processing procedure, comprises the steps:
Step S1, provides a semiconductor base 100 with the first conduction type, and in an embodiment of the present invention, the material of above-mentioned semiconductor base 100 is P type silicon, and the first conduction type is P type, structure as shown in Figure 1.
Step S2, the above-mentioned semiconductor base 100 of partial etching forms substrate 101 and is positioned at several strip fin structures 102 on these substrate 101 surfaces, because above-mentioned substrate 100 and fin structure 102 are that semiconductor base 100 etchings form, therefore above-mentioned substrate 100 is integral type structure with fin structure 102, and there is isolation channel 103 between adjacent fin structure 102, above-mentioned some strip fin structures 102 that are parallel to each other are divided into first set fin structure 1021 and (in figure, conveniently do not identify first set fin structure, braces has been contained part isolation channel, but the actual fin structure that only includes) and second cover fin structure 1022 (in figure, conveniently do not identify the second cover fin structure, braces has been contained part isolation channel, but the actual fin structure that only includes), the second cover fin structure 1022 is positioned at the both sides of first set fin structure 1021, in an embodiment of the present invention, above-mentioned some strip fin structures 102 being parallel to each other can be divided into the second cover fin structure that comprises the first set fin structure of some fin structures and comprise remaining fin structure according to concrete technology demand, structure as shown in Figures 2 and 3.
In an embodiment of the present invention, because the material of semiconductor base 100 is P type silicon, so the material of these some fin structures 102 and substrate 101 is P type silicon.
In an embodiment of the present invention, first set fin structure 1021 comprises 3 fin structures 102, the second cover fin structure 1022 comprises 4 fin structures 102, and first set fin structure 1021 is divided into two parts by the second cover fin structure 1022, and these two parts lay respectively at the both sides of first set fin structure 1021.
Step S3, partial etching first set fin structure 102 forms some transverse concave grooves that are parallel to each other 104, with by remaining first set fin structure 1021 ＇ along block the second area (region of being enclosed as Fig. 4 dotted line 2) that forms first area (region of being enclosed as dotted line in Fig. 4 1) and be arranged in these both sides, first area along isolation channel 103 length directions perpendicular to the direction of strip fin structure 102 length, in an embodiment of the present invention, first area is the region between outermost two transverse concave grooves, second area is the region being positioned at outside outermost two transverse concave grooves, that is to say, this second area is the regions of above-mentioned remaining first set fin structure 1021 ＇ except the region between outermost two transverse concave grooves, structure as shown in Figures 4 and 5.
Step S4, continue at fill insulant in above-mentioned isolation channel 103 and transverse concave groove 104, and adopt dry etch process to return to carve this insulating material with after the partial sidewall of isolation channel 103 and transverse concave groove 104 is exposed, the bottom of the remaining described insulating material formation insulating barrier 105 above-mentioned isolation channel 103 of covering and transverse concave groove 104 and partial sidewall are (because the accompanying drawing in this step is based on above-mentioned accompanying drawing 5 and 6, therefore the sign that accompanying drawing 5 and 6 are seen in the position of transverse concave groove and isolation channel, at this, just will not identify), structure as shown in Figures 6 and 7.
Preferably, the material of above-mentioned insulating material is silicon dioxide, and an object of returning this insulating material at quarter is the ion doping of being convenient in subsequent step S5.
Step S5, the ion doping that continuation is carried out the second conduction type of high concentration to the substrate being arranged in below, first area (region surrounding as Fig. 4 dotted line 1) forms the well region 106 with the second conduction type with the substrate below this first area, in an embodiment of the present invention, the ion of the second conduction type is N-type ion, the well region of this second conduction type is N trap, in this step or before carrying out this step, also comprise the step that removes the grid polycrystalline silicon in other regions, structure as shown in Figure 8.
Step S6, spin coating photoresist also carries out photoetching process to expose the second cover fin structure 1022, be arranged in after the upper surface of first area fin structure partly, adopt angle-tilt ion injection technique the region of this exposure to be carried out to the ion doping of the first conduction type, wherein, doped with not forming the formation collector area, region of the well region 106 with the second conduction type in the second cover fin structure 1022 ＇ of the ion of the first conduction type and substrate 101 ＇, doped with the fin structure that is arranged in first area part of the ion of the first conduction type (i.e. the fin structure of remaining first set fin structure 1021 ＇ between two transverse concave grooves of inner side), form emitter region, in an embodiment of the present invention, the ion doping that only a fin structure in remaining first set fin structure 1021 ＇ between two transverse concave grooves of inner side is carried out to the first conduction type forms emitter region, the first set fin structure of 1021 ＇ ＇ after for the ion for first conduction type that adulterated in this step in figure, structure as shown in Figure 9 and Figure 10.
Preferably, when above-mentioned the second cover fin structure 1022, the fin structure that is arranged in first area part are carried out to the ion doping of the first conduction type, fin structure in second area is also carried out to the ion doping of the first conduction type, in the cover of second after doping fin structure 1022 ＇, substrate 101 ＇, do not form the region of the well region 106 with the second conduction type and the second cover fin structure 1022 ＇ after doping and form collector area.
Step S7, spin coating photoresist also carries out photoetching process and is arranged in after the upper surface of the remaining fin structure in above-mentioned first area (being the fin structure that first area is not doped) to expose, adopt angle-tilt ion injection technique the region of this exposure to be carried out to the ion doping of the second conduction type, wherein, the fin structure that is positioned at first area and the above-mentioned well region 106 with the second conduction type that have adulterated after the ion of the second conduction type form base regions, in figure, 1023 is the first set fin structure after the ion of second conduction type that adulterated in this step, structure as shown in Figure 11 and Figure 12.
Step S8, continues follow-up preparation technology, forms PNP bipolar transistor, and this step comprises preparation technologies such as drawing metal electrode, because the present invention does not relate to the improvement of this part, therefore do not repeat them here.
Wherein, the emitter structure of bipolar transistor comprises and is arranged in first area doped with the fin structure of the ion of the first conduction type, the base structure of bipolar transistor comprises the fin structure doped with the ion of the second conduction type, the collector structure of bipolar transistor comprises the fin structure of the remaining ion doped with the first conduction type, and the fin structure in bipolar transistor base structure is around the fin structure in emitter bipolar transistor structure, in an embodiment of the present invention, the emitter structure of bipolar transistor also comprises the region that does not form the well region with the second conduction type in above-mentioned substrate.
In sum, the invention discloses a kind of method that forms vertical bipolar transistor in FinFET processing procedure, by the method for selectively adulterating in zones of different, utilize existing FinFET structure, form vertical bipolar transistor (for example PNP bipolar transistor), thereby increased the function of integrated circuit.
It should be appreciated by those skilled in the art that those skilled in the art, realizing described variation example in conjunction with prior art and above-described embodiment, do not repeat at this.Such variation example does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It will be appreciated that, the present invention is not limited to above-mentioned specific implementations, and the equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or being revised as the equivalent embodiment of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (10)
1. in FinFET processing procedure, form a method for vertical bipolar transistor, it is characterized in that, comprise the steps:
One substrate with the first conduction type is provided, described substrate surface is formed with some strip fin structures that are parallel to each other, and between adjacent described fin structure, there is isolation channel, described some strip fin structures that are parallel to each other are divided into first set fin structure and the second cover fin structure;
Prepare some transverse concave grooves that are parallel to each other, so that the second area that forms first area and be positioned at both sides, described first area along described isolation channel length direction is blocked in described first set fin structure edge perpendicular to the direction of described strip fin structure length;
In described isolation channel and described transverse concave groove, prepare after insulating barrier, at the substrate being arranged in below described first area, form the well region with the second conduction type;
Described the second cover fin structure, the fin structure that is arranged in described first area part are carried out after the ion doping of the first conduction type, continue to carry out being arranged in the remaining fin structure in described first area the ion doping of the second conduction type;
Continue follow-up preparation technology, form described bipolar transistor;
Wherein, the emitter structure of described bipolar transistor comprises and is arranged in described first area doped with the fin structure of the ion of the first conduction type, the base structure of described bipolar transistor comprises the fin structure doped with the ion of the second conduction type, and the collector structure of described bipolar transistor comprises the fin structure of the remaining ion doped with the first conduction type.
2. in FinFET processing procedure as claimed in claim 1, form the method for vertical bipolar transistor, it is characterized in that, the material of described substrate is P type silicon.
3. in FinFET processing procedure as claimed in claim 1, form the method for vertical bipolar transistor, it is characterized in that, described in there is the first conduction type ion be P type ion, described in there is the second conduction type ion be N-type ion.
4. in FinFET processing procedure as claimed in claim 1, form the method for vertical bipolar transistor, it is characterized in that, the fin structure in described bipolar transistor base structure is around the fin structure in described emitter bipolar transistor structure.
5. in FinFET processing procedure as claimed in claim 1, form the method for vertical bipolar transistor, it is characterized in that, described method also comprises, when described the second cover fin structure, the fin structure that is arranged in described first area part are carried out to the ion doping of the first conduction type, the fin structure in described second area is also carried out to the ion doping of the first conduction type.
6. in FinFET processing procedure as claimed in claim 1, form the method for vertical bipolar transistor, it is characterized in that, spin coating photoresist also carries out photoetching process to expose described the second cover fin structure, to be arranged in after the upper surface of described first area fin structure partly, adopts angle-tilt ion injection technique the region of this exposure to be carried out to the ion doping of the first conduction type.
7. in FinFET processing procedure as claimed in claim 1, form the method for vertical bipolar transistor, it is characterized in that, spin coating photoresist also carries out photoetching process and is arranged in after the upper surface of the remaining fin structure in described first area to expose, and adopts angle-tilt ion injection technique the region of this exposure to be carried out to the ion doping of the second conduction type.
8. in FinFET processing procedure as claimed in claim 1, form the method for vertical bipolar transistor, it is characterized in that, the method for preparing described insulating barrier comprises:
Fill insulant in described isolation channel and described transverse concave groove;
Adopt dry etch process to return and carve this insulating material so that the partial sidewall of described lateral channel and described transverse concave groove is exposed, remaining described insulating material forms described insulating barrier.
9. in FinFET processing procedure as claimed in claim 1, form the method for vertical bipolar transistor, it is characterized in that, the emitter structure of described bipolar transistor also comprises in described substrate the region described in not forming with the well region of the second conduction type.
10. in FinFET processing procedure as claimed in claim 1, form the method for vertical bipolar transistor, it is characterized in that, described substrate and described fin structure are integral type structure.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10665702B2 (en) | 2017-12-27 | 2020-05-26 | Samsung Electronics Co., Ltd. | Vertical bipolar transistors |
| TWI726155B (en) * | 2017-09-14 | 2021-05-01 | 聯華電子股份有限公司 | Bipolar junction transistor |
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| US8258602B2 (en) * | 2009-01-28 | 2012-09-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bipolar junction transistors having a fin |
| CN103187438A (en) * | 2011-12-28 | 2013-07-03 | 台湾积体电路制造股份有限公司 | Fin-like BJT |
| CN103378160A (en) * | 2012-04-25 | 2013-10-30 | 国际商业机器公司 | Device structures compatible with fin-type field-effect transistor technologies |
| CN103489863A (en) * | 2012-06-12 | 2014-01-01 | 台湾积体电路制造股份有限公司 | Homo-junction diode structures using fin field effect transistor processing |
| CN103811484A (en) * | 2012-11-15 | 2014-05-21 | 台湾积体电路制造股份有限公司 | ESD Devices Comprising Semiconductor Fins |
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2014
- 2014-05-22 CN CN201410218419.4A patent/CN104022032B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8258602B2 (en) * | 2009-01-28 | 2012-09-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bipolar junction transistors having a fin |
| CN103187438A (en) * | 2011-12-28 | 2013-07-03 | 台湾积体电路制造股份有限公司 | Fin-like BJT |
| CN103378160A (en) * | 2012-04-25 | 2013-10-30 | 国际商业机器公司 | Device structures compatible with fin-type field-effect transistor technologies |
| CN103489863A (en) * | 2012-06-12 | 2014-01-01 | 台湾积体电路制造股份有限公司 | Homo-junction diode structures using fin field effect transistor processing |
| CN103811484A (en) * | 2012-11-15 | 2014-05-21 | 台湾积体电路制造股份有限公司 | ESD Devices Comprising Semiconductor Fins |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI726155B (en) * | 2017-09-14 | 2021-05-01 | 聯華電子股份有限公司 | Bipolar junction transistor |
| US10665702B2 (en) | 2017-12-27 | 2020-05-26 | Samsung Electronics Co., Ltd. | Vertical bipolar transistors |
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| CN104022032B (en) | 2017-04-05 |
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