CN103022087A - Semiconductor chip and production method thereof - Google Patents

Semiconductor chip and production method thereof Download PDF

Info

Publication number
CN103022087A
CN103022087A CN2011102873969A CN201110287396A CN103022087A CN 103022087 A CN103022087 A CN 103022087A CN 2011102873969 A CN2011102873969 A CN 2011102873969A CN 201110287396 A CN201110287396 A CN 201110287396A CN 103022087 A CN103022087 A CN 103022087A
Authority
CN
China
Prior art keywords
semiconductor
layer
type semiconductor
wafer
conductive type
Prior art date
Application number
CN2011102873969A
Other languages
Chinese (zh)
Inventor
朱江
盛况
Original Assignee
朱江
盛况
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 朱江, 盛况 filed Critical 朱江
Priority to CN2011102873969A priority Critical patent/CN103022087A/en
Publication of CN103022087A publication Critical patent/CN103022087A/en

Links

Abstract

The invention discloses a semiconductor chip in a super junction structure and a production method of the semiconductor chip. The device can be produced and manufactured by using fewer times of photolithographic technique and dry etching technique, a good columnar P type semiconductor and an N type semiconductor area and even impurity concentration distribution in vertical direction can be realized, and the reverse voltage endurance characteristic of the chip and the reliability of the device can be improved.

Description

A kind of semiconductor wafer and manufacture method thereof

Technical field

The present invention relates to a kind of semiconductor wafer and manufacture method thereof, particularly relate to and to realize that height is withstand voltage, semiconductor wafer and the manufacture method thereof of low on-resistance.

Background technology

Energy realization height is withstand voltage and semiconductor chip structure low on-resistance is to present the P type semiconductor of column and the structure that the N type semiconductor zone alternately is arranged side by side, and the P type semiconductor of column and N type semiconductor are perpendicular to wafer surface.Be set as desired value by impurity concentration and width with P type semiconductor and N type semiconductor, when applying reverse pressure drop, can realize high withstand voltage.This kind structure is called super-junction structure.

Known super-junction structure semiconductor chip structure and manufacture method are as follows:

The first, the certain thickness N-type epitaxial loayer of deposit arranges mask and injects p type impurity, and annealing forms the P-type conduction layer.Then repeatedly repeat above-mentioned technological process, form alternate configurations P type semiconductor and N type semiconductor zone.The semiconductor wafer manufacture craft of this kind super-junction structure is loaded down with trivial details, needs about 7 times photoetching implantation annealing technique, and the PN junction face presents waveform, affects the reverse voltage endurance of wafer.

The second, by a plurality of grooves of formation in the N-type epitaxial loayer, thereby the angle-tilt ion implantation annealing that carries out p type impurity arranges P type columnar semiconductor zone, then imbeds dielectric between P type columnar semiconductor zone, obtains super-junction structure.The semiconductor wafer injection technology control difficulty of this kind super-junction structure is larger, easily forms in vertical direction inhomogeneous p type impurity CONCENTRATION DISTRIBUTION, thereby has influence on the wafer voltage endurance.,

The third carries out the N-type epitaxial loayer and forms, and etching forms groove, then carries out P type epitaxial loayer and forms, and etching forms groove, carries out the N-type epitaxial loayer again and forms, and etching forms groove, fills at last dielectric in groove.The manufacture craft of the semiconductor wafer of this kind super-junction structure needs more repeatedly anisotropic dry etch process to control P type semiconductor and the N type semiconductor area distribution of column, easily affect the columnar semiconductor planform, thereby affect wafer voltage endurance and reliability.

Summary of the invention

The present invention is directed to the problems referred to above and propose, a kind of semiconductor wafer and manufacture method thereof with super-junction structure is provided.

A kind of semiconductor wafer is characterized in that: comprising: substrate layer, a kind of conductive type semiconductor material; A plurality of the first semiconductor layers are separated from each other and are arranged on the substrate layer, are the first conductive type semiconductor material; A plurality of the second semiconductor layers on the sidewall and the substrate layer between the first semiconductor layer of the first semiconductor layer, are the second conductive type semiconductor material; A plurality of the 3rd semiconductor layers are positioned at the groove that the second semiconductor layer forms, and are the first conductive type semiconductor material;

The manufacture method of described semiconductor wafer is characterized in that: comprise the steps:

Form the first conductive type semiconductor material epitaxy layer in a kind of conductive type semiconductor material substrate; In epitaxial loayer, form a plurality of grooves; Form the second conductive type semiconductor material epitaxy layer on the surface; Form the first conductive type semiconductor material epitaxy layer on the surface; Effects on surface carries out grinding and polishing, and the degree of depth of grinding and polishing is for exposing the first conductive type semiconductor material epitaxy layer in wafer surface.

Semiconductor wafer with super-junction structure of the present invention, the P type semiconductor of column and N type semiconductor zone are made of epitaxial loayer, can realize that the P type semiconductor of column and the impurity concentration in N type semiconductor zone evenly distribute in vertical direction, P type semiconductor and N type semiconductor zone form by an anisotropic dry etch process, be easier to control the column structure in P type semiconductor and N type semiconductor zone on the technique, can be perpendicular to semiconductor chip structure in the easy formation of the faying face of PN junction, therefore the evenly super pn junction p n wafer of expansion of a kind of depletion layer can be provided, improve the reverse voltage endurance of wafer and device reliability.

Preparation method with semiconductor wafer of super-junction structure of the present invention, can use less photoetching process and anisotropic dry etch process to realize the manufacturing of device, production technology simpler production more compact structure reduces production cycle of device, has reduced the production cost of device.

Description of drawings

Fig. 1 is a kind of generalized section of semiconductor wafer of the present invention.

Fig. 2 is the generalized section of one embodiment of the present invention technique first step.

Fig. 3 is the generalized section of one embodiment of the present invention technique second step.

Fig. 4 is one embodiment of the present invention technique generalized section in the 3rd step.

Fig. 5 is one embodiment of the present invention technique generalized section in the 4th step.

Fig. 6 is one embodiment of the present invention technique generalized section in the 5th step.

Wherein,

1, substrate layer;

2, the first semiconductor layer;

3, the second semiconductor layer;

4, the 3rd semiconductor layer;

5, oxide layer.

Embodiment

Embodiment

Fig. 1 is a kind of generalized section of a kind of semiconductor wafer of the present invention, describes semiconductor device of the present invention in detail below in conjunction with Fig. 1.

A kind of semiconductor wafer with super-junction structure comprises: substrate layer 1, be N conductive type semiconductor silicon materials, and the doping content of phosphorus atoms is 1E20cm-3; The first semiconductor layer 2 is positioned on the substrate layer 1, is the semiconductor silicon material of N conduction type, and width is 2 μ m, and thickness is 20 μ m, and the doping content of phosphorus atoms is 1E16cm-3; The second semiconductor layer 3 is positioned at the first semiconductor layer 2 sidewalls and substrate layer 1 surface, is the semiconductor silicon material of P conduction type, and width is 2 μ m, and thickness is 20 μ m, and the doping content of boron atom is 1E16cm-3; The 3rd semiconductor layer 4 is positioned at the groove of the second semiconductor layer 3, is the semiconductor silicon material of N conduction type, and width is 2 μ m, and thickness is 18 μ m, and the doping content of phosphorus atoms is 1E16cm-3.

Its manufacture craft comprises the steps:

The first step is 1E20cm-3 semiconductor silicon material substrate layer 1 superficial growth phosphorus atoms doped epitaxial layer in the doping content of phosphorus atoms, forms the first semiconductor layer 2, as shown in Figure 2;

Second step carries out high-temperature oxydation, forms oxide layer 5 in epi-layer surface, then removes surface portion oxide layer 5 by lithography corrosion process, as shown in Figure 3;

The 3rd step by anisotropic dry etch process, formed a plurality of grooves in the first semiconductor layer 2, again carry out high-temperature oxydation, and remove surface oxide layer, as shown in Figure 4;

In the 4th step, the atom doped epitaxial loayer of growth boron forms the second semiconductor layer 3, as shown in Figure 5;

In the 5th step, the epitaxial loayer that the growth phosphorus atoms mixes forms the 3rd semiconductor layer 4, as shown in Figure 6;

In the 6th step, effects on surface carries out grinding and polishing, and the degree of depth of grinding and polishing is that the first semiconductor layer 2 is exposed on the surface, as shown in Figure 1.

As mentioned above, adopt above-described embodiment structure and preparation method, compared with prior art, can use Twi-lithography technique to realize the manufacturing of device, omit the photoetching process of the contact zone of traditional fabrication method, the present invention has reduced the technological requirement that photoetching is produced, production technology simpler production more compact structure, reduce the production cycle of device, reduced the production cost of device.

Groove vertical MOS structure Schottky diode of the present invention, when device connects reverse biased, electric-field intensity distribution by MOS structural change drift region, so that peak value electric field appears near the semi-conducting material of channel bottom, rather than appear near the schottky barrier junction, thereby improved the direction puncture voltage of device, can think that perhaps the doping content of the impurity that improved the drift region reduces the forward conduction resistance of device.

Set forth the present invention by above-mentioned example, also can adopt other example to realize the present invention simultaneously, the present invention is not limited to above-mentioned instantiation, so the present invention is by the claims circumscription.

Claims (6)

1. semiconductor wafer is characterized in that: comprising:
Substrate layer, a kind of conductive type semiconductor material; A plurality of
The first semiconductor layer is separated from each other and is arranged on the substrate layer, is the first conductive type semiconductor material; A plurality of
The second semiconductor layer on the sidewall and the substrate layer between the first semiconductor layer of the first semiconductor layer, is the second conductive type semiconductor material; A plurality of
The 3rd semiconductor layer is positioned at the groove that the second semiconductor layer forms, and is the first conductive type semiconductor material;
Wherein, be provided with a plurality of PN junctions with the semiconductor wafer surface vertical direction.
2. semiconductor wafer as claimed in claim 1, it is characterized in that: described the 3rd semiconductor layer does not contact with substrate layer.
3. semiconductor wafer as claimed in claim 1, it is characterized in that: the length of described the first semiconductor layer vertical wafer is greater than the length of the 3rd semiconductor layer vertical wafer.
4. the manufacture method of semiconductor wafer as claimed in claim 1 is characterized in that: comprise the steps:
1) forms the first conductive type semiconductor material epitaxy layer in a kind of conductive type semiconductor material substrate;
2) in epitaxial loayer, form a plurality of grooves;
3) form the second conductive type semiconductor material epitaxy layer on the surface;
4) form the first conductive type semiconductor material epitaxy layer on the surface;
5) effects on surface carries out grinding and polishing.
5. preparation method as claimed in claim 4, it is characterized in that: described epitaxial loayer in the vertical direction impurities concentration distribution is even.
6. preparation method as claimed in claim 4, it is characterized in that: the degree of depth of described grinding and polishing is for exposing the first conductive type semiconductor material epitaxy layer in wafer surface.
CN2011102873969A 2011-09-26 2011-09-26 Semiconductor chip and production method thereof CN103022087A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2011102873969A CN103022087A (en) 2011-09-26 2011-09-26 Semiconductor chip and production method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2011102873969A CN103022087A (en) 2011-09-26 2011-09-26 Semiconductor chip and production method thereof

Publications (1)

Publication Number Publication Date
CN103022087A true CN103022087A (en) 2013-04-03

Family

ID=47970481

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011102873969A CN103022087A (en) 2011-09-26 2011-09-26 Semiconductor chip and production method thereof

Country Status (1)

Country Link
CN (1) CN103022087A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103730355A (en) * 2013-12-27 2014-04-16 西安龙腾新能源科技发展有限公司 Method for manufacturing super junction structure
CN103762156A (en) * 2013-12-31 2014-04-30 上海新傲科技股份有限公司 Manufacturing method of semiconductor substrate, semiconductor substrate and high-voltage transistor
CN104347351A (en) * 2013-07-31 2015-02-11 英飞凌科技奥地利有限公司 Super junction semiconductor device and manufacturing method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060197152A1 (en) * 2005-03-01 2006-09-07 Kabushiki Kaisha Toshiba Semiconductor device
CN1909245A (en) * 2005-08-01 2007-02-07 半导体元件工业有限责任公司 Semiconductor structure with improved on resistance and breakdown voltage performance
CN101388336A (en) * 2007-09-13 2009-03-18 三洋电机株式会社 Semiconductor crystal manufacture method
JP2009224606A (en) * 2008-03-17 2009-10-01 Shin Etsu Handotai Co Ltd Manufacturing method of semiconductor element having superjunction structure
CN102129997A (en) * 2010-01-18 2011-07-20 上海华虹Nec电子有限公司 Method for forming P-type pole in N-type super junction vertical double diffused metal oxide semiconductor (VDMOS)

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060197152A1 (en) * 2005-03-01 2006-09-07 Kabushiki Kaisha Toshiba Semiconductor device
CN1909245A (en) * 2005-08-01 2007-02-07 半导体元件工业有限责任公司 Semiconductor structure with improved on resistance and breakdown voltage performance
CN101388336A (en) * 2007-09-13 2009-03-18 三洋电机株式会社 Semiconductor crystal manufacture method
JP2009224606A (en) * 2008-03-17 2009-10-01 Shin Etsu Handotai Co Ltd Manufacturing method of semiconductor element having superjunction structure
CN102129997A (en) * 2010-01-18 2011-07-20 上海华虹Nec电子有限公司 Method for forming P-type pole in N-type super junction vertical double diffused metal oxide semiconductor (VDMOS)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104347351A (en) * 2013-07-31 2015-02-11 英飞凌科技奥地利有限公司 Super junction semiconductor device and manufacturing method
CN103730355A (en) * 2013-12-27 2014-04-16 西安龙腾新能源科技发展有限公司 Method for manufacturing super junction structure
CN103730355B (en) * 2013-12-27 2016-05-11 西安龙腾新能源科技发展有限公司 A kind of manufacture method of super-junction structure
CN103762156A (en) * 2013-12-31 2014-04-30 上海新傲科技股份有限公司 Manufacturing method of semiconductor substrate, semiconductor substrate and high-voltage transistor

Similar Documents

Publication Publication Date Title
US20170179225A1 (en) Semiconductor device having a super junction structure and method of manufacturing the same
US8946038B2 (en) Diode structures using fin field effect transistor processing and method of forming the same
TWI422012B (en) Semiconductor power device and method for preparing semiconductor power device
US6710418B1 (en) Schottky rectifier with insulation-filled trenches and method of forming the same
US8421152B2 (en) Semiconductor device and manufacturing method for the same
CN102005452B (en) Integrated schottky diode in high voltage semiconductor device
CN102792448B (en) Semiconductor device
US7052982B2 (en) Method for manufacturing a superjunction device with wide mesas
TWI455310B (en) Nano-Tube MOSFET Technology And Devices
JP4939760B2 (en) Semiconductor device
CN100595920C (en) Semiconductor device and method of fabricating the same
TWI472034B (en) Super junction device with deep trench and implant
CN102403356B (en) Semiconductor device
CN105097894B (en) Semiconductor devices
JP5740108B2 (en) Semiconductor device
JP4417962B2 (en) Planarization method in the manufacture of superjunction devices
US8030705B2 (en) Semiconductor device and method of fabricating the same
US8067800B2 (en) Super-junction trench MOSFET with resurf step oxide and the method to make the same
TWI399815B (en) High voltage structure and methods for vertical power devices with improved manufacturability
DE102008023349B4 (en) Semiconductor device
CN102804386B (en) Semiconductor device
US8513763B2 (en) Silicon carbide semiconductor device
JP5439763B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2006024770A (en) Semiconductor device
CN105453265B (en) Method and semiconductor structure with deep trench isolation structure

Legal Events

Date Code Title Description
PB01 Publication
C06 Publication
SE01 Entry into force of request for substantive examination
C10 Entry into substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20130403

C02 Deemed withdrawal of patent application after publication (patent law 2001)