CN103022087A - Semiconductor chip and production method thereof - Google Patents
Semiconductor chip and production method thereof Download PDFInfo
- Publication number
- CN103022087A CN103022087A CN2011102873969A CN201110287396A CN103022087A CN 103022087 A CN103022087 A CN 103022087A CN 2011102873969 A CN2011102873969 A CN 2011102873969A CN 201110287396 A CN201110287396 A CN 201110287396A CN 103022087 A CN103022087 A CN 103022087A
- Authority
- CN
- China
- Prior art keywords
- semiconductor
- layer
- type semiconductor
- wafer
- conductive type
- Prior art date
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- 239000004065 semiconductors Substances 0.000 title claims abstract description 101
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000009826 distribution Methods 0.000 claims abstract description 5
- 239000010410 layers Substances 0.000 claims description 56
- 239000000463 materials Substances 0.000 claims description 18
- 239000000758 substrates Substances 0.000 claims description 14
- 238000000407 epitaxy Methods 0.000 claims description 8
- 238000000227 grinding Methods 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 6
- 238000002360 preparation methods Methods 0.000 claims description 4
- 230000000694 effects Effects 0.000 claims description 3
- 238000000034 methods Methods 0.000 abstract description 18
- 238000001312 dry etching Methods 0.000 abstract 1
- 125000004437 phosphorous atoms Chemical group 0.000 description 6
- 239000002210 silicon-based materials Substances 0.000 description 5
- AHKZTVQIVOEVFO-UHFFFAOYSA-N oxide(2-) Chemical compound data:image/svg+xml;base64,PD94bWwgdmVyc2lvbj0nMS4wJyBlbmNvZGluZz0naXNvLTg4NTktMSc/Pgo8c3ZnIHZlcnNpb249JzEuMScgYmFzZVByb2ZpbGU9J2Z1bGwnCiAgICAgICAgICAgICAgeG1sbnM9J2h0dHA6Ly93d3cudzMub3JnLzIwMDAvc3ZnJwogICAgICAgICAgICAgICAgICAgICAgeG1sbnM6cmRraXQ9J2h0dHA6Ly93d3cucmRraXQub3JnL3htbCcKICAgICAgICAgICAgICAgICAgICAgIHhtbG5zOnhsaW5rPSdodHRwOi8vd3d3LnczLm9yZy8xOTk5L3hsaW5rJwogICAgICAgICAgICAgICAgICB4bWw6c3BhY2U9J3ByZXNlcnZlJwp3aWR0aD0nMzAwcHgnIGhlaWdodD0nMzAwcHgnIHZpZXdCb3g9JzAgMCAzMDAgMzAwJz4KPCEtLSBFTkQgT0YgSEVBREVSIC0tPgo8cmVjdCBzdHlsZT0nb3BhY2l0eToxLjA7ZmlsbDojRkZGRkZGO3N0cm9rZTpub25lJyB3aWR0aD0nMzAwJyBoZWlnaHQ9JzMwMCcgeD0nMCcgeT0nMCc+IDwvcmVjdD4KPHRleHQgZG9taW5hbnQtYmFzZWxpbmU9ImNlbnRyYWwiIHRleHQtYW5jaG9yPSJlbmQiIHg9JzE3NC45NTInIHk9JzE1Ni42JyBzdHlsZT0nZm9udC1zaXplOjQwcHg7Zm9udC1zdHlsZTpub3JtYWw7Zm9udC13ZWlnaHQ6bm9ybWFsO2ZpbGwtb3BhY2l0eToxO3N0cm9rZTpub25lO2ZvbnQtZmFtaWx5OnNhbnMtc2VyaWY7ZmlsbDojRTg0MjM1JyA+PHRzcGFuPk88L3RzcGFuPjx0c3BhbiBzdHlsZT0nYmFzZWxpbmUtc2hpZnQ6c3VwZXI7Zm9udC1zaXplOjMwcHg7Jz4tMjwvdHNwYW4+PHRzcGFuPjwvdHNwYW4+PC90ZXh0Pgo8L3N2Zz4K data:image/svg+xml;base64,PD94bWwgdmVyc2lvbj0nMS4wJyBlbmNvZGluZz0naXNvLTg4NTktMSc/Pgo8c3ZnIHZlcnNpb249JzEuMScgYmFzZVByb2ZpbGU9J2Z1bGwnCiAgICAgICAgICAgICAgeG1sbnM9J2h0dHA6Ly93d3cudzMub3JnLzIwMDAvc3ZnJwogICAgICAgICAgICAgICAgICAgICAgeG1sbnM6cmRraXQ9J2h0dHA6Ly93d3cucmRraXQub3JnL3htbCcKICAgICAgICAgICAgICAgICAgICAgIHhtbG5zOnhsaW5rPSdodHRwOi8vd3d3LnczLm9yZy8xOTk5L3hsaW5rJwogICAgICAgICAgICAgICAgICB4bWw6c3BhY2U9J3ByZXNlcnZlJwp3aWR0aD0nODVweCcgaGVpZ2h0PSc4NXB4JyB2aWV3Qm94PScwIDAgODUgODUnPgo8IS0tIEVORCBPRiBIRUFERVIgLS0+CjxyZWN0IHN0eWxlPSdvcGFjaXR5OjEuMDtmaWxsOiNGRkZGRkY7c3Ryb2tlOm5vbmUnIHdpZHRoPSc4NScgaGVpZ2h0PSc4NScgeD0nMCcgeT0nMCc+IDwvcmVjdD4KPHRleHQgZG9taW5hbnQtYmFzZWxpbmU9ImNlbnRyYWwiIHRleHQtYW5jaG9yPSJlbmQiIHg9JzY2LjEwMTEnIHk9JzQ4LjM3NScgc3R5bGU9J2ZvbnQtc2l6ZTozOHB4O2ZvbnQtc3R5bGU6bm9ybWFsO2ZvbnQtd2VpZ2h0Om5vcm1hbDtmaWxsLW9wYWNpdHk6MTtzdHJva2U6bm9uZTtmb250LWZhbWlseTpzYW5zLXNlcmlmO2ZpbGw6I0U4NDIzNScgPjx0c3Bhbj5PPC90c3Bhbj48dHNwYW4gc3R5bGU9J2Jhc2VsaW5lLXNoaWZ0OnN1cGVyO2ZvbnQtc2l6ZToyOC41cHg7Jz4tMjwvdHNwYW4+PHRzcGFuPjwvdHNwYW4+PC90ZXh0Pgo8L3N2Zz4K [O-2] AHKZTVQIVOEVFO-UHFFFAOYSA-N 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N boron Chemical group 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[B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 238000005755 formation reactions Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000007254 oxidation reactions Methods 0.000 description 2
- 125000004429 atoms Chemical group 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injections Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
Abstract
Description
Technical field
The present invention relates to a kind of semiconductor wafer and manufacture method thereof, particularly relate to and to realize that height is withstand voltage, semiconductor wafer and the manufacture method thereof of low on-resistance.
Background technology
Energy realization height is withstand voltage and semiconductor chip structure low on-resistance is to present the P type semiconductor of column and the structure that the N type semiconductor zone alternately is arranged side by side, and the P type semiconductor of column and N type semiconductor are perpendicular to wafer surface.Be set as desired value by impurity concentration and width with P type semiconductor and N type semiconductor, when applying reverse pressure drop, can realize high withstand voltage.This kind structure is called super-junction structure.
Known super-junction structure semiconductor chip structure and manufacture method are as follows:
The first, the certain thickness N-type epitaxial loayer of deposit arranges mask and injects p type impurity, and annealing forms the P-type conduction layer.Then repeatedly repeat above-mentioned technological process, form alternate configurations P type semiconductor and N type semiconductor zone.The semiconductor wafer manufacture craft of this kind super-junction structure is loaded down with trivial details, needs about 7 times photoetching implantation annealing technique, and the PN junction face presents waveform, affects the reverse voltage endurance of wafer.
The second, by a plurality of grooves of formation in the N-type epitaxial loayer, thereby the angle-tilt ion implantation annealing that carries out p type impurity arranges P type columnar semiconductor zone, then imbeds dielectric between P type columnar semiconductor zone, obtains super-junction structure.The semiconductor wafer injection technology control difficulty of this kind super-junction structure is larger, easily forms in vertical direction inhomogeneous p type impurity CONCENTRATION DISTRIBUTION, thereby has influence on the wafer voltage endurance.，
The third carries out the N-type epitaxial loayer and forms, and etching forms groove, then carries out P type epitaxial loayer and forms, and etching forms groove, carries out the N-type epitaxial loayer again and forms, and etching forms groove, fills at last dielectric in groove.The manufacture craft of the semiconductor wafer of this kind super-junction structure needs more repeatedly anisotropic dry etch process to control P type semiconductor and the N type semiconductor area distribution of column, easily affect the columnar semiconductor planform, thereby affect wafer voltage endurance and reliability.
Summary of the invention
The present invention is directed to the problems referred to above and propose, a kind of semiconductor wafer and manufacture method thereof with super-junction structure is provided.
A kind of semiconductor wafer is characterized in that: comprising: substrate layer, a kind of conductive type semiconductor material; A plurality of the first semiconductor layers are separated from each other and are arranged on the substrate layer, are the first conductive type semiconductor material; A plurality of the second semiconductor layers on the sidewall and the substrate layer between the first semiconductor layer of the first semiconductor layer, are the second conductive type semiconductor material; A plurality of the 3rd semiconductor layers are positioned at the groove that the second semiconductor layer forms, and are the first conductive type semiconductor material;
The manufacture method of described semiconductor wafer is characterized in that: comprise the steps:
Form the first conductive type semiconductor material epitaxy layer in a kind of conductive type semiconductor material substrate; In epitaxial loayer, form a plurality of grooves; Form the second conductive type semiconductor material epitaxy layer on the surface; Form the first conductive type semiconductor material epitaxy layer on the surface; Effects on surface carries out grinding and polishing, and the degree of depth of grinding and polishing is for exposing the first conductive type semiconductor material epitaxy layer in wafer surface.
Semiconductor wafer with super-junction structure of the present invention, the P type semiconductor of column and N type semiconductor zone are made of epitaxial loayer, can realize that the P type semiconductor of column and the impurity concentration in N type semiconductor zone evenly distribute in vertical direction, P type semiconductor and N type semiconductor zone form by an anisotropic dry etch process, be easier to control the column structure in P type semiconductor and N type semiconductor zone on the technique, can be perpendicular to semiconductor chip structure in the easy formation of the faying face of PN junction, therefore the evenly super pn junction p n wafer of expansion of a kind of depletion layer can be provided, improve the reverse voltage endurance of wafer and device reliability.
Preparation method with semiconductor wafer of super-junction structure of the present invention, can use less photoetching process and anisotropic dry etch process to realize the manufacturing of device, production technology simpler production more compact structure reduces production cycle of device, has reduced the production cost of device.
Description of drawings
Fig. 1 is a kind of generalized section of semiconductor wafer of the present invention.
Fig. 2 is the generalized section of one embodiment of the present invention technique first step.
Fig. 3 is the generalized section of one embodiment of the present invention technique second step.
Fig. 4 is one embodiment of the present invention technique generalized section in the 3rd step.
Fig. 5 is one embodiment of the present invention technique generalized section in the 4th step.
Fig. 6 is one embodiment of the present invention technique generalized section in the 5th step.
Wherein,
1, substrate layer;
2, the first semiconductor layer;
3, the second semiconductor layer;
4, the 3rd semiconductor layer;
5, oxide layer.
Embodiment
Embodiment
Fig. 1 is a kind of generalized section of a kind of semiconductor wafer of the present invention, describes semiconductor device of the present invention in detail below in conjunction with Fig. 1.
A kind of semiconductor wafer with super-junction structure comprises: substrate layer 1, be N conductive type semiconductor silicon materials, and the doping content of phosphorus atoms is 1E20cm-3; The first semiconductor layer 2 is positioned on the substrate layer 1, is the semiconductor silicon material of N conduction type, and width is 2 μ m, and thickness is 20 μ m, and the doping content of phosphorus atoms is 1E16cm-3; The second semiconductor layer 3 is positioned at the first semiconductor layer 2 sidewalls and substrate layer 1 surface, is the semiconductor silicon material of P conduction type, and width is 2 μ m, and thickness is 20 μ m, and the doping content of boron atom is 1E16cm-3; The 3rd semiconductor layer 4 is positioned at the groove of the second semiconductor layer 3, is the semiconductor silicon material of N conduction type, and width is 2 μ m, and thickness is 18 μ m, and the doping content of phosphorus atoms is 1E16cm-3.
Its manufacture craft comprises the steps:
The first step is 1E20cm-3 semiconductor silicon material substrate layer 1 superficial growth phosphorus atoms doped epitaxial layer in the doping content of phosphorus atoms, forms the first semiconductor layer 2, as shown in Figure 2;
Second step carries out high-temperature oxydation, forms oxide layer 5 in epi-layer surface, then removes surface portion oxide layer 5 by lithography corrosion process, as shown in Figure 3;
The 3rd step by anisotropic dry etch process, formed a plurality of grooves in the first semiconductor layer 2, again carry out high-temperature oxydation, and remove surface oxide layer, as shown in Figure 4;
In the 4th step, the atom doped epitaxial loayer of growth boron forms the second semiconductor layer 3, as shown in Figure 5;
In the 5th step, the epitaxial loayer that the growth phosphorus atoms mixes forms the 3rd semiconductor layer 4, as shown in Figure 6;
In the 6th step, effects on surface carries out grinding and polishing, and the degree of depth of grinding and polishing is that the first semiconductor layer 2 is exposed on the surface, as shown in Figure 1.
As mentioned above, adopt above-described embodiment structure and preparation method, compared with prior art, can use Twi-lithography technique to realize the manufacturing of device, omit the photoetching process of the contact zone of traditional fabrication method, the present invention has reduced the technological requirement that photoetching is produced, production technology simpler production more compact structure, reduce the production cycle of device, reduced the production cost of device.
Groove vertical MOS structure Schottky diode of the present invention, when device connects reverse biased, electric-field intensity distribution by MOS structural change drift region, so that peak value electric field appears near the semi-conducting material of channel bottom, rather than appear near the schottky barrier junction, thereby improved the direction puncture voltage of device, can think that perhaps the doping content of the impurity that improved the drift region reduces the forward conduction resistance of device.
Set forth the present invention by above-mentioned example, also can adopt other example to realize the present invention simultaneously, the present invention is not limited to above-mentioned instantiation, so the present invention is by the claims circumscription.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| CN103730355A (en) * | 2013-12-27 | 2014-04-16 | 西安龙腾新能源科技发展有限公司 | Method for manufacturing super junction structure |
| CN103762156A (en) * | 2013-12-31 | 2014-04-30 | 上海新傲科技股份有限公司 | Manufacturing method of semiconductor substrate, semiconductor substrate and high-voltage transistor |
| CN104347351A (en) * | 2013-07-31 | 2015-02-11 | 英飞凌科技奥地利有限公司 | Super junction semiconductor device and manufacturing method |
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