CN115172406A - Vertical Hall device array and preparation method thereof - Google Patents
Vertical Hall device array and preparation method thereof Download PDFInfo
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Abstract
A vertical Hall device array and a preparation method thereof are provided, the vertical Hall device array comprises: a P-type substrate; an N-type well disposed on the P-type substrate; the groove isolation structure is arranged on the surface of the N-type well; a plurality of vertical type Hall devices equally spaced on the N-type well; and the vertical Hall devices are connected by adopting an alternative interconnection method. According to the vertical Hall device array and the preparation method, the magnetic induction measuring precision of the device and the stability of the working state of the vertical Hall device are improved, meanwhile, the area of the vertical Hall array can be effectively reduced, the area of a magnetic induction area is reduced, and the integration level of a Hall chip is improved.
Description
Technical Field
The application relates to the technical field of integrated circuit design, in particular to a vertical Hall device array and a preparation method thereof.
Background
With the development of scientific technology, the hall sensor based on the CMOS process has attracted more and more attention because it is easy to integrate with the CMOS circuit, and can realize the advantages of low cost and high integration level. Integrated hall chips are also increasingly used in the fields of automobile manufacturing, medical electronics, mobile communications, and the like. The Hall sensor is mainly divided into a horizontal Hall device and a vertical Hall device, the horizontal Hall sensor is mainly used for detecting the magnetic field component in the direction vertical to the surface of the chip, the preparation process is simple, and the Hall sensor has excellent performance; the vertical Hall sensor is mainly used for detecting the magnetic field component parallel to the surface direction of a chip, when the vertical Hall device works, bias current needs to flow into the device from a surface input electrode firstly, then flows out from a surface output electrode after passing through a U-shaped path in the device, so that the Hall sensing accuracy of the vertical Hall device is influenced by a complex path, mismatch voltage can occur, and the two Hall electrode ports also have potential difference under the condition of zero magnetic field.
In order to reduce the mismatch voltage of the vertical hall devices, an alternating interconnection method is generally adopted, and each signal flows through the same area of the hall devices through the alternating connection among different electrodes of the vertical hall devices, so that the initial offset disturbance of the devices is effectively reduced. The conventional alternate interconnection method is realized by interconnecting a plurality of separated vertical hall devices, but the conventional alternate interconnection method occupies a large chip area and brings a challenge to high integration of the chip.
Disclosure of Invention
In order to overcome the defects in the prior art, the application aims to provide a vertical Hall device array and a preparation method thereof.
To achieve the above object, the present application provides a vertical hall device array, comprising:
a P-type substrate;
an N-type well disposed on the P-type substrate;
the groove isolation structure is arranged on the surface of the N-type well;
a plurality of vertical type Hall devices distributed on the N-type well at equal intervals;
and the vertical Hall devices are connected by adopting an alternative interconnection method.
Further, the number of the vertical hall devices is 4N, where N is a positive integer greater than or equal to 1.
Further, the depth of the trench isolation structure is greater than 0.5 μm.
Furthermore, the vertical hall device further comprises an N-type buried layer arranged at the bottom of the N-type well, and a port structure located above the N-type buried layer.
Further, the relationship between the distance between the vertical hall devices and the width of the N-type buried layer is as follows:
wherein, L1 is the distance between the vertical Hall devices, and L2 is the width of the N-type buried layer.
Further, the port structure comprises a first ohmic electrode, a second ohmic electrode, a first hall electrode, and a second hall electrode, wherein,
the second Hall electrodes are positioned at two ends of the port structure and are in short circuit through metal leads;
and an N + region is arranged below the first ohmic electrode, the second ohmic electrode, the first Hall electrode and the second Hall electrode, so that the first ohmic electrode, the second ohmic electrode, the first Hall electrode and the second Hall electrode respectively form ohmic contact with the N-type trap.
Further, the trench isolation structures are respectively located between the first ohmic electrode, the second ohmic electrode, the first hall electrode and the second hall electrode, and between the vertical hall devices.
Further, the relationship between the spacing between the first hall electrode and the first ohmic electrode and the spacing between the second ohmic electrode and the first hall electrode is:
wherein L3 is a distance between the first hall electrode and the first ohmic electrode, and L4 is a distance between the second ohmic electrode and the first hall electrode.
Furthermore, the plurality of vertical hall devices are connected by an alternating interconnection method, which includes:
the first ohmic electrode of the 1+ m Hall devices, the first ohmic electrode of the 2+ m Hall devices, the second ohmic electrode of the 3+ m Hall devices and the second Hall electrode of the 4+ m Hall devices are connected with each other to form a current excitation signal input port;
the second ohmic electrode of the 1+ m Hall devices, the second ohmic electrode of the 2+ m Hall devices, the first ohmic electrode of the 3+ m Hall devices and the first Hall electrode of the 4+ m Hall devices are connected with each other to form a current excitation signal output port;
the first Hall electrode of the 1+ m Hall device, the second ohmic electrode of the 2+ m Hall device, the second Hall electrode of the 3+ m Hall device and the first ohmic electrode of the 4+ m Hall device are connected with each other to form a first Hall potential detection port;
the second Hall electrode of the 1+ m Hall device, the first ohmic electrode of the 2+ m Hall device, the first Hall electrode of the 3+ m Hall device and the second ohmic electrode of the 4+ m Hall device are connected with each other to form a second Hall potential detection port;
wherein M =4 (M-1), and M is an integer of 1 or more.
In order to achieve the above objects, the present application also provides a method for manufacturing a vertical hall device array, comprising the steps of,
forming an N-type well on a P-type substrate;
implanting high-energy N-type ions into the N-type well to form an N-type buried layer;
etching a groove structure on the surface of the N-type well by using a dry etching method;
forming an N + region on the surface of the N-type well through high-energy phosphorus ion implantation;
and photoetching a metal electrode lead-out hole on the surface of the N + region, and depositing a metal layer to form metal contact.
Furthermore, the step of etching the trench structure on the surface of the N-type well by using a dry etching method further includes: the trench region is filled with silicon dioxide using a chemical vapor deposition process.
Compared with the prior art, the method has the following advantages:
(1) By adopting the N-type buried layer structure, a low-resistance region can be introduced to the bottom of the N-type trap. After current flows into the device from the input electrode, the current flows downward preferentially due to attraction of the low-resistance buried layer region, and flows out from the surface output electrode after a "U" shaped path is formed inside the device. As shown in fig. 4, after the current flows into the vertical hall device from the first ohmic electrode, the current will preferentially move down to the low resistance region with the buried layer, and then the current will move along the region of the buried layer, and finally flow out of the vertical hall device from the second ohmic electrode, so that the current path is "U" shaped as a whole. The "U" shaped current path can increase the longitudinal current component in the vertical type hall device. According to the left-hand rule, the higher the longitudinal current proportion is, more electrons in motion can be deflected in the motion direction under the action of Lorentz force, so that a larger Hall potential difference is generated on Hall electrodes, and the measurement accuracy of a magnetic field is improved.
(2) The plurality of N-type buried layer structures with a certain interval limit the current flowing area flowing into the vertical hall device array by utilizing the characteristic that current tends to flow through the low resistance area, so that the current flowing path in each vertical hall device is concentrated in the corresponding N-type buried layer area (as shown in fig. 5). By introducing the N-type buried layers, the independent flow of the internal current of each vertical Hall device can be ensured under the condition that the vertical Hall devices share one N-type trap, and the stability of the working state of each vertical Hall device is ensured.
(3) The groove isolation structure between the device electrodes improves the surface equivalent resistance by prolonging the current path between the electrodes, so that the isolation between the devices and the separation of surface current flow can be realized, and the short circuit effect caused by the current flowing along the surface between the electrodes is avoided. The improvement of the surface resistance can further improve the longitudinal current component and improve the measurement precision of the magnetic induction of the device.
(4) The groove isolation structure on the surface of the vertical Hall device array and the internal N-type buried layer structures at intervals realize that a plurality of vertical Hall devices are integrated in one N-type trap, and simultaneously the working states of the vertical Hall devices are not influenced mutually, so that the area of the vertical Hall array can be effectively reduced, the area of a magnetic induction area is reduced, and the integration level of a Hall chip is improved.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, with the embodiments of the application being illustrated and not intended to limit the application:
FIG. 1 is a top view of a vertical Hall device array of the present application;
fig. 2 isbase:Sub>A cross-sectional view of the vertical type hall device arraybase:Sub>A-base:Sub>A' of the present application of fig. 1;
fig. 3 is a cross-sectional view of the vertical type hall device array B-B' of the present application of fig. 1;
FIG. 4 isbase:Sub>A schematic current distribution diagram ofbase:Sub>A cross-section A-A' of the Hall device array of the present application of FIG. 1;
FIG. 5 is a schematic current distribution diagram of a cross-section B-B' of the inventive vertical Hall device array of FIG. 1;
fig. 6 is a schematic view of an alternate connection method adopted by the vertical hall device array of the present application.
Fig. 7 is a flowchart of a method for manufacturing a vertical hall device array according to the present application.
In the figure, a P-type substrate 1, an N-type well 2, an N-type buried layer 3, a trench isolation structure 4, a device port 5, an N + region 6, a first ohmic electrode 51, a second ohmic electrode 52, a first Hall electrode 53 and a second Hall electrode 54.
Detailed Description
Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present application. It should be understood that the drawings and embodiments of the present application are for illustration purposes only and are not intended to limit the scope of the present application.
It should be understood that the various steps recited in the method embodiments of the present application may be performed in a different order and/or in parallel. Moreover, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present application is not limited in this respect.
The term "include" and variations thereof as used herein are open-ended, i.e., "including but not limited to". The term "based on" is "based, at least in part, on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions for other terms will be given in the following description.
It is noted that references to "a", "an", and "the" modifications in this application are intended to be illustrative rather than limiting, and that those skilled in the art will recognize that reference to "one or more" unless the context clearly dictates otherwise. "plurality" is to be understood as two or more.
Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.
Example 1
In the embodiment of the application, the vertical Hall device array takes a P-type material as a substrate, an N-type trap is arranged in the P-type substrate, and an N + region is arranged on the surface of the N-type trap and is used for realizing ohmic contact with a metal electrode; the metal electrodes of the vertical Hall device array are arranged according to a certain transverse interval and a certain longitudinal interval to form a metal electrode array; and the groove isolation structure positioned between the metal electrodes isolates the metal electrode array to form the electrodes of each vertical Hall device. The bottom of the N-type trap is provided with a plurality of mutually independent N-type buried layers, the N-type buried layers are positioned under the vertical Hall devices to form vertical Hall devices with buried layer structures, and the vertical Hall devices form a vertical Hall device array with a segmented buried layer structure.
Fig. 1 isbase:Sub>A top view, fig. 2 isbase:Sub>A cross-sectional view, fig. 1, and fig. 3 isbase:Sub>A cross-sectional view, fig. 1, of the vertical hall device arraybase:Sub>A-base:Sub>A 'of the present application, and fig. 3 isbase:Sub>A cross-sectional view, fig. 1, of the vertical hall device array B-B' of the present application, and as shown in fig. 1-3, the vertical hall device array of the present application, includingbase:Sub>A P-type substrate 1, an N-type well 2,base:Sub>A plurality of N-type buried layers 3,base:Sub>A plurality of vertical hall devices, andbase:Sub>A trench isolation structure 4, wherein,
the N-type well 2 is positioned in the P-type substrate 1;
and a plurality of N-type buried layers 3 disposed at the bottom of the N-type well 2.
A plurality of vertical Hall devices are distributed on the N-type well 2 at equal intervals to form a vertical Hall device array.
The trench isolation structure 4 is a multi-trench structure, is located on the surface of the N-type well 2 (the surface perpendicular to the hall device array), and is filled with silicon dioxide in each trench.
Each vertical type Hall device comprises an N type buried layer 3, a groove isolation structure 4, a device port 5 and an N + region 6.
A plurality of N + regions for forming ohmic contact with metal are arranged on the top of the N-type well 2;
a metal electrode lead-out hole is formed at the upper part of each N + region, and the metal layer forms a metal contact as a device port 5.
In the embodiment of the application, the number of the vertical Hall devices in the N-type well 2 is 4 \65121n, wherein N is a positive integer greater than or equal to 1.
In the embodiment of the application, the number of the N-type buried layers 3 is 4 \65121n, wherein N is a positive integer greater than or equal to 1 and is consistent with the number of 1 vertical Hall devices.
In the embodiment of the present application, each vertical hall device has a five-port structure, and is located directly above the N-type buried layer 3, where two outer ports are short-circuited through a metal wire, so that the five ports form four signal electrodes, which are a first ohmic electrode 51, a second ohmic electrode 52, a first hall electrode 53, and a second hall electrode 54.
N + regions 6 formed by high-concentration N-type doping are respectively disposed below the first ohmic electrode 51, the second ohmic electrode 52, the first hall electrode 53, and the second hall electrode 54, so that the metal electrodes and the N-type well 2 form ohmic contact.
In the embodiment of the present application, the relationship between the distance L1 between the vertical hall devices and the width L2 of the N-type buried layer 3 is:
the relationship between the spacing L3 between the first hall electrode 53 and the first ohmic electrode 51 and the spacing L4 between the second ohmic electrode 52 and the first hall electrode 53 is:
in the embodiment of the present application, the trench depth (H) of the trench isolation structure 4 is greater than 0.5 μm.
Fig. 4 isbase:Sub>A schematic current distribution diagram ofbase:Sub>A cross sectionbase:Sub>A-base:Sub>A' of the vertical hall device array of the present application of fig. 1, where, as shown in fig. 4, after current flows into the vertical hall device from the first ohmic electrode, the current will preferentially move downward to the low resistance region with the buried layer, then the current will move along the region of the buried layer, and finally, the current flows out of the vertical hall device from the second ohmic electrode, so that the current path is "U" shaped asbase:Sub>A whole. The "U" shaped current path can increase the longitudinal current component in the vertical type hall device. According to the left-hand rule, the higher the longitudinal current proportion is, more electrons in motion can be deflected in the motion direction under the action of Lorentz force, so that a larger Hall potential difference is generated on Hall electrodes, and the measurement accuracy of a magnetic field is improved.
Fig. 5 is a schematic current distribution diagram of a cross section B-B' of the vertical hall device array of fig. 1, as shown in fig. 5, the vertical hall device of the present application employs an N-type buried layer structure, and limits a current flowing region in the vertical hall device array by utilizing a characteristic that current tends to flow through a low resistance region, so that a current flowing path in each vertical hall device is concentrated in a corresponding N-type buried layer region (as shown in fig. 5). By introducing the N-type buried layers, the independent flow of the internal current of each vertical Hall device can be ensured under the condition that the vertical Hall devices share one N-type trap, and the stability of the working state of each vertical Hall device is ensured.
Fig. 6 is a schematic diagram of an alternative connection method adopted by the vertical hall device array of the present application, and as shown in fig. 6, an alternative interconnection method is adopted between a plurality of vertical hall device signal electrodes in the vertical hall device array of the present application, and four signals respectively flow through four signal electrodes of the vertical hall device in an alternating manner. The specific connection method is as follows:
(1) The first ohmic electrode 51 of the 1+ m hall device, the first ohmic electrode 53 of the 2+ m hall device, the second ohmic electrode 52 of the 3+ m hall device, and the second hall electrode 54 of the 4+ m hall device are connected to form a current excitation signal input port Iin. Wherein M =4 (M-1), M is 1,2,3 \8230.
(2) The second ohmic electrode 52 of the 1+ m Hall devices, the second Hall electrode 54 of the 2+ m Hall devices, the first ohmic electrode 51 of the 3+ m Hall devices, and the first Hall electrode 53 of the 4+ m Hall devices are connected to form a current excitation signal output port Iout. Wherein M =4 (M-1), M is 1,2,3 \8230.
(3) The first Hall electrode 53 of the 1+ m Hall device, the second ohmic electrode 52 of the 2+ m Hall device, the second Hall electrode 54 of the 3+ m Hall device, and the first ohmic electrode 51 of the 4+ m Hall device are connected to form a first Hall potential detection port Vhall1. Wherein M =4 (M-1), M is 1,2,3 \8230.
(4) The second Hall electrode 54 of the 1+ m Hall device, the first ohmic electrode 51 of the 2+ m Hall device, the first Hall electrode 53 of the 3+ m Hall device, and the second ohmic electrode 52 of the 4+ m Hall device are connected to form a second Hall potential detection port Vhall2; wherein M =4 (M-1), M is 1,2,3 \8230.
Example 2
Fig. 7 is a flowchart of a method for manufacturing a vertical hall device array according to the present application, and the method for manufacturing a vertical hall device array according to the present application will be described in detail with reference to fig. 7.
First, in a first step, a P-type substrate 1 is pre-cleaned, and then an N-type well 2 is formed by N-type ion implantation and then high-temperature annealing, as shown in (a) of fig. 7.
In the second step, high-energy N-type ions are implanted to form the N-type buried layer 3. As shown in fig. 7 (b).
In the third step, a trench structure 4 is etched on the surface of the N-type well 2 by using dry etching, as shown in (c) of fig. 7; the trench region is then filled with silicon dioxide using chemical vapor deposition, as shown in fig. 7 (d).
In the fourth step, an N + region 6 is formed in the N-type well 2 by high-energy phosphorus ion implantation for ohmic contact with the metal, as shown in (e) of fig. 7.
In the fifth step, a metal electrode lead-out hole is photo-etched on the N + region 6, a metal layer is deposited, and an excess metal is etched to form a metal contact, as shown in (f) of fig. 7.
Finally, it is to be noted that: although the present application has been described in detail with reference to the embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described in the foregoing embodiments, or some features may be substituted by equivalent features, and any modifications, equivalents, improvements and the like, which are within the spirit and principle of the present application, are intended to be included within the scope of the present application.
Claims (11)
1. A vertical Hall device array is characterized by comprising,
a P-type substrate;
an N-type well disposed on the P-type substrate;
the groove isolation structure is arranged on the surface of the N-type well;
a plurality of vertical type Hall devices equally spaced on the N-type well;
and the vertical Hall devices are connected by adopting an alternative interconnection method.
2. The array of vertical hall devices of claim 1 wherein the number of vertical hall devices is 4N, wherein N is a positive integer greater than or equal to 1.
3. The array of vertical hall devices of claim 1 wherein the trench isolation structures have a depth greater than 0.5 μm.
4. The array of vertical hall devices of claim 1 further comprising an N-type buried layer disposed at a bottom of the N-type well and a port structure located above the N-type buried layer.
5. The array of vertical hall devices of claim 4 wherein the distance between the vertical hall devices and the width of the buried N-type layer are in relation to:
，
wherein, L1 is the distance between the vertical Hall devices, and L2 is the width of the N-type buried layer.
6. The array of vertical hall devices of claim 4 wherein the port structure comprises a first ohmic electrode, a second ohmic electrode, a first hall electrode, and a second hall electrode, wherein,
the second Hall electrodes are positioned at two ends of the port structure and are in short circuit through metal leads;
and an N + region is arranged below the first ohmic electrode, the second ohmic electrode, the first Hall electrode and the second Hall electrode, so that the first ohmic electrode, the second ohmic electrode, the first Hall electrode and the second Hall electrode respectively form ohmic contact with the N-type trap.
7. The array of vertical hall devices of claim 6 wherein the trench isolation structures are located between the first ohmic electrode, the second ohmic electrode, the first hall electrode and the second hall electrode, and the vertical hall devices, respectively.
8. The array of vertical hall devices of claim 7 wherein the spacing between the first hall electrode and the first ohmic electrode is in relation to the spacing between the second ohmic electrode and the first hall electrode:
，
wherein L3 is a distance between the first hall electrode and the first ohmic electrode, and L4 is a distance between the second ohmic electrode and the first hall electrode.
9. The vertical hall device array of claim 1 wherein the plurality of vertical hall devices are interconnected by an alternating interconnection method comprising:
the first ohmic electrode of the 1+ m Hall devices, the first ohmic electrode of the 2+ m Hall devices, the second ohmic electrode of the 3+ m Hall devices and the second Hall electrode of the 4+ m Hall devices are connected with each other to form a current excitation signal input port;
the second ohmic electrode of the 1+ m Hall devices, the second Hall electrode of the 2+ m Hall devices, the first ohmic electrode of the 3+ m Hall devices and the first Hall electrode of the 4+ m Hall devices are connected with each other to form a current excitation signal output port;
the first Hall electrode of the 1+ m Hall device, the second ohmic electrode of the 2+ m Hall device, the second Hall electrode of the 3+ m Hall device and the first ohmic electrode of the 4+ m Hall device are connected with each other to form a first Hall potential detection port;
the second Hall electrode of the 1+ m Hall device, the first ohmic electrode of the 2+ m Hall device, the first Hall electrode of the 3+ m Hall device and the second ohmic electrode of the 4+ m Hall device are connected with each other to form a second Hall potential detection port;
wherein M =4 (M-1), and M is an integer of 1 or more.
10. A preparation method of a vertical Hall device array comprises the following steps:
forming an N-type well on a P-type substrate;
injecting high-energy N-type ions into the N-type trap to form an N-type buried layer;
etching a groove structure on the surface of the N-type trap by using a dry etching method;
forming an N + region on the surface of the N-type well through high-energy phosphorus ion implantation;
and photoetching a metal electrode leading-out hole on the surface of the N + region, and depositing a metal layer to form metal contact.
11. The method of claim 10, wherein the step of etching the trench structure in the surface of the N-type well by dry etching further comprises: and filling silicon dioxide in the groove area by using a chemical vapor deposition method.
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| CN117279481A (en) * | 2023-11-23 | 2023-12-22 | 深圳市晶扬电子有限公司 | High-performance vertical Hall device |
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| CN117279481A (en) * | 2023-11-23 | 2023-12-22 | 深圳市晶扬电子有限公司 | High-performance vertical Hall device |
| CN117279481B (en) * | 2023-11-23 | 2024-02-09 | 深圳市晶扬电子有限公司 | High-performance vertical Hall device |
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