JPH0311679A - Hall device - Google Patents

Abstract

PURPOSE:To enhance a sensitivity and to reduce an offset by a method wherein a Hall device is formed of a Hall element where an insulating layer has been formed on an n-epitaxial layer by filling a groove and by a separation. CONSTITUTION:Hall elements 10, 10a which have been formed by growing an n-epitaxial layer 37 on a p-type substrate 38 are arranged. These Hall elements 10, 10a respectively form the following: one pair of input electrodes 11, 12 formed on the n-epitaxial layer 37; one pair of output terminals 13, 14 used to output a Hall voltage; and an insulating layer by isolating filled grooves 22 to 24 in the n-epitaxial layer 37. Thereby, a width through which carriers moving in the individual Hall elements 10, 10a are passed is narrowed. In addition, a direction of the carriers becomes a horizontal direction; a sensitivity is enhanced; it is possible to suppress an offset to be low by connecting a plurality of these Hall elements 10, 10a.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a Hall device formed by forming a plurality of Hall elements on the same chip by forming an n epitaxial layer on a p-type silicon substrate. It is something.

[Prior Art] A Hall element is constructed by growing an n epitaxial layer on a p-type substrate and forming four n+ terminals thereon. Among these four terminals, two terminals are input terminals for supplying current to the Hall element, and the other two terminals are terminals for outputting the generated Hall voltage. Some of these Hall devices include a cross-coupled quad 5tr structure in which four Hall elements are electrically connected in parallel.
There is also a pole effect device. Two of these Hall elements are arranged perpendicularly to each other, and one set of them is a chip (Hall device).
The other set is used to reduce mechanical offsets due to stress when bonded to the metal header part, and the other set is provided to reduce offsets due to manufacturing errors in photomasks and other Hall elements. ing.

As mentioned above, these four Hall elements are electrically connected in parallel, and the directions of the currents flowing through the Hall elements are orthogonal to each other at 90 degrees, so the error voltage is generated between the four elements. It is averaged and minimized, and the offset of the Hall element as a whole due to structural stress is also reduced.

[Problems to be Solved by the Invention] However, in the conventional Hall effect device having such a configuration, only the reduction of the offset of the Hall elements on the chip as a whole is considered, and the reduction of the offset of the individual Hall elements is considered. No consideration is given to reducing offset or improving sensitivity of the entire chip based on the shape of the chip. For this reason,
The offset is not completely canceled out (e.g. less than 2mV),
The sensitivity error has only decreased to about 160 G, and the emergence of a Hall effect device with higher accuracy and less offset is eagerly awaited.

The present invention has been made in view of the above-mentioned conventional example, and is a Hall device in which the sensitivity of the entire Hall device is improved and the offset voltage is reduced by making each Hall element on the Hall device have a groove filling structure. The purpose is to provide

[Means for Solving the Problems] In order to achieve the above object, the Hall device of the present invention has the following configuration. That is, it is a Hall device including a plurality of Hall elements formed by growing an n-epitaxial layer on a p-type substrate, each of the hall elements having at least one pair of hall elements formed on the n-epitaxial layer. an input electrode, at least one pair of output terminals formed on the n-epitaxial layer for outputting a Hall voltage, and an insulating layer formed on the n-epitaxial layer by trench filling separation, and the plurality of Hall elements. A current supply line connects the input electrodes of the plurality of Hall elements in parallel, and a Hall voltage output line connects the output terminals of the plurality of Hall elements in parallel.

[Function] In the above structure, a plurality of Hall elements formed by growing an n-epitaxial layer on a p-type substrate are arranged, and each of these hall elements is formed by at least one pair of hall elements formed on an n-epitaxial layer. an input electrode, at least one pair of output terminals formed on the n-epitaxial layer for outputting a Hall voltage, and an insulating layer formed on the n-epitaxial layer by trench filling separation. As a result, the width of the passage of the carrier moving through each ball element is narrowed, and the direction of the carrier is horizontal, so sensitivity can be improved and offset can be kept low by connecting a plurality of these elements.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Before explaining the Hall device of this embodiment, one Hall element 30 on a conventional ball device will be explained with reference to FIG.
We will explain the structure of In FIG. 3, reference numerals 31 and 32 indicate input electrodes for passing current ■ through the Hall element 30; 33.
34 is the Hall voltage V H generated in this Hall element 30
It is a Hall electrode for extracting. 39 is Hall element 3
FIG.

37 is an n-epitaxial (n-epi) layer, 38 is a p-substrate (p-type substrate), and 32.34 is an n+ part constituting an electrode. 35 and 36 are p portions forming an insulating separation wall for electrons by a p-n junction.

Here, when a magnetic field B is applied in the vertical direction of the Hall element 30 in FIG. 3 (direction perpendicular to the drawing), the electrodes 31.3
The current flowing between the two is bent by the magnetic field B, and the Hall voltage vH is obtained from VH=R11.I.B/a-(1). Here, R□ is the Hall coefficient, ■ is the applied current, B is the magnetic flux density, and d is the thickness of the element. Furthermore, when the width of the Hall element is W and the length of the Hall element is L, the input resistance R of the Hall element is R-ρ・L/dW (ρ
is the specific resistance). From this, 1/d(・R−W/(L・ρ)
) into equation (1), we get V,=RHI ・BR−
W/(ρ・L). R・■ is the input voltage■, RH/p
is the electron mobility μ, so the ball voltage Vl+ is VH=
It can also be expressed as u·W-V-B/L-(2).

In order to control this thickness in the manufacturing process of the Hall element 30, when forming an n epitaxial layer on a p-type 81 substrate, the growth rate of this layer must be controlled extremely accurately by controlling the amount of raw materials supplied, temperature, time, etc. need to be controlled. The present invention forms an insulating layer in the n-epitaxial layer of each Hall element by trench-filling isolation to narrow the range (width) through which carriers pass, substantially reducing the thickness d of each element, and By specifying the moving direction of carriers in the horizontal direction, the Hall voltage (Vo) with respect to the magnetic field (B) is increased to increase sensitivity.

Before explaining the Hall device of the embodiment, the configuration of one Hall element constituting the device will be explained.

[Description of Hall Element (Fig. 4)] Fig. 4 is a diagram showing the shape and cross section of one Hall element 1o constituting the Hall device of the embodiment, and is different from the conventional Hall element 30 in Fig. 3. Common parts are indicated by the same numbers.

In FIG. 4, reference numerals 11 and 12 are input electrodes through which current flows, and 3rd and 14th are Hall electrodes that output a Hall voltage V□. Reference numeral 18 indicates a cross-sectional shape of the Hall element 10 taken along line BB'. Here, as in the conventional bipolar process, an n epitaxial layer 37 is grown on a p-type silicon substrate 38 by thermal diffusion, etc., and a p layer 35, 36, which is an insulating separation wall, is formed by thermal diffusion or ion implantation. There is.

The parts indicated by 15 to 17 are RIE (React
This is a part in which a narrow groove (trench) is formed using a processing technique using -ive ion etching), and nine layers are formed in the groove by base boron diffusion or the like.

Furthermore, the inner parts 22 to 2 of these nine layers 15 to 17
4 is filled with polyimide or the like to form an insulating layer (trench isolation).

By using such a trench structure, insulation 1'i
Since the cross-sectional shape of 23 can be made rectangular, the diagonal component of the direction of the current (movement of majority carriers) flowing between the electrodes 11 and 12 can be eliminated, so the direction of current flow in the n epitaxial layer 37 is Becomes horizontal.

In this way, by lengthening the path along which the majority carriers move in the horizontal direction within the n epitaxial layer 37, the distance the carriers move to be affected by the magnetic field can be increased, which improves the sensitivity of the Hall element. . Furthermore, according to the first equation described above, the width of movement of majority carriers in the n epitaxial layer 37 (thickness of the Hall element) is narrowed, so the Hall voltage vH for a predetermined magnetic field B increases, and the sensitivity improves. Recognize. In this embodiment, the depth of the trench portion 23 is approximately 10 to 90% 1 2 of the n epitaxial layer 37, and the depth of the n epitaxial layer 37 is approximately 17 μm.

[Description of the Hall device (FIGS. 1 and 2)] FIG. 1 shows the configuration of the Hall device 100 formed by connecting two Hall elements 10 and 10a shown in FIG. 4, and its A-A'
This is a diagram showing a cross-sectional shape 110 of FIG. 4, and the same parts as in FIG. Note that the Hall element 10a has exactly the same configuration as the Hall element 10, and in order to simplify the drawing, numbering in the cross-sectional shape of one Hall element 10a is omitted.

In the figure, 101 is an input terminal for applying a voltage and passing current, and 102 is a Hall electrode for outputting a Hall voltage. As is clear from the figure, the directions of the two currents flowing through the Hall elements 10 and 10a are orthogonal to each other. Since the output Hall voltages are connected in parallel, the output value is the same as that of the two Hall elements 10.10a.
is the average value. In addition, two Hall elements 10.10a
By connecting as shown in the figure, the offset outputs of the two elements cancel each other out, making it possible to create a Hall device with less offset.

FIG. 2 is a diagram showing the configuration of a Hall device 200 according to another embodiment, which includes four Hall elements 10. ．． 10a-10c is 1
It is formed on two Hall devices. Each of these Hall elements is made with the same configuration as the Hall element shown in FIG. Note that 201 is an input electrode for applying a current to each Hall element, and 202 is a Hall output terminal to which the Hall voltages of each Hall element are connected in parallel.

In this case as well, the current directions in each Hall element are orthogonal to each other and their Hall voltages are also connected in parallel, so the output Hall voltage of the entire ball device is averaged, and the offset of each Hall element is cancel each other out.

[Other Examples] ■In Fig. 1, supply electrode 11.12 and hole electrode 1
3. The distance between each terminal in 14 and the insulating separation wall 35.36 (L
+, L2) is maximized within the range of device mounting (
Here, the value is 5 oILm or more, preferably 80 to 110
00JL), it is possible to reduce offset voltage caused by misalignment such as mask alignment.

■Relational equation of Hall voltage in Equation (2) mentioned above V IIμ
From W −V −B/L, by shortening the length of the Hall element and widening the width W of the Hall element, the Hall voltage v
It can be seen that sensitivity can be improved by increasing H. Therefore, by changing the distance between the current supply electrode 11 and the electrode 12 (the length L of the Hall element) and the distance between the ball electrodes 13 and 14 (the width W of the Hall element), the sensitivity of the Hall element can be further increased. be able to.

■Furthermore, according to this embodiment, the insulating separation wall of the Hall element is formed by the nine-layer portion 35, 36, but by insulating this portion with a trench structure, it is possible to further increase the degree of integration. can.

As explained above, the Hall device of this embodiment has the effect of further improving sensitivity, lowering power consumption, and reducing aging.

Furthermore, according to the Hall device of this example, a minute magnetic field can be detected, and the output Hall voltage is also proportional to the strength of the magnetic field. There is a possibility that an acceleration sensor of 5 6 can be developed.

Furthermore, this Hall device can be applied to a wide variety of sensors that detect geomagnetism, flow rate, membrane pressure, direction, and the like.

Furthermore, since the Hall device of this embodiment is composed of a Hall element formed in silicon using a bipolar process, the Hall device including its signal processing circuit, etc.
This makes it possible to make chips into chips, making it possible to develop intelligent sensors.

[Effects of the Invention] As explained above, according to the present invention, a Hall device can be formed using a Hall element in which an insulating layer is formed in an n-epitaxial layer by trench-filling isolation, making use of the manufacturing process of a Hall element using a bipolar process. This has the effect of improving sensitivity, reducing offset, and further reducing power consumption and aging.

In this example, the directions of current flow in each Hall element are orthogonal to each other, and the Hall elements are connected so that the average value of the output Hall voltage of each Hall element is output, but the present invention is not limited to this. Each Hall element may be connected so that the current directions are orthogonal to each other so that the difference in the output Hall voltage of each Hall element is output, or the current direction of each ball element is made the same and the difference in the output Hall voltage is output. Alternatively, they may be connected so that the average value is output.

Further, in this embodiment, the case where the number of Hall elements is two or four has been described, but it is needless to say that the number is not limited to this.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the shape of a Hall device of an embodiment and its cross-sectional shape, Fig. 2 is a diagram showing the structure of a Hall device of another embodiment, and Fig. 3 is a diagram showing the shape of a conventional Hall element and its cross-sectional shape. and FIG. 4 are diagrams showing the shape and cross-sectional shape of the Hall element in the Hall device of the example. In the figure, 10. 10a-10c-Hall element, 11
．． 12...Manual electrode, 13.14...Hall voltage output terminal, 15-17...p layer portion of trench, 22
~24...Trench (groove filling part), 35.36...
Insulating separation wall, 37...n epitaxial layer, 38...
・P-type substrate (substrate), 100, 200...
Hall device, 101, 201... input electrode, 10
2.202...Hall output terminal.

Claims (1)

[Claims] A Hall device comprising a plurality of Hall elements formed by growing an n-epitaxial layer on a p-type substrate, wherein each of the hall elements is formed on an n-epitaxial layer. at least one pair of input electrodes, at least one pair of output terminals formed on the n-epitaxial layer for outputting a Hall voltage, and an insulating layer formed on the n-epitaxial layer by groove filling separation, A Hall characterized by having: a current supply line connecting input electrodes of a plurality of Hall elements in parallel; and a Hall voltage output line connecting output terminals of the plurality of Hall elements in parallel. device.