JP2002343967A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a withstand voltage in a peripheral region without enlarging the area of the peripheral region and also without thickening a drift layer. SOLUTION: A layer 8 of an opposite conductivity type is added to the drift layer 10. Consequently, a structure is obtained wherein a depletion layer stretches from at least two junction surfaces, and distribution of electric field intensity is made uniform in the depthwise direction of the semiconductor device. As a result, a large peak of electric field intensity is not generated in a specified depth, and the withstand voltage in the peripheral region can be improved without increasing an ON voltage in a central region and enlarging the area of the peripheral region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technique for increasing the breakdown voltage of a semiconductor device. In particular, the present invention relates to a semiconductor device having an increased withstand voltage in a peripheral region (usually, a region where a guard ring is formed) of the semiconductor device.

[0002]

2. Description of the Related Art As a power control semiconductor device,
Semiconductor devices incorporating MOS or IGBT structures are known. In this type of semiconductor device, a power MOS or IGBT structure is formed in a central region of a semiconductor substrate, and the periphery is a peripheral region. Usually, a guard ring is formed in this peripheral region to increase the breakdown voltage of the peripheral region.

FIG. 5 is a sectional structure of a peripheral region of a semiconductor device.
And, in this case, p⁺On the back surface of the mold semiconductor substrate 44
A drain electrode 42 is formed, and p⁺Type semiconductor substrate 44
To n ⁺The pattern buffer layer 46 is laminated, and n⁺Type buffer layer
N on 46⁻The mold drift layer 50 is stacked. region
A indicates a central region or an element formation region, and in this case, n
⁻P on the drift layer 50⁻The mold body layer 36 is laminated
ing. p⁻N in the mold body layer 36⁺Type emitter region 3
0 and p⁺The body contact region 28 is formed,
, An emitter electrode 26 is formed. Figure 5 is a trench
Illustrates a type of switching with a gate, where n⁻
Type drift layer 50 and n⁺Between the emitter regions 30⁻
Facing the mold body layer 36 with the insulating layer 32 interposed therebetween
A gate electrode 34 is formed at the position. Due to this structure
Thus, the IGBT structure is built in the central region A. Week
The side region B includes a peripheral region when the semiconductor device is viewed in plan.
A plurality of guard rings 60, 56a, 56
b, 56c are formed. Each guard ring 60, 5
6a, 56b and 56c are p⁺Formed with mold diffusion layer
I have. The innermost guard ring 60 is p⁻Mold body layer 3
6 and p⁻Type body layer 36 is an emitter electrode
26, and the emitter electrode 26 is grounded and used.
Therefore, the innermost guard ring 60 is grounded.
You. Other guard rings 56a, 56b, 56c
Is floating. Each guard ring 5
6a, 56b, 56c have electrodes 58a, 58b, 58c
Are connected, the electrodes 58a, 58b, 58
c is not connected anywhere. Electrodes 58a, 58b, 58
c increases the width of the depletion layer described later. Widening the depletion layer
When the guard rings 56a, 56b, 56c
The depletion layers extending from the respective layers are continuous, and the breakdown voltage is improved.

[0004]

In the conventional peripheral structure for increasing the breakdown voltage of the peripheral region B, the effect of increasing the breakdown voltage is not remarkable. To ensure the necessary breakdown voltage, the n ⁻ type drift layer 50 is required.
It is necessary to increase the thickness or to lower the impurity concentration. However, in any case, if the required withstand voltage is secured by adopting the above method, the central region A
Up to the on-state voltage. In addition, there is a problem that a large number of guard rings are required and the area of the peripheral region B is increased. The present invention realizes a semiconductor structure that does not increase the on-voltage in the central region A, does not increase the area of the peripheral region B, and can ensure the withstand voltage required for the peripheral region B.

[0005]

Means and Action for Solving the Problems According to the present invention,
The above problem is solved by adding a layer of the opposite conductivity type to the drift layer. According to this structure, a structure in which a depletion layer extends from at least two bonding surfaces is obtained, and the electric field intensity distribution is uniformed in the depth direction of the semiconductor device, and a large electric field intensity peak does not occur at a specific depth. The withstand voltage of the peripheral region can be improved. It is not necessary to increase the on-voltage in the central region and to increase the area of the peripheral region.

One semiconductor device realized by the present invention is:
The semiconductor device is characterized in that a layer of a conductivity type opposite to that of the drift layer is laminated in the peripheral drift layer of the semiconductor device over the entire peripheral region. When the layer of the opposite conductivity type is spread over the entire peripheral region when viewed in a plan view, the electric field intensity distribution in the peripheral region is more homogenized, and the electric field intensity peak value decreases,
The withstand voltage of the peripheral region is effectively improved.

It is preferable that a plurality of layers of the opposite conductivity type to the drift layer are stacked in the peripheral drift layer in the depth direction of the semiconductor device. In this case, it is preferable that each layer of the opposite conductivity type extends over the entire peripheral region when viewed in plan. In this case, the electric field intensity distribution in the peripheral region is further homogenized, the electric field intensity peak value is further reduced, and the breakdown voltage in the peripheral region is effectively improved.

In another semiconductor device realized by the present invention, a layer having a conductivity type opposite to that of the drift layer is stacked in a peripheral drift layer of the semiconductor device, and the layer having the opposite conductivity type has the same conductivity as the drift layer. It is formed in contact with the semiconductor substrate of the mold. In this case, each layer of the opposite conductivity type may be locally spread when viewed in plan and may be separated from each other. That is, layers of the opposite conductivity type, each of which locally spreads when viewed in a plan view, may be separated from each other. In this case, even if the layers of the opposite conductivity type are separated from each other, the withstand voltage in the peripheral region is effectively improved because they are formed in contact with the semiconductor substrate of the same conductivity type as the drift layer.

In still another semiconductor device realized by the present invention, a layer group of a conductivity type opposite to that of the drift layer is stacked in a peripheral drift layer so as to be spaced apart from each other in plan view, and is formed below the drift layer. The buffer layer and the semiconductor substrate are stacked. In this case, the layer of the opposite conductivity type may or may not be connected to the buffer layer.
Also in this case, the withstand voltage in the peripheral region is effectively improved.

When a guard ring is formed in a peripheral region on the surface of the semiconductor device and a depletion layer extending from the guard ring to the drift layer is formed, a layer of the opposite conductivity type is formed within a depth reached by the depletion layer. Is preferred. In this case, the depletion layer spreads over a wide range, the electric field intensity distribution in the peripheral region is further homogenized, the electric field intensity peak value is further reduced, and the withstand voltage in the peripheral region is effectively improved.

[0011]

FIG. 1 shows the present invention having a trench gate.
1 shows an embodiment embodied in a peripheral region of an IGBT.
In the case of the semiconductor device of this embodiment, p⁺Type semiconductor substrate 4
A drain electrode 2 is formed on the back surface, and p⁺Type semiconductor substrate 4
N on⁺Type buffer layer 6 is laminated, and n⁺Type buffer layer
P on 6⁻Type drift layer 8 is laminated, ⁻Mold drift
N on layer 8⁻The mold drift layer 10 is stacked. FIG.
In comparison with the prior art shown in FIG.⁻Type drift layer 8
You can see that it has been added. In the central area, n⁻Type
P on the lift layer 10⁻Mold body layer 36 is laminated
You. p⁻N in the mold body layer 36⁺Type emitter region 30
p⁺A mold body contact region 28 is formed, and
Mitter electrodes 26 are formed. n⁺Type emitter region
30 and p⁻Through the mold body layer 36⁻Type drift layer 1
0 is formed, in which a trench is formed.
The gate electrode 34 covered with the insulating layer 32 is buried.
You. The gate electrode 34 has n⁻Type drift layer 10 and n⁺Type
P between the emitter regions 30⁻Perfect for mold body layer 36
They face each other via the edge layer 32. The sectional structure of FIG.
The gate electrode 3 is continuous in a direction perpendicular to the paper surface and has a cross section (not shown).
4 is connected to external wiring. The cross-sectional structure shown in FIG.
It is repeated to the left of the paper.

In the peripheral region, two guard rings 20 and 16 are formed extending in the peripheral region when the semiconductor device is viewed in a plan view and surrounding the semiconductor device. Each of the guard rings 20, 16 is formed of ap ⁺ -type diffusion layer. The inner guard ring 20 p ^- connects to the mold body layer 36, p ^- type body layer 36 is connected to the emitter electrode 26, since the emitter electrode 26 is used while being grounded, the inner guard ring 20 Grounded. The outer guard ring 16a is floated. Although the electrodes 22, 18 are connected to the guard rings 20, 16, the electrodes 22, 18 are not connected anywhere. Electrode 2
2, 18 increase the width of the depletion layer described later. When the width of the depletion layer is increased, the depletion layers extending from each of the guard rings 20 and 16 are continuous, and the breakdown voltage is improved. An n ⁺ type region 12 is formed on the outermost peripheral surface of the semiconductor device. n
^{The +} type region 12 inhibits a current from flowing up and down along the side surface of the semiconductor device. The electrode 14 connected to the n ⁺ type region 12 is also floating.

1 and FIG. 5, it is apparent that, in the present embodiment, the n ⁻ type drift layer 50 is provided with a layer (p ⁻
Mold drift layer) 8 is added. The total thickness of the drift layers 10 and 8 is smaller than the thickness of the drift layer 50. Further, the impurity concentration of the drift layers 10 and 8 is higher than the impurity concentration of the conventional drift layer 50, and the resistance is reduced. Further, the number of guard rings is different, and the area of the peripheral region of the semiconductor device of FIG.
Smaller than the area of the peripheral region of the semiconductor device.

When a reverse bias is applied to the semiconductor device,
A pn junction between the n ⁺ -type buffer layer 6 and the p ⁻ -type drift layer 8 and a p ^- type junction between the n ⁻ -type drift layer 10 and the p ⁻ -type body layer 36.
A depletion layer extends from the n junction and the pn junction between the n ⁻ type drift layer 10 and the p ⁺ type guard rings 20 and 16.

[0015] ^{n +} type buffer layer 6 and the p ^- type drift layer 8
The depletion layer extending from the pn junction therebetween extends mainly toward the p ⁻ type drift layer 8 and punches through the n ⁻ type drift layer 10. The depletion layer extending from the pn junction between the n ⁻ -type drift layer 10 and the p ⁻ -type body layer 36 extends toward the p ⁻ -type body layer 36 and extends over the entire area of the p ⁻ -type body layer 36. When a reverse bias is applied, the depletion layers become the drift layers 8 and 10 and the body layer 12.
Therefore, the breakdown voltage of the central region of the semiconductor device is higher than that of the conventional semiconductor device.

In the peripheral region, n ⁺ type buffer layer 6 and p ⁻
The depletion layer extending from the pn junction between the drift layers 8 mainly extends to the p ⁻ drift layer 8 side, and the n ⁻ drift layer 10
Punch through. The depletion layer extending from the pn junction between the n ⁻ -type drift layer 10 and the p ⁺ -type guard rings 20 and 16 mainly extends to the n ⁻ -type drift layer 10 and punches through the p ⁻ -type drift layer 8. The p ⁻ type drift layer 8 is provided at a depth at which a depletion layer extending from the guard rings 20 and 16 extends. When a reverse bias is applied, the depletion layer spreads widely throughout the drift layers 8 and 10, so that the breakdown voltage in the peripheral region of the semiconductor device is higher than in the past. Since the p ⁻ type drift layer 8 is continuously spread over the entire peripheral region, the electric field intensity distribution in the semiconductor device is homogenized, the peak value of the electric field intensity is reduced, and the withstand voltage is effectively improved. .

In the above semiconductor structure, the drift layers 8 and 1
Since a high breakdown voltage can be obtained without increasing the resistance of 0, the resistance can be reduced by increasing the impurity concentration of the drift layers 8 and 10, and the layer thickness can be reduced. For this reason, it is possible to keep the on-voltage low while securing the withstand voltage.

FIG. 2 shows a second embodiment, in which n⁺Type buffer
On layer 6, p⁻Drift layer 8 and n ⁻Type drift layer 10
IGBT obtained by repeating the alternate layer twice twice. In FIG.
Indicates the lower alternate layer with a suffix a, and the upper alternate layer with a suffix b.
Is shown. The number of alternating layers is not limited to two, but three
It may be above. Multiple drift layers of opposite conductivity type
When used, a uniform depletion layer is formed over a wide area
And the withstand voltage can be more effectively increased. Opposite conductivity
The plurality of drift layers 8a, 8b of the
4 is formed in a region deeper than the deepest portion of the IGBT.
The basic configuration is maintained.

FIG. 3 shows a third embodiment. The drift layer 8d of the opposite conductivity type added to the drift layer 10 in the peripheral region does not necessarily have to spread over the entire area, and may be present locally at a necessary portion. In this case,
The drift layer 8d of the opposite conductivity type includes the guard rings 16, 2
It is formed only in the region between 0. Even in this case, the depletion layer spreading from the guard rings 16 and 20 punches through the drift layer 8d of the opposite conductivity type, thereby increasing the breakdown voltage of the peripheral region. In the case of FIG. 3, the drift layer 8 d of the opposite conductivity type is in contact with the n ⁺ -type buffer layer 6, but may be separated from the n ⁺ -type buffer layer 6. In this case, the drift layer 8 d of the opposite conductivity type is formed at an intermediate height in the drift layer 10.

In the above embodiment, the case where the IGBT is formed in the central region and the n ⁺ -type buffer layer 6 is laminated on the surface of the semiconductor substrate 4 in the peripheral region accordingly has been described. When a MOS is formed in the central region,
The n ⁺ type buffer layer 6 is unnecessary, and an n ⁺ type substrate is used as the substrate. Alternatively, only in the central region where the IGBT is created, n
There is a case where the ⁺ type buffer layer 6 is formed and the n ⁺ type buffer layer 6 is not formed partially in the peripheral region. Even in such a case, by adding a layer (p ⁻ type drift layer) 8 of the opposite conductivity type to the n ⁻ type drift layer 10,
The withstand voltage of the peripheral region is secured. In this case, as shown in FIG. 3, a plurality of p ⁻ -type drift layers 8c and 8d that are locally spread and separated from each other when viewed in a plan view can be added. When using a plurality of opposite conductivity type drift layers that are partially spread and separated from each other when viewed in a plan view, the opposite conductivity type drift layers need to be in contact with the semiconductor substrate. On the other hand, when a layer of the opposite conductivity type is used which extends over the entire peripheral region, or when the buffer layer has a layer of the opposite conductivity type, the opposite conductivity type is also used. Need not be connected to the semiconductor substrate or the buffer layer. Even if they are not connected, the withstand voltage in the peripheral region is ensured.

FIG. 4 shows a fourth embodiment. In this case, the stacked structure of the drain electrode 2, the p ⁺ type semiconductor substrate 4, the n ⁺ type buffer layer 6, the p ⁻ type drift layer 6, and the n ⁻ type drift layer 10 is the same as that in FIG. Further, the IGBT structure formed in the central region is the same as that in FIG. The difference is that the side surface of the semiconductor device has a bevel structure, and at least the outer guard ring 16 is eliminated. At least a part of the inner guard ring 22 is also cut and lost. Even with this bevel structure, it is possible to prevent a high electric field intensity peak value from being generated in the peripheral region, and it is possible to keep the breakdown voltage of the peripheral region high. In each of the embodiments described above, the conductivity types of p and n can be switched.

[0022]

According to the present invention, when a layer of a conductivity type opposite to that of a drift layer is laminated over the entire peripheral region in a peripheral drift layer of a semiconductor device, a structure in which a depletion layer extends from at least two junction surfaces is obtained. The intensity distribution is uniformed in the depth direction of the semiconductor device, so that a large electric field intensity peak does not occur at a specific depth, without increasing the on-voltage in the central region, and without increasing the area of the peripheral region. Thus, the breakdown voltage of the peripheral region can be improved. As illustrated in FIG. 2, when a plurality of layers of the conductivity type opposite to the drift layer are stacked in the peripheral drift layer over the entire peripheral region, the above-described operation can be more efficiently obtained. In the peripheral drift layer, a layer group of the opposite conductivity type to the drift layer is stacked apart from each other in plan view, and the layer group of the opposite conductivity type is formed in contact with the semiconductor substrate of the same conductivity type as the drift layer. Also, a high breakdown voltage can be ensured in the peripheral region. As illustrated in FIG. 3, a layer group of the opposite conductivity type to the drift layer is stacked separately in a peripheral drift layer of the semiconductor device, and a buffer layer and a semiconductor substrate are stacked below the drift layer. However, high withstand voltage can be ensured in the peripheral region. As illustrated in FIGS. 1 to 3, when a guard ring is formed in a peripheral region of the semiconductor device surface, and a layer of the opposite conductivity type is formed within a depth range where a depletion layer extending from the guard ring to the drift layer reaches. In addition, the depletion layer spreads widely, and the breakdown voltage in the peripheral region is effectively improved.

[Brief description of the drawings]

FIG. 1 shows a cross section of a semiconductor device according to a first embodiment.

FIG. 2 shows a cross section of a semiconductor device according to a second embodiment.

FIG. 3 shows a cross section of a semiconductor device according to a third embodiment.

FIG. 4 shows a cross section of a semiconductor device of a fourth embodiment.

FIG. 5 shows a cross section of a conventional semiconductor device.

[Explanation of symbols]

2: drain electrode 4: p ⁺ type semiconductor substrate 6: n ⁺ type buffer layer 8: p ⁻ type drift layer 10: n ⁻ type drift layer 16, 20: p ⁺ type guard ring

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/06 301 H01L 29/06 301D (72) Inventor Takahide Sugiyama Okumachi, Nagakute-cho, Aichi-gun, Aichi Prefecture 41 No. 1 Inside Toyota Central Research Institute Co., Ltd. (72) Inventor Masayasu Ishiko 41-Chome Toyoda Central Research Laboratories Co., Ltd. 1 Toyota Town Inside Toyota Motor Corporation

Claims (5)

[Claims] 1. A semiconductor device, wherein a layer of a conductivity type opposite to that of a drift layer is laminated in a peripheral drift layer of the semiconductor device over the entire peripheral region. 2. The semiconductor device according to claim 1, wherein a plurality of layers of a conductivity type opposite to the drift layer are stacked in the peripheral drift layer of the semiconductor device over the entire peripheral region. 3. A local layer group of the opposite conductivity type to the drift layer is stacked separately in a peripheral drift layer of the semiconductor device in plan view, and the layer group of the opposite conductivity type has the same conductivity as the drift layer. A semiconductor device formed in contact with a semiconductor substrate of a mold. 4. A local layer group of a conductivity type opposite to that of the drift layer is stacked separately in a peripheral drift layer of the semiconductor device in plan view, and a buffer layer and a semiconductor substrate are stacked below the drift layer. A semiconductor device characterized by being performed. 5. The semiconductor device according to claim 1, wherein a guard ring is formed in a peripheral region of the surface of the semiconductor device, and the layer of the opposite conductivity type is formed to a depth reaching a depletion layer extending from the guard ring to the drift layer. The semiconductor device according to claim 1.