CN1316628C - Semiconductor device and its mfg method - Google Patents
Semiconductor device and its mfg method Download PDFInfo
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- CN1316628C CN1316628C CNB2004100741965A CN200410074196A CN1316628C CN 1316628 C CN1316628 C CN 1316628C CN B2004100741965 A CNB2004100741965 A CN B2004100741965A CN 200410074196 A CN200410074196 A CN 200410074196A CN 1316628 C CN1316628 C CN 1316628C
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 96
- 238000000034 method Methods 0.000 title description 12
- 210000000746 body region Anatomy 0.000 claims abstract description 123
- 230000002093 peripheral effect Effects 0.000 claims description 19
- 230000004888 barrier function Effects 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 12
- 230000003685 thermal hair damage Effects 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 24
- 238000004519 manufacturing process Methods 0.000 description 19
- 239000002800 charge carrier Substances 0.000 description 15
- 238000009792 diffusion process Methods 0.000 description 15
- 238000010438 heat treatment Methods 0.000 description 15
- 230000006378 damage Effects 0.000 description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 11
- 229910052796 boron Inorganic materials 0.000 description 11
- 239000011248 coating agent Substances 0.000 description 11
- 238000000576 coating method Methods 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 7
- 229910052698 phosphorus Inorganic materials 0.000 description 7
- 239000011574 phosphorus Substances 0.000 description 7
- GOLXNESZZPUPJE-UHFFFAOYSA-N spiromesifen Chemical compound CC1=CC(C)=CC(C)=C1C(C(O1)=O)=C(OC(=O)CC(C)(C)C)C11CCCC1 GOLXNESZZPUPJE-UHFFFAOYSA-N 0.000 description 7
- 238000012797 qualification Methods 0.000 description 5
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
To prevent thermal damage to a semiconductor device caused in a periphery region, and to obtain a high withstand voltage of the semiconductor device. The semiconductor device has a central region M in which a semiconductor switch element group is formed, and a periphery region N in which a guard ring 38 group surrounding the central region M is formed. A body region 34 of the semiconductor switching element formed in an outermost periphery and a guard ring 38 formed in an innermost periphery are formed in an overlapped manner. Gate wiring 48 connected to a gate electrode 35 of the semiconductor switching element group is opposed to an overlapped region 39 between the body region 34 and the guard ring 38 through an insulating layer 46. The width of the overlapping region 39 is not less than 1/3 of the depth of either the body region 34 or the guard ring 38 whichever is deeper.
Description
Technical field
The present invention relates to make the technology of high withstand voltageization of semiconductor device.The relevant technology of guard ring that particularly relates to and the central area that has formed the thyristor group is fenced up.
Background technology
In order to use aspect the power control, people are developing the semiconductor device of the thyristor group that possesses MOS (metal-oxide semiconductor (MOS)) structure or IGBT (insulated gate bipolar transistor) structure etc.Figure 12 example shows the plane graph of the semiconductor device that possesses the thyristor group.M is the central area among the figure, is the zone that has formed the thyristor group.N is the neighboring area among the figure, and M has enclosed the central area, is positioned at the periphery of Semiconductor substrate 137.In the N of neighboring area, be formed with the guard ring group 138 that the thyristor group is fenced up.Guard ring group 138 is to form in order to improve the withstand voltage of semiconductor device.In the M of central area, be covered with and make the thyristor group become gate electrode group for ON (conducting) (omit and draw), the grating routing 148 that has been connected on this gate electrode group extends across N ground, neighboring area.
Figure 13 is the XIII-XIII line profile of Figure 12.Show the boundary vicinity of central area M and neighboring area N this profile model utility.In addition, the guard ring of neighboring area N, in general, though be to form tens mostly,, in Figure 13, but only showing Monday side 3 guard ring 138a, 138b, 138c, please be careful this point.
Figure 13 example shows the semiconductor device of the thyristor group that possesses the IGBT structure.Begin to possess successively from bottom: collector electrode 120; With this collector electrode 120 the 1st conduction type in succession (be p in this example
+Type) Semiconductor substrate 122; The 2nd conduction type that has been laminated to these Semiconductor substrate 122 tops (is n in this example
+Type) resilient coating 124; The 2nd conduction type that has been laminated to these resilient coating 124 tops (is n in this example
-Type) drift layer 126; The 1st conduction type that forms in this drift layer 126 (is p in this example
-Type) body region 134; The 2nd conduction type that forms in this body region 134 (is n in this example
+Type) emitter region 130; The 1st conduction type that forms in this body region 134 (is p in this example
+Type) body contact area 132, and be present in the gate electrodes 135 that exist insulating barrier 136 subtends in the middle of the body region 134 between this emitter region 130 and the drift layer 126; With emitter region 130 and body contact area 132 emitter electrode 144 in succession.
With emitter region 130, body region 134, drift layer 126, resilient coating 124, centre exist insulating barrier 136 ground and be present in emitter region 130 and drift layer 126 between the gate electrode 135 of body region 134 subtends constitute IGBT structure as unit, this is as IGBT of unit structure, carries out repetition repeatedly at the left of figure.
In addition; when the conducting of thyristor; for example under the high voltage of peak voltage etc. is applied to situation on the semiconductor device; shown in the arrow among Figure 13; be present in the remaining hole in the drift layer 126, punctured pn between guard ring group 138a, 138b, 138c and drift layer 126 tie face near flow in guard ring group 138a, 138b, the 138c behind the depletion layer of formation.Flow into the hole of coming in, discharge to emitter electrode 144 via body region 134 and body contact area 132 from interior all guard ring 138a.Remaining hole then spreads all over adjacent guard ring ground and flows.
Make and can get rid of the hole swimmingly like that, with the p of the thyristor that on most peripheral, has formed
-Form the p that will on interior week, form on the position that the body region 134 of type overlaps each other
+The guard ring 138a of type.Grating routing 148, centre exist insulating barrier 146 ground, with the p of the thyristor of most peripheral
-The body region 134 of type and the p in interior week
+The repeating part subtend of the guard ring 138a of type.
In the semiconductor device of this kind, under the high voltage condition that is applied with peak voltage etc. to semiconductor device, semiconductor device will generate heat in the N of neighboring area, and semiconductor device usually can suffer heat damage.
Summary of the invention
The objective of the invention is to find out the reason of in the N of neighboring area, generating heat, be provided at the semiconductor device that can not cause heat damage in the neighboring area.
The inventor etc.; in the thyristor group that in the central area, has formed MOS structure or IGBT structure etc.; in the neighboring area, formed in the semiconductor device of guard ring group; after at length having studied the phenomenon of in its neighboring area, generating heat; find: the most violent part of generate heat is the body region and the repeat region of the guard ring in interior week of the thyristor of most peripheral.Also find: wherein, exist in the repeat region of insulating barrier and grating routing subtend in the centre, it is the most violent to generate heat.
So when pursuing its reason, find: in the body region of most peripheral with on the section of the repeat region of the guard ring in interior week, exist the zone that the degree of depth shoals partly, the intransitable sectional area minimizing in hole is a key factor.In addition, also find: after being applied with voltage to grating routing, form inversion layer on the top with the zone of grating routing subtend, the sectional area that the hole can be passed through further reduces, and is the another one key factor.Confirm: in the semiconductor device of reality; because grating routing extends to the body region of crosscut most peripheral and the repeat region of the guard ring in interior week; so with the repeat region of grating routing subtend in 2 key factors produce overlappingly, this will bring violent heating.
The inventor etc., owing to obtained above-mentioned new opinion, so successfully prevented the generation of the situation that semiconductor device wrecks because of heating in the neighboring area.
The semiconductor device of being formulated in the present invention has the central area that has formed the thyristor group and has formed the neighboring area of the guard ring group that this central area is fenced up.The body region that possesses the thyristor that on most peripheral, forms; form with the guard ring that forms in interior week with being piled up; be connected to the grating routing on the gate electrode of thyristor group, the centre exists the structure of the repeat region subtend of insulating barrier ground and body region and guard ring.
Semiconductor device of being formulated in the present invention is characterized in that: the width of the repeat region of body region and guard ring (correctly say and refer to the width of measuring the repeat region that the surface of semiconductor regions has exposed from the central area towards neighboring area ground) is more than 1/3 of the degree of depth of the dark side within the degree of depth of the degree of depth of body region and guard ring.
In the conventional semiconductor device, the body region of most peripheral and the guard ring in interior week also carry out overlapping.But; in the conventional semiconductor device; the guard ring in the body region of most peripheral and interior week is as long as contact, owing to recognize and do not make it expressly overlapping necessity that must be greatly, so even if only be that the deviation that exists mask alignment is carried out overlapping with also can contacting the sort of degree.
At least be not the sort of recognize with the part of grating routing subtend on form inversion layer, it is overlapping that the passing through of charge carrier makes it to carry out after the situation that sectional area will reduce.
Therefore, it is inadequate repeating in the conventional semiconductor device, and the width of the repeat region of body region and guard ring does not reach more than 1/3 of the degree of depth of the dark side within the degree of depth of the degree of depth of body region and guard ring.For this reason, with the repeat region of grating routing subtend in, violent heating has taken place owing to said 2 key factors in top.
Research according to inventor etc.; confirm: if the width of the repeat region of body region and guard ring is become more than 1/3 of the degree of depth of the dark side within the degree of depth of the degree of depth of body region and guard ring; then just can tackle effectively for the 1st key factor; even if the supposition charge carrier pass through sectional area because of with the zone of grating routing subtend on formed inversion layer and narrowed down; also can between body region and guard ring, guarantee the sectional area that passes through of sufficient charge carrier, can suppress violent heating.
Here the said degree of depth refers to diffusion depth, the distance till referring to from the surface of semiconductor regions to the degree of depth of conduction type transoid.
The minimum-depth of the repeat region of body region and guard ring is more than 1/2 of the degree of depth of body region, is desirable.
If the repeat region of body region and guard ring is become cross section view, then between body region and guard ring, exist the zone that shoals locally.According to inventor's etc. research, confirm: if guarantee the most shallow degree of depth in other words minimum-depth then can guarantee the guiding path of charge carrier fully in more than 1/2 of the degree of depth of body region, can suppress violent heating.
According to common diffusion conditions,, then can guarantee the minimum-depth more than 1/2 of the degree of depth of body region as if more than 1/3 of the degree of depth of the dark side within the degree of depth of the degree of depth that the width of the repeat region of body region and guard ring is become body region and guard ring.
Under most situation, this side is darker than body region for guard ring.Under this side of guard ring situation darker than body region, it is desirable to the width of the repeat region of body region and guard ring is become more than 2/3 of the degree of depth of body region, become more than 1/3 of the degree of depth of guard ring
If satisfy above-mentioned condition, then can guarantee the guiding path of charge carrier, can suppress violent heating.
According to the present invention, find: resistivity importantly when being applied with the grid conducting voltage to grating routing, the positive following repeat region of grating routing, be below 20 Ω cm.
When being applied with the grid conducting voltage to grating routing, will form inversion layer on the repeat region top of body region and guard ring (with the zone of grating routing subtend), the resistance of repeat region will increase.Even if under the state after resistance increases, if satisfy the resistivity of the repeat region of body region and guard ring is suppressed to condition below the 20 Ω cm, then can guarantee the guiding path of charge carrier fully, can suppress violent heating.
If adopt the present invention, then can be provided in other various gimmicks of the guiding path of guaranteeing charge carrier in the positive following repeat region of grating routing.
A semiconductor device of being formulated in the present invention; it is characterized in that:, be formed with high concentration ground and contain layer with the impurity of body region and the same conduction type of guard ring on the top that comprises with the zone of the repeat region of the body region of grating routing subtend and guard ring.
This high concentration layer is as suppressing or forbidding that the layer that near surface (with the part of grating routing subtend) at body region and guard ring carries out transoid plays a role.Because the voltage of grating routing suppresses or forbids forming inversion layer at the near surface of body region and guard ring, so can suppress the generation of the phenomenon that the guiding path of charge carrier narrows down.This high concentration layer, it is desirable to the grating routing subtend, in addition, comprise that also body region and guard ring carry out forming on the zone in zone of repetition.
In addition; because if utilize this high concentration layer can suppress or forbid then that the near surface of body region and guard ring carries out transoid; so can relax the restriction of the repetition scope of body region and guard ring; therefore; under the situation that will utilize this high concentration layer; even if the width of repeat region less than 1/3 of the degree of depth of the dark side in body region and the guard ring, still can be guaranteed the guiding path of charge carrier fully, can suppress violent heating.
Semiconductor device of being formulated in the present invention is characterized in that: on the top that comprises with the zone of the repeat region of the body region of grating routing subtend and guard ring, be formed with the layer of the impurity that contains the conduction type different with body region and guard ring.
The impurity layer of this films of opposite conductivity can be evaluated as the layer that has carried out transoid originally.Therefore, even if be applied with voltage, also can limit inversion layer and extend to its below always to grating routing.As long as therefore be pre-formed the impurity layer of films of opposite conductivity.Because the voltage of grating routing may be limited to the formation that the near surface of body region and guard ring surpasses the inversion layer of imagination.The generation of the item that the former guiding path that can suppress charge carrier narrows down.The impurity layer of this films of opposite conductivity it is desirable to and the grating routing subtend, and is comprising that body region and guard ring carry out forming on the zone in zone of repetition.
In addition, because if utilize the impurity layer of this films of opposite conductivity, the near surface that then can limit body region and guard ring surpasses the transoid of imagination, so can relax the restriction of the repetition scope of body region and guard ring.Even if the width of repeat region less than 1/3 of the degree of depth of the dark side in body region and the guard ring, also can be guaranteed the guiding path of charge carrier fully, can suppress violent heating.
The present invention when the semiconductor device of the thyristor of the structure that is applied to have the charge carrier that can discharge volume, then will realize useful especially result.The thyristor that this semiconductor device possessed has: collector electrode; Semiconductor substrate with this collector electrode the 1st conduction type in succession; Be laminated to the drift layer of the 2nd conduction type of this Semiconductor substrate top; The body region of the 1st conduction type that in this drift layer, forms; The emitter region of the 2nd conduction type that in this body region, forms; The centre exists insulating barrier ground and is present in the gate electrode of the body region subtend between this emitter region and the drift layer; With emitter region emitter electrode in succession.It is characterized in that: drift layer extends towards the neighboring area, is formed with the guard ring group of the 1st conduction type in this drift layer.In addition, as required, can also between Semiconductor substrate and drift layer, form the resilient coating of the high concentration of the 2nd conduction type.Possess the IGBT structure of this resilient coating, be called PT (break-through) type in general.
Above-mentioned semiconductor device, the thyristor that has utilized IGBT to construct when being applied with high voltage, will be discharged the charge carrier of volume to the body region of most peripheral.If adopt the said any structure in top,, cause destruction because of in the neighboring area, generating heat so can suppress semiconductor device owing to can between the body region of the guard ring in interior week and most peripheral, guarantee wide discharge path.
The present invention in addition, has also produced the new method of making withstand voltage high semiconductor device.In the method, implement to comprising that body region and guard ring carry out repetition, simultaneously with the top of the semiconductor regions in the zone of grating routing subtend, the injection depth as shallow during than organizator zone and guard ring implanting impurity ion and the operation that makes it to spread.
If implement above-mentioned operation, then can make and can form the transoid that the near surface of forbidding or limiting body region and guard ring carries out transoid and prevent layer or transoid limiting layer, making can not cause the semiconductor device of destruction because of heating in the neighboring area.
If adopt semiconductor device of the present invention, then can suppress semiconductor device causes the item of heat damage because of heating in the neighboring area generation, can improve the withstand voltage of semiconductor device.
Description of drawings
Fig. 1 shows the major part oblique view of embodiments of the invention 1.
Fig. 2 shows the relation of the resistivity of overlap ratio and parasitic MOS.
Fig. 3 shows the manufacturing process (1) of embodiments of the invention 1.
Fig. 4 shows the manufacturing process (2) of embodiments of the invention 1.
Fig. 5 shows the manufacturing process (3) of embodiments of the invention 1.
Fig. 6 shows the major part oblique view of embodiments of the invention 2.
Fig. 7 shows the manufacturing process (1) of embodiments of the invention 2.
Fig. 8 shows the manufacturing process (2) of embodiments of the invention 2.
Fig. 9 shows the manufacturing process (3) of embodiments of the invention 2.
Figure 10 shows the manufacturing process (4) of embodiments of the invention 2.
Figure 11 shows the major part oblique view of embodiments of the invention 3.
Figure 12 shows the plane graph of conventional semiconductor device.
Figure 13 shows the major part profile of conventional semiconductor device.
Embodiment
The main feature of the embodiment of the following stated is listed below.
(form 1) is a kind of semiconductor device that has the central area that has formed the thyristor group and formed the neighboring area of the guard ring group that this central area is fenced up, it is characterized in that:
The thyristor of each all has: collector electrode; Semiconductor substrate with this collector electrode the 1st conduction type in succession; Be laminated to the resilient coating of the 2nd conduction type of this Semiconductor substrate top; Drift layer at the 2nd conduction type of this resilient coating superimposed layer; The body region of the 1st conduction type that in this drift layer, forms; The emitter region of the 2nd conduction type that in this body region, forms; The body contact area of the 1st conduction type that in this body region, forms; The centre exists insulating barrier ground and is present in the gate electrode of the body region subtend between this emitter region and the drift layer; With emitter region and body contact area emitter electrode in succession,
Above-mentioned drift layer extends towards ground, neighboring area,
The guard ring group of the 1st conduction type forms in this drift layer,
Form overlappingly in the body region of the thyristor that forms on the most peripheral and the guard ring that on interior week, forms,
Be connected to the grating routing on the gate electrode of thyristor group, the centre exists the repeat region subtend of insulating barrier ground and body region and guard ring.
(form 2) is the semiconductor device of form 1, it is characterized in that: the width of the repeat region of body region and guard ring, more than 1/3 of the degree of depth of the dark side in body region and guard ring.
(form 3) is the semiconductor device of form 1, it is characterized in that: the minimum-depth of the repeat region of body region and guard ring, and in more than 1/2 of the degree of depth of body region.
(form 4) is the semiconductor device of form 1, it is characterized in that: the width of the repeat region of body region and guard ring, and in more than 2/3 of the degree of depth of body region.
(form 5) is the semiconductor device of form 1, it is characterized in that: the resistivity of the body region of the positive bottom of the grating routing when being applied with the grid conducting voltage to grating routing and the repeat region of guard ring is below 20 Ω cm.
(form 6) is the semiconductor device of form 1, it is characterized in that: on the top that comprises with the zone of the repeat region of the body region of grating routing subtend and guard ring, be formed with high concentration ground and contain layer with the impurity of body region and the same conduction type of guard ring.
(form 7) is the semiconductor device of form 1, it is characterized in that: on the top that comprises with the zone of the repeat region of the body region of grating routing subtend and guard ring, be formed with the layer that contains with the impurity of body region and guard ring different conduction-types.
Embodiment
Below, referring to Fig. 1～Figure 11, each embodiment is described.
The semiconductor device of (embodiment 1) embodiment 1 has the central area of the thyristor group that has formed the IGBT structure and has formed the neighboring area of the guard ring group that this central area is fenced up.
Fig. 1 shows the IGBT33 on the most peripheral that is positioned at central area M askance model utility, and near zone (being called repeat region) that the interior all guard rings 38 that form on the N of neighboring area are piled up.
IGBT33 as unit possesses: go up the collector electrode 20 that forms the oxidation aluminum overleaf; With this collector electrode 20 the 1st conduction type in succession (be p in this example
+Type) Semiconductor substrate 22; The 2nd conduction type that has been laminated to these Semiconductor substrate 22 tops (is n in this example
+Type) resilient coating 24; The 2nd conduction type that has been laminated to these resilient coating 24 tops (is n in this example
-Type) drift layer 26; The 1st conduction type that forms in this drift layer 26 (is p in this example
-Type) body region 34; The 2nd conduction type that forms in this body region 34 (is n in this example
+Type) emitter region 30; The 1st conduction type that forms in this body region 34 (is p in this example
+Type) body contact area 32, and be present in the gate electrode 35 that exists insulating barrier 36 subtends in the middle of the body region 34a between this emitter region 30 and the drift layer 26; With emitter region 30 and body contact area 32 emitter electrode in succession.Though emitter electrode does not draw, utilize the incised notch part of gate electrode shown in Figure 1 35, be electrically connected on emitter region 30 and the body contact area 32.
Be connected to the grating routing 48 on the gate electrode 35 of IGBT33; the centre exists insulating barrier 46 ground; with the body region 34 of most peripheral and repeat region 39 subtends of the guard ring 38 in interior week (similar with the planar configuration of prior art shown in Figure 12, this point is please referring to Figure 12).Body region 34 has been mixed boron, and this impurity concentration typically says so 1 * 10
15～1 * 10
18Cm
-3, the thickness of its depth direction is 3～6 microns.In addition, the impurity concentration of the body region 34 of embodiment 1 is 1 * 10
18Cm
-3, its degree of depth is set to 6 microns.
Though Fig. 1 is illustrative is the type of carrying out switch with planar gate electrodes 35.But also can be the trench gate type.Gate electrode 35 can form with metal or polysilicon.
When semiconductor device is drawn as vertical view, in the N of neighboring area, be formed with in the N of neighboring area a plurality of guard rings around a circle, Fig. 1 only shows the p in interior week wherein for convenience's sake
+The guard ring 38 of type.Guard ring 38 has mixed boron, and its impurity concentration typically says to be 1 * 10
16～1 * 10
20Cm
-3, the thickness of its depth direction is 4～8 microns.In addition, the impurity concentration of the guard ring 38 of embodiment 1 is 4 * 10
18Cm
-3, its degree of depth is set to 8 microns.In guard ring 38 tops, the centre exists insulating barrier 46 ground and is equipped with grating routing 48, and grating routing 48 has been connected on the gate electrode 35.In embodiment 1, the area dividing of between gate electrode 35 and grating routing 48, not drawing.When becoming vertical view, then can distinguish gate electrode 35 and grating routing 48 clearly.
As shown in Figure 1, the body region 34 of most peripheral and the guard ring 38 in interior week overlap each other.In repeat region 39, show the body region 34 and the outline line of the guard ring 38 in interior week with imaginary line.So-called repeat region 39 refers to the impurity of wanting organizator zone 34 and the zone that the impurity that will form guard ring 38 all exists, and refers to the zone between 2 imaginary lines.According to inventor's etc. research, distinguish: in order to improve the withstand voltage of semiconductor device, it is important designing repeat region 39 best.
The width of so-called repeat region 39 refers to the width V of the repeat region 39 that will expose on the surface 41 of semiconductor regions.In other words, refer to the interval that 2 imaginary lines shown in Figure 1 expose on the surface 41 of semiconductor regions.The direction of width V will be evaluated as and makes it with consistent towards the direction that neighboring area N advances from central area M.In addition, the minimum-depth W of so-called repeat region 39 refers to the distance till the position that the outline line of outline line and guard ring 38 from the surface 41 of semiconductor regions to body region 34 intersects.
In the semiconductor device of embodiment 1, guard ring 38 forms deeplyer than body region 34.In Fig. 1, be the depth representing of guard ring 38 X.
In the semiconductor device of embodiment 1, the width V on the surface 41 of the semiconductor regions of repeat region 39 formation more than 1/3 of the degree of depth X of guard ring 38.
Fig. 2 shows the measurement result of the resistivity of the repeat region 39 of the grating routing 48 positive bottoms when the width V of the repeat region 39 that makes body region 34 and guard ring 38 changes in the semiconductor device of embodiment 1.Here, resistivity is to measure under the state of being applied with the grid conducting voltage for grating routing 48.The transverse axis of Fig. 2 is the resulting value of width V (being defined as overlap ratio in this manual) of removing repeat region 39 with the degree of depth X of guard ring.The longitudinal axis of Fig. 2 is the resistivity of repeat region 39.This resistivity is to adopt in the outer Monday of body contact area 32 and guard ring 38 to form a pair of electrode on the side end, gives the value of the way mensuration of the voltage that applies regulation between this a pair of electrode.In this case, the resistivity between pair of electrodes is main component with the resistivity of repeat region 39, so just can be evaluated as a pair of interelectrode resistivity the resistivity of repeat region 39.
As shown in Figure 2, as can be known: overlap ratio is big more, and then the resistivity of repeat region 39 is just low more.In addition, dotted line shown in Figure 2 is the critical point that produces heat damage in semiconductor device.Under the resistivity of repeat region 39 situation higher, in semiconductor device, will produce heat damage than dotted line.If below 20 Ω cm, in semiconductor device, just can not produce heat damage in the resistivity of being applied with the repeat region of measuring under the state of grid conducting voltage 39 for grating routing 48.As shown in Figure 2: just can form resistivity below the 20 Ω cm if guarantee the overlap ratio more than 1/3.Even if this be considered to because of with the zone of grating routing 48 subtends on formed inversion layer and make the sectional area that passes through in hole narrow down; if guarantee the overlap ratio more than 1/3; also can between body region 34 and guard ring 38, guarantee the sectional area that passes through in sufficient hole, so resistivity is become below the 20 Ω cm.
In semiconductor device, make the method for repeat region 39 with Fig. 3～Fig. 5 explanation.
Fig. 3 shows the section of the semiconductor regions of manufacturing process.Shown in this section is at n
-P has been formed at the top of the drift layer 26 of type
+The guard ring 38 of type has formed the state of oxide-film 50 on the surface of guard ring 38 and drift layer 23.Illustrated guard ring 38 is the guard rings 38 in interior week.The manufacturing technology that can utilize general epitaxial growth method or ion injection method or other manufacture method to form in addition and utilize in manufacturing process up to now is not subjected to special qualification.
Secondly, as shown in Figure 4, coating forms resist film 52, forms opening and make it graphical on assigned position.Secondly, from this opening boron ion implantation.The amount of the boron that injects or the degree of depth will with consistently determine based on heat treated diffusion property.For example, under the situation of the ion that will use as boron, its diffusion property is about 0.8 times with respect to the diffusion length that spreads to the diffusion length of diffusion in a lateral direction on longitudinal direction.Consider this situation, implement ion and inject, on desirable zone, form diffusion length.
Secondly, as shown in Figure 5, implement heat treatment, the boron diffusion that ion is injected come in.Boron after the diffusion enters in the body region 34, forms repeat region 39.Repeat region 39 main employings make the boron that is injected form to the way of horizontal direction diffusion.
In addition, in this semiconductor device, in general, form guard ring 38 deeplyer than body region 34.,, form with guard ring 38 when overlapping when body region 34 is spread for this reason, the minimum-depth W of this repeat region 39, will follow the surface of repeating zone 39 width V increase and increase.If body region 34 is diffused into always make the width V on the surface of repeat region 39 become for the degree of depth X of guard ring 38 more than 1/3 till, then the minimum-depth W of repeat region 39 will become more than 1/2 of degree of depth Y for body region 34 mostly.In addition, the width V on repeat region 39 surfaces becomes the degree of depth of body region 34 more than 2/3 more.In this case, it is below the 20 Ω cm that the resistivity of repeat region 39 will become, and just can not produce heat damage in semiconductor device.
Show the major part oblique view of the semiconductor device of embodiment 2 (embodiment 2) Fig. 6 model utility.Embodiment 2 is characterised in that: the body region 34 that forms on the thyristor of the most peripheral that is included in central area M; and the top in the zone of the repeat region 39 between the guard ring 38 in the interior week of neighboring area N, possess the layer 60 that contains with the high concentration of the impurity of body region 34 and guard ring 38 same conduction types.
In existing this semiconductor device (not possessing under the situation of layer 60 of high concentration); exist with to be applied on the gate electrode 35 the grid conducting voltage accordingly, with the repeat region 39 of the body region 34 of grating routing 35 subtends and guard ring 38 on form the problem of inversion layer.Particularly under the situation that is applied with high grid conducting voltage, because except that supplying with via repeat region 39 to the hole that body contact area 32 is discharged will increase from the drop ply 22 of neighboring area N one side, the width of the inversion layer that forms on repeat region 39 also will broaden accordingly with high grid conducting voltage, so the guiding path in the hole in this repeat region 39 will narrow down.For this reason, in existing this semiconductor device, such phenomenon will take place significantly: produce the concentrations in hole in this repeat region 39, semiconductor device wrecks.
In the semiconductor device of embodiment 2, form the layer 60 high accordingly with the impurity concentration of body region 34 and guard ring 38 same conduction types with the zone that will form at the inversion layer of grating routing 48 positive bottoms.Have benefited from this layer 60,, also can suppress or forbid the formation of inversion layer on this zone even if under the situation that is applied with high grid conducting voltage.Because the formation of inversion layer is suppressed or is under an embargo, so can guarantee the guiding path in hole fully, the element that concentrations produced that can reduce because of the hole destroys.
In addition, as for the position or the shape of the layer 60 that forms high concentration, not what special qualification is as long as form on the position on the top that comprises repeat region 39 at least.As long as on this position, form at least, just can suppress or forbid becoming the formation of inversion layer of the reason of heat damage.
In addition, if utilize the layer 60 of this high concentration,, can relax the restriction of the repetition scope of body region 34 and guard ring 38 owing to can suppress or forbid transoid at the near surface of body region 34 and guard ring 38.Therefore, utilizing under layer 60 the situation of high concentration,, also can guarantee the guiding path of charge carrier fully, can suppress violent heating even if do not consider relevant restrictions such as width with repeat region 39.
The manufacture method of the semiconductor device of embodiment 2 is described with Fig. 7～Fig. 9.
Fig. 7 shows the section of the semiconductor regions of manufacturing process.Shown in this section is at n
-P has been formed at the top of the drift layer 26 of type
+The body region 34 and the p of type
+The guard ring 38 of type forms oxide-film 50 in its surface, again the state behind these oxide-film 50 top lamination polysilicon films 47.In addition, guard ring 38 is the guard rings 38 in interior week.In addition, can utilize general epitaxial growth method or ion injection method or other manufacture method to form and the manufacturing technology utilized in manufacturing process up to now is not subjected to special qualification.
At first, as shown in Figure 7, adopt and in polysilicon film 47, mix the way formation grating routing that impurity makes it low resistanceization.At this moment the impurity of Shi Yonging is typically said and can be used phosphorus.Phosphorus is difficult to the feature to foreign side's diffusion, so can make it equably to the polysilicon diffusion inside owing to have the diffusion coefficient height.Therefore, under the gate electrode of central area is groove-shaped situation, under the situation of wanting to make impurity always be diffused into dark zone, can use phosphorus satisfactorily.As shown in Figure 8, polysilicon 47 can become with common ion implantation and is grating routing 48.
Secondly, as shown in Figure 9, coating forms resist film 54, forms opening and make it graphical on assigned position.Secondly, to this opening boron ion implantation.
Secondly, as shown in figure 10, implement heat treatment and make the boron that is injected carry out thermal diffusion.By means of this, just can on desirable position, form the layer 60 of high concentration.
If utilize the said manufacture method in top to make the layer 60 of high concentration, then suppress or forbid that it is effective especially forming inversion layer grating routing 48 positive following.
As shown in Figure 7, in the operation that makes polysilicon 47 low resistanceizations, inject carrying out ion in the polysilicon with phosphorus.The part of the phosphorus that this injected is just crossed polysilicon 47 and is injected in the body region 34 or guard ring 38 of its below.In the conventional semiconductor device, just be through with owing to make in this in stage, so only ability is remaining on the surface portion of body region 34 or guard ring 38 a spot of phosphorus (n type impurity) arranged.Therefore, be applied with under the situation of grid conducting voltage for grating routing 48, just be easy at this grating routing 48 positive following inversion layers that form, the result has produced the phenomenon that the guiding path that makes the hole narrows down.
But if adopt manufacture method of the present invention, a spot of phosphorus (n type impurity) remaining in body region 34 or guard ring 38 is owing to forming p
+The boron that the layer that the impurity concentration of type is high injected in 60 o'clock carries out opposite injection in fact and disappears.Therefore and since with the layer 60 corresponding zone of high concentration in be difficult to form inversion layer, can guarantee the guiding path in hole fully, so can obtain the withstand voltage semiconductor device of height.
Show the major part oblique view of the semiconductor device of embodiment 3 (embodiment 3) Figure 11 model utility.
Embodiment 3 is characterised in that: the top in the position of the repeat region of the guard ring 38 in the interior week that comprises the body region 34 that will form and neighboring area N on the most peripheral of central area M, dispose the layer 62 of the high concentration of the conduction type different with body region 34 and guard ring 38.
Just as the semiconductor device of embodiment 3, adopt with the zone that will form the positive following inversion layer of grating routing 48 and form layers 62 high way of the impurity concentration of the conduction type different, the guiding path of formation electronics accordingly with body region 34 and guard ring 38.In the way of the guiding path that adopts the restriction electronics, be applied with under the situation of high grid conducting voltage for grating routing 48, the inversion layer that just can limit formation more extends the below to the layer 62 than high concentration.Therefore, the guiding path in hole can not narrow down.Owing to can guarantee the guiding path in hole fully, so can reduce the element destruction that the concentrations because of the hole forms.
In addition, form the position or the shape of the layer 62 of high concentration, not what special qualification is as long as form on the position on the top that comprises repeat region 39 at least.As long as on this position, form at least, just can suppress or forbid becoming the formation of inversion layer of the reason of heat damage.
In addition, if utilize the layer 62 of this high concentration,, can relax the restriction of the repetition scope of body region 34 and guard ring 38 owing to can suppress or forbid transoid at the near surface of body region 34 and guard ring 38.Therefore, utilizing under layer 69 the situation of high concentration,, also can guarantee the guiding path of charge carrier fully, can suppress violent heating even if do not consider relevant restrictions such as width with repeat region 39.
Though what tell about is the IGBT semiconductor element, also can obtain same effect for other element (controllable silicon, bipolar transistor, MOS) etc. in above embodiment.
Though more than understand concrete example of the present invention in detail, these concrete examples only are a kind of illustrations, are not the qualification to the scope of technical scheme.In the technology of in the scope of technical scheme, being told about, comprise the technology that makes concrete example illustrated above carry out various distortion, change.
In addition, illustrated technology essential factor in this specification or drawing can be brought into play technical serviceability separately or by means of various combinations, the described combination of technical scheme when being not limited to apply for.In addition, illustrated technology in this specification or drawing both can be the sort of technology that realizes a plurality of purposes simultaneously, also can be the technology of the sort of serviceability on possessing skills in realizing one of them purpose this part thing itself.
Claims (4)
1. semiconductor device has the central area that has formed the thyristor group and has formed the neighboring area of the guard ring group that this central area is fenced up, and it is characterized in that:
The body region of the thyristor that forms on most peripheral and the guard ring that forms in interior week form overlappingly,
Be connected to the grating routing on the gate electrode of thyristor group, the centre exists the overlapping region subtend of insulating barrier ground and body region and guard ring,
The width of above-mentioned overlapping region is the dark side's of the degree of depth in body region and the guard ring more than 1/3 or 1/3 of the degree of depth.
2. semiconductor device according to claim 1 is characterized in that: the minimum-depth of above-mentioned overlapping region is more than 1/2 or 1/2 of the degree of depth of body region.
3. semiconductor device according to claim 1 and 2 is characterized in that:
Above-mentioned guard ring forms deeply than above-mentioned body region,
The width of above-mentioned overlapping region is more than 2/3 or 2/3 of the degree of depth of body region, and is more than 1/3 or 1/3 of the degree of depth of guard ring.
4. semiconductor device according to claim 1 is characterized in that:
Thyristor has: collector electrode; Semiconductor substrate with this collector electrode the 1st conduction type in succession; Be laminated to the drift layer of the 2nd conduction type of this Semiconductor substrate top; The body region of the 1st conduction type that in this drift layer, forms; The emitter region of the 2nd conduction type that in this body region, forms; The centre exists insulating barrier ground and is present in the gate electrode of the body region subtend between this emitter region and the drift layer; With emitter region emitter electrode in succession,
Above-mentioned drift layer extends towards the neighboring area,
In this drift layer, be formed with the guard ring group of the 1st conduction type.
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| JP2003308320A JP4264316B2 (en) | 2003-09-01 | 2003-09-01 | Semiconductor device and manufacturing method thereof |
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| JP5286706B2 (en) * | 2007-07-10 | 2013-09-11 | 三菱電機株式会社 | Power semiconductor device and manufacturing method thereof |
| KR100976646B1 (en) | 2008-03-06 | 2010-08-18 | 주식회사 케이이씨 | Power semiconductor device and fabricating method thereof |
| CN103094079B (en) * | 2011-11-07 | 2015-08-19 | 上海华虹宏力半导体制造有限公司 | Improve the method for PowerMOS device UIS performance |
| US9412809B2 (en) * | 2013-02-15 | 2016-08-09 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
| JP2014241367A (en) | 2013-06-12 | 2014-12-25 | 三菱電機株式会社 | Semiconductor element, semiconductor element manufacturing method |
| CN112786683B (en) * | 2020-12-29 | 2022-07-15 | 浙江清华长三角研究院 | Power device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1347158A (en) * | 2000-09-28 | 2002-05-01 | 株式会社东芝 | Semiconductor device and method for mfg. same |
| US6388276B1 (en) * | 2000-07-27 | 2002-05-14 | Mitsubishi Denki Kabushiki Kaisha | Reverse conducting thyristor |
| JP2002343967A (en) * | 2001-05-14 | 2002-11-29 | Toyota Central Res & Dev Lab Inc | Semiconductor device |
| JP2003197898A (en) * | 2001-12-25 | 2003-07-11 | Shindengen Electric Mfg Co Ltd | Planar type semiconductor device |
| JP2003224282A (en) * | 1995-03-15 | 2003-08-08 | Toshiba Corp | High voltage semiconductor element |
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2003
- 2003-09-01 JP JP2003308320A patent/JP4264316B2/en not_active Expired - Fee Related
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003224282A (en) * | 1995-03-15 | 2003-08-08 | Toshiba Corp | High voltage semiconductor element |
| US6388276B1 (en) * | 2000-07-27 | 2002-05-14 | Mitsubishi Denki Kabushiki Kaisha | Reverse conducting thyristor |
| CN1347158A (en) * | 2000-09-28 | 2002-05-01 | 株式会社东芝 | Semiconductor device and method for mfg. same |
| JP2002343967A (en) * | 2001-05-14 | 2002-11-29 | Toyota Central Res & Dev Lab Inc | Semiconductor device |
| JP2003197898A (en) * | 2001-12-25 | 2003-07-11 | Shindengen Electric Mfg Co Ltd | Planar type semiconductor device |
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| JP4264316B2 (en) | 2009-05-13 |
| CN1967869B (en) | 2010-05-26 |
| CN1967869A (en) | 2007-05-23 |
| JP2005079359A (en) | 2005-03-24 |
| CN1591897A (en) | 2005-03-09 |
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