CN103094079B

CN103094079B - Improve the method for PowerMOS device UIS performance

Info

Publication number: CN103094079B
Application number: CN201110348539.2A
Authority: CN
Inventors: 罗清威; 吴晶; 左燕丽
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2011-11-07
Filing date: 2011-11-07
Publication date: 2015-08-19
Anticipated expiration: 2031-11-07
Also published as: CN103094079A

Abstract

The invention discloses a kind of method improving PowerMOS device UIS performance, comprising: on the preparation technology basis of existing power MOS (Metal Oxide Semiconductor) device, injected by twice source electrode, form N+N-source electrode, change parasitic for MOS N+PN pipe into N+N-PN pipe.The present invention, by the Process ba-sis of original power MOS (Metal Oxide Semiconductor) device, does not increase extra light shield, only injecting original Source by once changing twice into, just can obtain the more superior MOS device of UIS performance.

Description

Improve the method for PowerMOS device UIS performance

Technical field

The present invention relates to the method for raising UIS (undamped inductive switching) performance in a kind of semiconductor integrated circuit field, particularly relate to a kind of method improving PowerMOS (MOS) device UIS performance.

Background technology

MOS (metal-oxide semiconductor (MOS)) device, it is the device be made up of metal, oxide (Si02 or SiN) and semiconductor three kinds of materials, it can export larger operating current (a few peace is to tens peaces), for the device of power output stage.

The structure of typical Trench MOS (metal-oxide semiconductor (MOS)) device as shown in Figure 1.This structure utilizes the region between P-base and N+ to form conducting channel, and when Gate termination zero or negative voltage, device is in off state, and when Gate termination positive voltage, device is opened.

Carrying out in UIS test process to this device, general meeting adds 50V voltage by non-clamper inductance at Drain again after Drain holds the inductance of a series connection non-clamper, the pulse enable signal device of an input Microsecond grade is held to open instantaneously to device Gate again, when device is from being opened to turn off process, due to the effect of non-clamper inductance, the ID electric current of device can not sport 0 at once, but is progressively reduced to 0 by ID; In device current ID reduction process, once the pressure drop that the electric current flowing through Source lower zone produces reaches the cut-in voltage of PN junction, the parasitic NPN pipe of MOSFET will be opened, thus device is burnt.

In existing common power MOS device, Source (source electrode) end is by once heavy dose of N-type impurity injection formation, this kind of way can form a N+P type PN junction in Sorce end below, the PN junction of this kind of form is having in metal-oxide-semiconductor UIS test process, open than being easier to make the parasitic NPN pipe of metal-oxide-semiconductor, namely drop on pressure drop on P-base/N+ and be greater than the cut-in voltage of this diode, make MOS device flow through very big current, thus device was lost efficacy in UIS test.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of method improving PowerMOS device UIS performance, the method is by the Process ba-sis of existing power MOS (Metal Oxide Semiconductor) device, only original Source being injected by once changing twice into, the MOS device that UIS performance is more superior can be obtained.

For solving the problems of the technologies described above, the method for raising PowerMOS device UIS performance of the present invention, comprising:

On the preparation technology basis of existing power MOS (Metal Oxide Semiconductor) device, injected by twice source electrode, form N+N-source electrode, change parasitic for MOS N+PN pipe into N+N-PN pipe, effectively reduce MOS parasitic NPN pipe and open, thus improve power MOS (Metal Oxide Semiconductor) device UIS performance.

The step of said method, comprising:

(1) the once heavy dose of source electrode in existing power MOS (Metal Oxide Semiconductor) device preparation technology is injected, change once low dose of P source electrode injection into and inject with once heavy dose of As source electrode;

(2) once anneal, source junction depth is shifted onto the degree of depth of needs.

In described step (1), low dose is 10 ¹³~ 10 ¹⁴cm ^-2, heavy dose is 4 × 10 ¹⁵~ 8 × 10 ¹⁵cm ^-2.

In described step (2), annealing temperature is 900 DEG C ~ 950 DEG C, and annealing time is 30min ~ 60min; The degree of depth is 0.3 μm ~ 0.5 μm.

In the realization of power MOS (Metal Oxide Semiconductor) device concrete technology of the present invention, compared with existing mill run, structure is substantially the same, difference only makes on basis at original power MOS (Metal Oxide Semiconductor) device, does not increase extra light shield, is only injected by a source electrode and becomes twice source electrode injection, N+ source configuration by existing power MOS (Metal Oxide Semiconductor) device changes N+N-source configuration into, in effective minimizing MOS, the unlatching of parasitic NPN pipe, makes device UIS performance obtain larger raising, and does not affect other parameters of device.

Accompanying drawing explanation

Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:

Fig. 1 is typical Trench power MOS device construction generalized section;

Fig. 2 is the power MOS (Metal Oxide Semiconductor) device schematic diagram of integrated Ti metal silicide on grid polycrystalline silicon of the present invention;

Fig. 3 be of the present invention finish first time source inject after structural representation;

Fig. 4 is the structural representation after second time source of the present invention injects;

Fig. 5 be of the present invention annealed after source schematic diagram;

Fig. 6 is that MOS Contact of the present invention opens, the schematic diagram after Contact implant finishes.

Embodiment

The method of raising PowerMOS device UIS performance of the present invention, comprising:

(1) on the preparation technology basis of existing power MOS (Metal Oxide Semiconductor) device, the once heavy dose of source electrode held by original PowerMOS source injects (N-type impurity injection), changes one time 10 into ¹³~ 10 ¹⁴cm ^-2the P source electrode of low dose inject, form N-source, and for one time 4 × 10 ¹⁵~ 8 × 10 ¹⁵cm ^-2heavy dose As source electrode inject, formed N+source;

Wherein, finish the structural representation after source injection for the first time, as shown in Figure 3, known, compared with mill run, structure is substantially the same, and just the N-type impurity concentration of first time Source injection is less, and this step is used for forming darker N-source;

Structural representation after second time source injects, as shown in Figure 4, known, compared with existing (tradition) MOS, now define darker N-source and more shallow N+source;

(2) then carry out the annealing of a 30min ~ 60min at 900 DEG C ~ 950 DEG C, source junction depth is shifted onto the degree of depth (0.3 μm ~ 0.5 μm) of needs, and As and P of source is activated.Wherein, the source schematic diagram after annealed, as shown in Figure 5.

After operating according to the method described above, again according to the preparation technology of existing MOS, carry out MOS Contact open with Contactimplant (injection) after, result as shown in Figure 6, finally can form the power MOS (Metal Oxide Semiconductor) device of integrated Ti metal silicide on grid polycrystalline silicon of the present invention, as shown in Figure 2.

The present invention is on the basis of existing PowerMOS preparation technology, when Source injects, first carry out once low dose of P to inject, then carry out once heavy dose of As to inject, try again annealing (anneal), utilize the injection degree of depth of As and P in Si and the difference of diffusion rate, form N+N-source, hold traditional N+P to tie by source and become N+N-P knot, thus the parasitic N+PN transistor of conventional MOS is changed into N+N-PN pipe, reduce the possibility that MOS parasitic NPN pipe occurs to open, thus PowerMOS device UIS performance is improved.

Claims

1. improve a method for power MOS (Metal Oxide Semiconductor) device undamped inductive switching performance, it is characterized in that, comprising:

On the preparation technology basis of existing power MOS (Metal Oxide Semiconductor) device, injected by twice source electrode, form N+N-source electrode, change parasitic for MOS N+PN pipe into N+N-PN pipe;

Wherein, the source electrode of existing power MOS (Metal Oxide Semiconductor) device is the N+ source electrode formed by once heavy dose of injection, and this heavy dose is 4 × 10 ¹⁵~ 8 × 10 ¹⁵cm ^-2.

2. the method for claim 1, is characterized in that: the step of described method, comprising:

(2) once anneal, source electrode junction depth is shifted onto the degree of depth of needs.

3. method as claimed in claim 2, it is characterized in that: in described step (1), low dose is 10 ¹³~ 10 ¹⁴cm ^-2, heavy dose is 4 × 10 ¹⁵~ 8 × 10 ¹⁵cm ^-2.

4. method as claimed in claim 2, it is characterized in that: in described step (2), annealing temperature is 900 DEG C ~ 950 DEG C, and annealing time is 30min ~ 60min.

5. method as claimed in claim 2, it is characterized in that: in described step (2), the degree of depth is 0.3 μm ~ 0.5 μm.