CN103094079A

CN103094079A - Method for improving power metal oxide semiconductor (MOS) device unclamped inductive switching (UIS) performance

Info

Publication number: CN103094079A
Application number: CN2011103485392A
Authority: CN
Inventors: 罗清威; 吴晶; 左燕丽
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2011-11-07
Filing date: 2011-11-07
Publication date: 2013-05-08
Anticipated expiration: 2031-11-07
Also published as: CN103094079B

Abstract

The invention discloses a method for improving power metal oxide semiconductor (MOS) device unclamped inductive switching (UIS) performance. The method for improving the power MOS device UIS performance includes the following steps: forming N+N- source electrode through twice of source electrode injecting on the basis of an existing power MOS device preparation technology, and replacing MOS parasitic N+PN pipe with N+N-PN pipe. According to the method for improving the power MOS device UIS performance, on the basis of the existing power MOS device technology, the number of an extra photomask is not increased, only is existing source injecting changed from one time to two times, and then MOS device with preferable UIS performance can be obtained.

Description

Improve the method for PowerMOS device UIS performance

Technical field

The present invention relates to the method for raising UIS (the non-clamper inductive switch) performance in a kind of semiconductor integrated circuit field, particularly relate to a kind of method of raising PowerMOS (MOS) device UIS performance.

Background technology

MOS (metal-oxide semiconductor (MOS)) device is the device of being made by metal, oxide (Si02 or SiN) and three kinds of materials of semiconductor, and it can export larger operating current (a few peace to tens peace), is used for the device of power output stage.

The structure of typical Trench MOS (metal-oxide semiconductor (MOS)) device as shown in Figure 1.This structure utilizes the zone between P-base and N+ to form conducting channel, and when Gate termination zero or negative voltage, device is in off state, and when Gate termination positive voltage, device is opened.

In this device is carried out the UIS test process, generally can add 50V voltage by non-clamper inductance at Drain again after the inductance of a non-clamper of Drain end series connection, input again the pulse enable signal device moment unlatching of a Microsecond grade to device Gate end, when device from be opened to turn off process, effect due to non-clamper inductance, the ID electric current of device can not sport 0 at once, but progressively is reduced to 0 by ID; In device current ID reduces process, in case flow through the cut-in voltage that the pressure drop of the electric current generation of Source lower zone reaches PN junction, the parasitic NPN pipe of MOSFET will be opened, thereby device is burnt.

In existing common power MOS device, Source (source electrode) end is by once heavy dose of N-type Impurity injection formation, this kind way can form a N+P type PN junction below the Sorce end, the PN junction of this kind form is in having metal-oxide-semiconductor UIS test process, than being easier to, the parasitic NPN pipe of metal-oxide-semiconductor is opened, namely drop on the upper pressure drop of P-base/N+ greater than the cut-in voltage of this diode, make the MOS device flow through very large electric current, thereby device was lost efficacy in the UIS test.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of method of the PowerMOS of raising device UIS performance, the method is by on the technique basis of existing power MOS (Metal Oxide Semiconductor) device, only original Source is injected by once changing twice into, can obtain the more superior MOS device of UIS performance.

For solving the problems of the technologies described above, the method for raising PowerMOS device UIS performance of the present invention comprises:

On the preparation technology basis of existing power MOS (Metal Oxide Semiconductor) device, inject by twice source electrode, form the N+N-source electrode, change the parasitic N+PN pipe of MOS into the N+N-PN pipe, effectively reduce MOS parasitic NPN pipe and open, thus raising power MOS (Metal Oxide Semiconductor) device UIS performance.

The step of said method comprises:

(1) will have the source electrode injection of the once heavy dose in power MOS (Metal Oxide Semiconductor) device preparation technology now, and change once low dose of P source electrode into and inject and the once As source electrode injection of heavy dose;

(2) once anneal, the source junction depth is shifted onto the degree of depth that needs.

In described step (1), low dose is 10 ¹³～10 ¹⁴cm ^-2, heavy dose is 4 * 10 ¹⁵～8 * 10 ¹⁵cm ^-2

In described step (2), annealing temperature is 900 ℃～950 ℃, and annealing time is 30min～60min; The degree of depth is 0.3 μ m～0.5 μ m.

In the realization of power MOS (Metal Oxide Semiconductor) device concrete technology of the present invention, compare with existing mill run, structure is substantially the same, difference is only made on the basis at original power MOS (Metal Oxide Semiconductor) device, does not increase extra light shield, only a source electrode is injected to become twice source electrode injection, the N+ source configuration that is about to existing power MOS (Metal Oxide Semiconductor) device changes the N+N-source configuration into, effectively reduce the unlatching of parasitic NPN pipe in MOS, make device UIS performance obtain larger raising, and do not affect other parameters of device.

Description of drawings

The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:

Fig. 1 is typical Trench power MOS device construction generalized section;

Fig. 2 is the power MOS (Metal Oxide Semiconductor) device schematic diagram of integrated Ti metal silicide on grid polycrystalline silicon of the present invention;

Fig. 3 is the structural representation of finishing after source for the first time injects of the present invention;

Fig. 4 is the structural representation after source for the second time of the present invention injects;

Fig. 5 is annealed source schematic diagram afterwards of the present invention;

Fig. 6 is that MOS Contact of the present invention opens, the schematic diagram after Contact implant finishes.

Embodiment

The method of raising PowerMOS device UIS performance of the present invention comprises:

(1) on the preparation technology basis of existing power MOS (Metal Oxide Semiconductor) device, the once heavy dose of source electrode of original PowerMOS source end is injected (N-type Impurity injection), change one time 10 into ¹³～10 ¹⁴cm ^-2The P source electrode of low dose inject, form N-source, and one time 4 * 10 ¹⁵～8 * 10 ¹⁵cm ^-2The As source electrode of heavy dose inject, form N+source;

Wherein, finish the structural representation after source injects for the first time, as shown in Figure 3, as can be known, compare with mill run, structure is substantially the same, and just the N-type impurity concentration of Source injection for the first time is less, and this step is used for forming darker N-source;

Structural representation after source injects for the second time as shown in Figure 4, as can be known, is compared with existing (tradition) MOS, has formed darker N-source and more shallow N+source this moment;

(2) then 900 ℃～950 ℃ annealing of carrying out a 30min～60min, the source junction depth is shifted onto the degree of depth (0.3 μ m～0.5 μ m) that needs, and As and the P of source activated.Wherein, annealed source schematic diagram afterwards, as shown in Figure 5.

After operating according to the method described above, again according to the preparation technology who has MOS now, carry out that MOS Contact opens and Contactimplant (injection) after, result as shown in Figure 6, finally can form the power MOS (Metal Oxide Semiconductor) device of integrated Ti metal silicide on grid polycrystalline silicon of the present invention, as shown in Figure 2.

The present invention is on existing PowerMOS preparation technology's basis, when Source injects, first carrying out once low dose of P injects, then carrying out once heavy dose of As injects, annealing (anneal) tries again, utilize As and P in Si the injection degree of depth and the difference of diffusion rate, form N+N-source, be about to the traditional N+P knot of source end and become the N+N-P knot, thereby change the parasitic N+PN transistor of conventional MOS into the N+N-PN pipe, reduce MOS parasitic NPN pipe the possibility of unlatching occurs, thereby PowerMOS device UIS performance is improved.

Claims

1. a method that improves PowerMOS device UIS performance, is characterized in that, comprising:

On the preparation technology basis of existing power MOS (Metal Oxide Semiconductor) device, inject by twice source electrode, form the N+N-source electrode, change the parasitic N+PN pipe of MOS into the N+N-PN pipe.

2. the method for claim 1, it is characterized in that: the step of described method comprises:

3. method as claimed in claim 2, it is characterized in that: in described step (1), low dose is 10 ¹³～10 ¹⁴cm ^-2, heavy dose is 4 * 10 ¹⁵～8 * 10 ¹⁵cm ^-2

4. method as claimed in claim 2, it is characterized in that: in described step (2), annealing temperature is 900 ℃～950 ℃, and annealing time is 30min～60min.

5. method as claimed in claim 2, it is characterized in that: in described step (2), the degree of depth is 0.3 μ m～0.5 μ m.