JP2014229794A - Igbt - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power loss at the turn-off time by preventing short circuit of a collector electrode and a drift layer, preventing the ON-voltage of an IGBT from increasing, and preventing excessive injection of holes into the periphery of the IGBT.SOLUTION: Formation range of a collector electrode is restricted to a range including the central part, where an IGBT is formed, and extending to the outside thereof but not reaching the outside of the periphery, and the formation range of a collector layer is made wider than that of the collector electrode. The ON-voltage is low because the formation range of a collector electrode includes the central part where an IGBT is formed, the collector electrode and drift layer are never short-circuited because the formation range of a collector layer is wider than that of the collector electrode, and the holes are never injected excessively into the periphery because the formation range of a collector electrode does not reach the outside of the periphery.

Description

  In the present specification, an insulated gate bipolar transistor (IGBT) that can suppress an excessive injection of minority carriers into the drift layer and can secure an appropriate potential difference between the drift layer and the collector electrode is disclosed.

  An IGBT normally includes an n-type drift layer, a p-type collector layer, and a collector electrode, and holes are injected from the collector electrode and the p-type collector layer into the n-type drift layer, and the conductivity modulation phenomenon occurs in the n-type drift layer. Is generated. In this specification, a region where the conductivity modulation phenomenon occurs is referred to as a first conductivity type drift layer. It may be called a 1st conductivity type base layer or a 1st conductivity type bulk layer.

  In the IGBT, it is important to inject an appropriate amount of the second conductivity type carrier into the first conductivity type drift layer, and it may be necessary to suppress the second conductivity type carrier from being excessively injected. When the second conductivity type carrier is excessively injected, there arises a problem that, for example, power loss at turn-off increases.

  Therefore, the technique of Patent Document 1 has been proposed. In the technique of Patent Document 1, the p-type collector layer and the collector electrode are formed on a part of the back surface of the n-type drift layer (the surface on the side where the p-type collector layer and the collector electrode are formed). In a normal IGBT, a p-type collector layer and a collector electrode are formed over the entire back surface of the n-type drift layer. On the other hand, as described in Patent Document 1, when the formation range of the p-type collector layer and the collector electrode is restricted, the amount of holes injected into the n-type drift layer is suppressed.

JP 2009-099713 A

  In the technique of Patent Document 1, a p-type collector layer and a collector electrode are stacked on a part of the back surface of the n-type drift layer. The p-type collector layer and the collector electrode have the same size and are formed in the same range. In this structure, the p-type collector layer cannot be interposed between the end portion of the collector electrode and the n-type drift layer, and the end portion of the collector electrode and the n-type drift layer are easily short-circuited. When the collector electrode and the n-type drift layer are short-circuited and the potential difference between the two becomes small, holes are not injected from the p-type collector layer into the n-type drift layer, and the conductivity modulation phenomenon does not occur. The original operation of the IGBT will not be performed.

  In the present specification, the amount of the second conductivity type carriers injected into the first conductivity type drift layer is restricted by restricting the formation range of the collector electrode, and the collector electrode and the first conductivity type drift layer are short-circuited. Therefore, the proper potential difference is maintained between the two conductivity type carriers, whereby the second conductivity type carriers are injected from the second conductivity type collector layer into the first conductivity type drift layer, and the conductivity modulation phenomenon occurs. An IGBT is proposed.

In this specification, each part constituting the IGBT is referred to as an emitter electrode, a first conductivity type emitter region, a second conductivity type body region, a first conductivity type drift layer, a second conductivity type collector layer, a collector electrode, and a gate electrode. The body region may be referred to as a base region, and the drift layer may be referred to as a base layer or a bulk layer. The “layer” in this specification refers to a layer extending along the semiconductor substrate. Depending on the IGBT, the first conductivity type emitter region and the second conductivity type body region do not extend in layers, and may be formed in a local range, and hence are referred to as regions. Depending on the IGBT, the second conductivity type body region may include a high impurity concentration region in ohmic contact with the emitter electrode and a low impurity concentration region formed at a position facing the gate electrode.
In the IGBT, the first conductivity type emitter region is in contact with the emitter electrode, and the second conductivity type collector layer is in contact with the collector electrode. The first conductivity type emitter region and the second conductivity type collector layer are separated by at least the second conductivity type body region and the first conductivity type drift layer, and the second conductivity type body region is located on the first emitter region side. The first conductivity type drift layer is disposed on the second conductivity type collector layer side. The gate electrode is opposed to the second conductivity type body region in a range separating the first conductivity type emitter region and the first conductivity type drift layer via an insulating film.
In the IGBT disclosed in this specification, the formation range of the collector electrode is limited to a part of the formation range of the first conductivity type drift layer, and the formation range of the second conductivity type collector layer includes the formation range of the collector electrode. And it extends to the outside.

  In the above-described IGBT, the collector electrode formation range is limited to a part of the first conductivity type drift layer formation range, the amount of second conductivity type carriers injected into the first conductivity type drift layer is suppressed, and excessively Injection can be suppressed. At the same time, since the formation range of the second conductivity type collector layer includes the collector electrode formation range and extends to the outside thereof, the second conductivity type collector layer also extends between the collector electrode and the first conductivity type drift layer at the end of the collector electrode. A conductive collector layer is interposed. A potential difference in which the second conductivity type carriers move from the collector electrode to the first conductivity type drift layer is secured between the collector electrode and the first conductivity type drift layer, and the conductivity modulation phenomenon occurs in the first conductivity type drift layer. Arise. An IGBT with low power loss can be obtained.

In order to improve the characteristics of the IGBT, the basic structure of the IGBT may be improved. For example, in order to suppress the escape of the second conductivity type carrier to the emitter electrode, the first depth between the second conductivity type body region or the second conductivity type body region and the first conductivity type drift layer is suppressed. A conductive layer may be provided. Alternatively, in order to prevent the depletion layer from reaching the second conductivity type collector layer, a first conductivity type buffer layer may be inserted between the first conductivity type drift layer and the second conductivity type collector layer. The first conductivity type buffer layer contains the first conductivity type impurity at a higher concentration than the first conductivity type drift layer.
The IGBT described in the claims also includes the above-described improvements.

  In an actual semiconductor device, an IGBT is formed in the central portion of the semiconductor substrate and an electric field relaxation structure is formed in the peripheral portion of the semiconductor substrate. In that case, it is preferable that the collector electrode includes the central portion and extends to the outside thereof. That is, it is preferable that the collector electrode is formed over the entire area in the central portion where the IGBT is formed, while the collector electrode is not formed in at least a part of the peripheral portion.

  According to the above structure, since the collector electrode is formed over the entire area in the central portion where the IGBT is formed, an active conductivity modulation phenomenon occurs in the formation range of the IGBT, and the on-voltage decreases. On the other hand, since no collector electrode is formed in at least a part of the peripheral portion, excessive minority carriers are not injected into the drift layer in the peripheral portion, and power loss at turn-off is reduced. According to the above-described IGBT, the collector electrode and the drift layer are not short-circuited, the on-voltage is low, and the power loss during turn-off can be kept low.

When the collector electrode is formed over the entire area in the central portion, but the collector electrode is not formed in at least a part in the peripheral portion, when the semiconductor substrate is viewed in cross section, the outer peripheral edge of the collector electrode is It is preferable that the gate electrode and the first conductivity type drift layer remain at a central portion side with respect to a virtual line toward the side surface of the semiconductor substrate at an inclination angle of 45 ° from a position where the gate electrode and the first conductivity type drift layer are in contact.
A high-concentration region of the second conductivity type impurity may be formed at a position between the central portion where the IGBT is formed and the peripheral portion where the electric field relaxation structure is formed and facing the surface of the semiconductor substrate. In this case, it is preferable that the outer peripheral end of the collector electrode is located below the high concentration region of the second conductivity type impurity when the semiconductor substrate is viewed in cross section.

  In the above case, in the IGBT formation range, the second conductivity type carrier can be injected from the second conductivity type collector layer into the first conductivity type drift layer to obtain an active conductivity modulation phenomenon. It is possible to suppress excessive second conductivity type carriers from being injected into the conductivity type drift layer and to reduce power loss during turn-off.

  When the formation range of the collector electrode is restricted, the formation range of the second conductivity type collector layer may also be restricted, or the second conductivity type collector layer may not be restricted. That is, the second conductivity type collector layer may extend over the entire area of the semiconductor substrate. In this case, a process for restricting the formation range of the second conductivity type collector layer is unnecessary, and the manufacturing process is simplified.

When the collector electrode extends to the outside including the formation range of the IGBT and the second conductivity type collector layer extends to the outside including the formation range of the collector electrode, It is also meaningful to limit the formation range of the two-conductivity type collector layer. When the semiconductor substrate is viewed in cross section, the outer peripheral end of the second conductivity type collector layer is an imaginary line heading toward the side surface of the semiconductor substrate at an inclination angle of 45 ° from the position where the outermost gate electrode and the first conductivity type drift layer are in contact If it stays at the center portion side, an active conductivity modulation phenomenon can be obtained in the IGBT formation range, and excessive injection of the second conductivity type carrier can be suppressed in the peripheral portion.
A high-concentration region of the second conductivity type impurity may be formed at a position between the central portion where the IGBT is formed and the peripheral portion where the electric field relaxation structure is formed and facing the surface of the semiconductor substrate. In this case, when the semiconductor substrate is viewed in cross section, if the outer peripheral edge of the second conductivity type collector layer is located below the high concentration region of the second conductivity type impurity, active conduction is achieved in the IGBT formation range. The degree modulation phenomenon can be obtained, and excessive injection of the second conductivity type carrier can be suppressed in the peripheral portion.

  Details and further improvements of the technology disclosed in this specification will be described in the following “Description of Embodiments” and “Examples”.

It is sectional drawing of the semiconductor device of 1st Example. It is sectional drawing of the semiconductor device of 2nd Example. It is sectional drawing of the semiconductor device of 3rd Example.

The features and the like of the embodiments described below are listed. The claims include those that have these characteristics.
(Feature 1) First conductivity type = n type, second conductivity type = p type, and second conductivity type carrier = hole.
(Feature 2) The second conductivity type body region includes a high impurity concentration region that is in ohmic contact with the emitter electrode, and a low impurity concentration region in which an inversion layer is formed by a gate voltage.
(Feature 3) The second conductivity type body region extends in layers along the surface of the semiconductor substrate.
(Feature 4) A first conductivity type layer is inserted below or in the middle depth of the second conductivity type body region. The first conductivity type layer serves as a barrier against escape of the second conductivity type carriers injected into the first conductivity type drift layer to the emitter electrode.
(Feature 5) A first conductivity type buffer layer is inserted between the first conductivity type drift layer and the second conductivity type collector layer. The first conductivity type buffer layer contains the first conductivity type impurity at a higher concentration than the first conductivity type drift layer. The first conductivity type buffer layer prevents the depletion layer from reaching the second conductivity type collector layer and improves the withstand voltage performance.
(Feature 6) The second conductivity type collector layer extends from the collector electrode formation range beyond the thickness of the second conductivity type collector layer.
(Feature 7) Both the second conductivity type collector layer and the collector electrode extend beyond the central portion to the peripheral portion.

(First embodiment)
FIG. 1 shows a cross-sectional view of the vicinity of the periphery of the semiconductor device 36 of the first embodiment. A semiconductor structure that operates as an IGBT is formed in the central portion A of the semiconductor substrate 26, a structure that relaxes the electric field is formed in the peripheral portion B, and a dicing area C is prepared outside the peripheral portion B. Yes.

  In the central portion A, the Al electrode 4 and the surface electrode 2 are formed on the surface of the semiconductor substrate 26, and the emitter electrode 6 is formed by both. An n-type emitter region 10 is formed at a position facing the surface of the semiconductor substrate. The n-type emitter region 10 is doped with an n-type impurity having a concentration that makes ohmic contact with the emitter electrode 6. A p-type body region 16 is formed in a range surrounding the n-type emitter region 10 and facing the surface of the semiconductor substrate 26. The p-type body region 16 is formed of a high impurity concentration region 12 doped with a p-type impurity having a concentration in ohmic contact with the emitter electrode 6 and a low concentration region 14 of the p-type impurity. The p-type body region 16 extends in layers along the surface of the semiconductor substrate 26. An n-type drift layer 22 is formed below the p-type body region 16. The n-type drift layer 22 is in contact with the surface (that is, the lower surface) of the interface of the p-type body region 16 that is not in contact with the n-type emitter region 10. A p-type collector layer 24 is formed below the n-type drift layer 22. The p-type collector layer 24 is in contact with the surface (that is, the lower surface) of the interface of the n-type drift layer 22 that does not contact the p-type body region 16. The p-type collector layer 24 is formed in a part of the lower surface of the n-type drift layer 22. A collector electrode 28 is formed below the p-type collector layer 24. The collector electrode 28 is in contact with the surface (that is, the lower surface) of the p-type collector layer 24 interface that does not contact the n-type drift layer 22. The collector electrode 28 is formed in a part of the lower surface of the p-type collector layer 24. That is, the formation range of the p-type collector layer 24 includes the formation range of the collector electrode 28 and further extends outward by the distance a. The distance a is larger than the thickness of the p-type collector layer 24. A p-type collector layer 24 is interposed between the collector electrode 28 and the n-type drift layer 22 also at the outer peripheral end 28 a of the collector electrode 28, and the collector electrode 28 and the n-type drift layer 22 connect the p-type collector layer 24. It is prohibited to conduct without going through.

The p-type impurity low concentration region 14 constituting the p-type body region 16 separates the n-type emitter region 10 and the n-type drift layer 22. A trench reaching the n-type drift layer 22 from the surface of the semiconductor substrate 26 is formed. The trench penetrates the n-type emitter region 10 and the p-type body region 16 and reaches the n-type drift layer 22. A gate insulating film 20 is formed on the wall surface of the trench, and a gate electrode 18 is filled inside the gate insulating film 20. The upper surface of the gate electrode 18 is covered with an interlayer insulating film 8. The gate electrode 18 and the emitter electrode 6 are insulated by the interlayer insulating film 8. The gate electrode 18 faces the p body region 14 in a range separating the n-type emitter region 10 and the n-type drift layer 22 with an insulating film 20 interposed therebetween.
The IGBT is used in a state where the emitter electrode 6 is grounded and a positive voltage is applied to the collector electrode 28. If no positive voltage is applied to the gate electrode 18, the n-type emitter region 10 and the n-type drift layer 22 are insulated by the p body region 14, and the emitter electrode 6 and the collector electrode 28 are insulated. When a positive voltage is applied to the gate electrode 18, the low concentration region 14 of the p-type impurity in a range facing the gate electrode 18 through the insulating film 20 is inverted to the n-type, and the n-type emitter region 10 is changed to the n-type. Electrons are injected into the drift layer 22, and as a result, holes are injected into the drift layer 22 from the collector electrode 28 through the collector layer 24. A conductivity modulation phenomenon is obtained in the drift layer 22 and the on-voltage is lowered.

In the first embodiment, the position D of the inversion layer formed along the outermost peripheral gate electrode 18a is used as a reference, and (1) the collector electrode 28 is uniformly formed on the center side, and (2) The collector electrode 28 is not formed on the peripheral side. As described above, (3) the formation range of the p-type collector layer 24 extends outward by the distance a from the formation range of the collector electrode 28.
According to the above (1), holes are injected from the collector electrode 28 into the drift layer 22 through the collector layer 24 in the IGBT formation range. In the formation range of the IGBT, a sufficient amount of holes are injected into the drift layer 22, conductivity modulation is activated, and the on-voltage is lowered. Due to the above (2), the amount of holes injected into the drift layer 22 in the range where the IGBT is not formed is reduced, and the power loss at turn-off is reduced. According to the above (3), the collector electrode 28 and the drift layer 22 are not conducted without passing through the collector layer 24, and an appropriate potential difference is secured between the collector electrode 28 and the drift layer 22. It is possible to reliably obtain a phenomenon in which holes are injected into the drift layer 22 via.
In the first embodiment, the collector electrode 28 is formed on the center side of the inversion layer formed along the outermost peripheral gate electrode 18a, and the collector electrode 28 is formed on the peripheral side. Does not form. On the other hand, the collector layer 24 only needs to extend outward from the formation range of the collector electrode 28 over the thickness of the collector layer 24, and may reach the side surface 26 a of the semiconductor substrate 26.
Although not shown, an n-type layer may be inserted below or in the middle depth of the p-type low-concentration body region 14. The n-type layer serves as a barrier against the holes injected into the n-type drift layer from passing through the emitter electrode 6 and activates the conductivity modulation phenomenon. Further, an n-type buffer layer containing n-type impurities at a higher concentration than the n-type drift layer 22 may be inserted between the n-type drift layer 22 and the p-type collector layer 24. When the n-type buffer layer is inserted, it is possible to prevent the depletion layer extending from the p-type body region 16 from reaching the p-type collector layer 24 and improve the withstand voltage performance.

In the peripheral portion B, the RESURF layer 30 is formed in a range facing the surface of the semiconductor substrate 26. In the dicing region C, an n-type impurity implantation region 32 is formed in a range facing the surface of the semiconductor substrate. When the semiconductor substrate 26 is diced in the dicing region C, the n-type impurity implantation region 32 is exposed on the side surface 26a of the semiconductor substrate 26 that appears as a result of the dicing. In the peripheral portion B and the dicing region C, an insulating film 34 is formed on the surface of the semiconductor substrate 26.
In the peripheral portion B, the desurf layer is stretched toward the side surface 26a of the semiconductor substrate 26 by the RESURF layer 30, and the electric field is relaxed. In the dicing region C, the depletion layer extended toward the side surface 26a of the semiconductor substrate 26 by the n-type impurity implantation region 32 is prevented from reaching the side surface 26a. The peripheral portion B and the dicing region C ensure the breakdown voltage of the semiconductor device 36. In the first embodiment, holes are prevented from being injected into the peripheral portion B and the dicing region C by limiting the formation range of the collector electrode 28.
In the first embodiment, the electric field is relaxed by the RESURF layer 30, but an electric field relaxation structure may be formed using a field limiting ring, a field plate or the like instead of or in addition to this.

(Second embodiment)
Hereinafter, only differences from the first embodiment will be described, and redundant description will be omitted. The same applies to the third embodiment.
In the second embodiment, the p-type collector layer 124 is formed over the entire area facing the back surface of the semiconductor substrate 26. There is no need to limit the formation range of the p-type collector layer 124, and the manufacturing process can be simplified.
The collector electrode 128 extends to the peripheral side beyond the formation position D of the inversion layer formed along the outermost peripheral gate electrode 18a. However, it ends within a range not exceeding the virtual line E. The imaginary line E is a line toward the side surface 26a of the semiconductor substrate 26 at an inclination angle of 45 ° (inclined 45 ° from the perpendicular of the semiconductor substrate 26) from the position where the outermost gate electrode 18a and the n-type drift layer 22 are in contact. It is. Even if the collector electrode 128 extends beyond the formation position of the inversion layer formed along the outermost peripheral gate electrode 18a, the outer peripheral end 128a of the collector electrode 128 has an inclination angle of 45 ° from the formation position of the inversion layer. If it stays inside the imaginary line E toward the side surface 26a, it is possible to prevent excessive injection of holes into the peripheral portion B and the dicing region C, and to reduce power loss during turn-off.

(Third embodiment)
In the third embodiment, the isolation region F is formed between the central portion A where the IGBT is formed and the peripheral portion B where the electric field relaxation structure is formed. In the isolation region F, a region 38 in which p-type impurities are implanted at a high concentration is formed in a range facing the surface of the semiconductor substrate 26. In the third embodiment, the outer peripheral end 228a of the collector electrode 228 is located below the p-type impurity high concentration implantation region 38. Also according to the present embodiment, excessive injection of holes into the peripheral portion B and the dicing region C can be prevented, and power loss at turn-off can be reduced. An insulating film 230 may be formed on the back surface of the semiconductor substrate 26 in a range where the collector electrode 228 is not formed.

As shown in the second embodiment, the outer peripheral end 128a of the collector electrode 128 is more central than the imaginary line E extending at an inclination angle of 45 ° from the formation position of the inversion layer formed along the outermost gate electrode 18a. If the outer peripheral edge 228a of the collector electrode 228 is located below the high concentration implantation region 38 of the p-type impurity as shown in the third embodiment, the peripheral portion B and the dicing region C Holes can be prevented from being excessively injected, and power loss during turn-off can be reduced.
Even when the formation range of the collector electrode is restricted as described above, the outer peripheral ends 28a, 128a, 228a of the collector electrode extend to the peripheral side from the formation position D of the inversion layer formed along the outermost gate electrode 18a. If so, an active conductivity modulation phenomenon occurs in the IGBT region, and the on-voltage does not increase.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
For example, in this embodiment, the case where the first conductivity type is n-type and the second conductivity type is p-type has been described, but the first conductivity type is p-type and the second conductivity type is n-type. There may be.
In addition to restricting the position of the outer peripheral end of the collector electrode, it is also useful to restrict the position of the outer peripheral end of the collector layer. The outer peripheral edge of the collector layer is on the center side of the imaginary line E extending at an inclination angle of 45 ° from the formation position of the inversion layer formed along the outermost peripheral gate electrode 18a, or the height of the p-type impurity If it is located below the concentration injection region 38, it is possible to prevent excessive injection of holes into the peripheral portion B and the dicing region C, and to reduce power loss during turn-off.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

2: Surface electrode 4: Al electrode 6: Emitter electrode 8: Interlayer insulating film 10: n-type emitter region 12: p-type impurity high-concentration body region 14: p-type impurity low-concentration body region 16: p-type body region 18 : Gate electrode 18a: outermost gate electrode 20: gate insulating film 22: n-type drift layer 24: p-type collector layer 26: semiconductor substrate 26a: side surface 28 of the semiconductor substrate: collector electrode 30: RESURF layer 32: n-type impurity Implantation region 34: surface insulating film 36: semiconductor device 38: high concentration implantation region of p-type impurity A: central portion B where IGBT is formed B: peripheral portion C where electric field relaxation structure is formed: dicing area D: Inversion layer formation position E along the outermost peripheral gate electrode: virtual line F extending at an inclination angle of 45 ° from the inversion layer formation position along the outermost peripheral gate electrode: separation region

Claims (7)

An emitter electrode, a first conductivity type emitter region, a second conductivity type body region, a first conductivity type drift layer, a second conductivity type collector layer, a collector electrode, and a gate electrode;
A first conductivity type emitter region is in contact with the emitter electrode;
A second conductivity type collector layer is in contact with the collector electrode;
The first conductivity type emitter region and the second conductivity type collector layer are separated by at least the second conductivity type body region and the first conductivity type drift layer,
The second conductivity type body region is disposed on the first emitter region side, the first conductivity type drift layer is disposed on the second conductivity type collector layer side,
The formation range of the collector electrode is limited to a part of the formation range of the first conductivity type drift layer,
The formation range of the second conductivity type collector layer includes the formation range of the collector electrode and extends to the outside thereof.
An IGBT characterized in that a gate electrode is opposed to a second conductivity type body region in a range separating the first conductivity type emitter region and the first conductivity type drift layer through an insulating film. The structure which comprises IGBT of Claim 1 is formed in the center part of a semiconductor substrate,
An electric field relaxation structure is formed around the semiconductor substrate,
A semiconductor device, wherein a collector electrode includes a central portion and extends outward.   When the semiconductor substrate is viewed in cross section, the outer peripheral end of the collector electrode is at the center side from the imaginary line toward the side surface of the semiconductor substrate at an inclination angle of 45 ° from the position where the outermost peripheral gate electrode and the first conductivity type drift layer are in contact The semiconductor device according to claim 2, wherein: A high-concentration region of the second conductivity type impurity is formed at a position facing the surface of the semiconductor substrate between the central portion where the IGBT is formed and the peripheral portion where the electric field relaxation structure is formed,
3. The semiconductor device according to claim 2, wherein when the semiconductor substrate is viewed in cross section, the outer peripheral end of the collector electrode is located below the high concentration region of the second conductivity type impurity.   5. The semiconductor device according to claim 2, wherein the second conductivity type collector layer extends over the entire area of the semiconductor substrate. 6.   When the semiconductor substrate is viewed in cross section, the outer peripheral end of the second conductivity type collector layer is an imaginary line heading toward the side surface of the semiconductor substrate at an inclination angle of 45 ° from the position where the outermost gate electrode and the first conductivity type drift layer are in contact The semiconductor device according to claim 2, wherein the semiconductor device stays closer to the center. A high-concentration region of the second conductivity type impurity is formed at a position facing the surface of the semiconductor substrate between the central portion where the IGBT is formed and the peripheral portion where the electric field relaxation structure is formed,
3. The semiconductor device according to claim 2, wherein when the semiconductor substrate is viewed in cross section, the outer peripheral end of the second conductivity type collector layer is located below the high concentration region of the second conductivity type impurity.

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