JP6992476B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device.

Conventionally, a semiconductor device having a transistor portion and a diode portion is known (see, for example, Patent Document 1).
Patent Document 1 International Publication No. 2015/068203

In a semiconductor device having a transistor portion and a diode portion (so-called reverse conduction IGBT), it is required to reduce the influence of noise and alleviate the current concentration to improve the destruction resistance of the device. In particular, it is an object of the present invention to provide a semiconductor device capable of alleviating the current concentration of the semiconductor device.

In the first aspect of the present invention, the semiconductor device has a transistor portion and a diode portion, and the transistor portion and the diode portion are formed in an adjacent region to prevent interference between the transistor portion and the diode portion. The transistor portion and the diode portion have a region, and provide a semiconductor device including a plurality of trench portions arranged in a predetermined arrangement direction. The diode portion may be provided with a first conductive type cathode region on the surface of the semiconductor substrate opposite to the front surface side. The width of the diode portion in the arrangement direction may be larger than the width of the transistor portion in the arrangement direction. The cathode region may be provided extending to the boundary region in the arrangement direction.

In the arrangement direction, the width of the diode portion may be 1500 μm or more.

The semiconductor device may include a plurality of transistor portions and a plurality of diode portions. The total area of the plurality of diode portions may be larger than the total area of the plurality of transistor portions.

The semiconductor device includes a gate metal layer provided above the upper surface of the semiconductor substrate, an emitter electrode provided above the upper surface of the semiconductor substrate, and a first conductive type provided on the upper surface side of the semiconductor substrate in the transistor portion. The emitter region, the gate trench portion provided on the upper surface side of the semiconductor substrate in the transistor portion and electrically connected to the gate metal layer and in contact with the emitter region, and the emitter electrode provided on the upper surface side of the semiconductor substrate in the diode portion. Further, an electrically connected emitter trench portion may be provided. The emitter trench portion may be arranged in the transistor portion as well as between the gate trench portions at a constant cycle.

The semiconductor device may further include a dummy trench portion provided on the upper surface side of the semiconductor substrate, electrically connected to the gate metal layer, and not in contact with the emitter region.

The boundary region may be a region having a device structure different from the device structure of the transistor portion and the device structure of the diode portion.

The semiconductor device may further include an interlayer insulating film provided above the upper surface side of the semiconductor substrate, and a contact hole provided in the interlayer insulating film between the trench portions in the transistor portion and the diode portion and in which the emitter electrode is embedded. The interlayer insulating film between the trenches in the boundary region does not have to be provided with a contact hole.

The diode portion may have a boundary region and a non-boundary region. The concentration of the cathode region in the boundary region of the diode portion may be higher than the concentration of the cathode region in the non-boundary region of the diode portion.

The semiconductor device may further include a lower surface lifetime killer provided on the side opposite to the upper surface side of the semiconductor substrate. The diode portion may have a boundary region and a non-boundary region. The concentration of the bottom surface lifetime killer in the boundary region of the diode portion may be lower than the concentration of the bottom surface lifetime killer in the non-boundary region of the diode portion.

The semiconductor device may further include an upper surface lifetime killer introduced at least in the non-boundary region of the diode portion on the upper surface side of the semiconductor substrate. The cathode region may be provided so as to extend toward the transistor portion from the upper surface lifetime killer.

The outline of the above invention does not list all the features of the present invention. A subcombination of these feature groups can also be an invention.

This is an example of a top view of the semiconductor device 100 according to the first embodiment. It is an example of the aa'cross-sectional view of the semiconductor device 100 according to the first embodiment. It is an example of the top view of the semiconductor device 100 which concerns on Example 2. FIG. It is an example of the bb'cross-sectional view of the semiconductor device 100 according to the second embodiment. This is a modification of the semiconductor device 100. It is a top view of the semiconductor device 500 which concerns on a comparative example. An example of the whole chip diagram of the semiconductor device 500 is shown. An example of the whole chip diagram of the semiconductor device 100 is shown. It is a graph which shows the current density distribution. It is a graph which shows the turn-off waveform of the semiconductor device 100 and the semiconductor device 500. The conduction current density distribution of a full-gate semiconductor device is shown. The conduction current density distribution of the semiconductor device having an emitter trench part E is shown. The conduction current density distribution of the semiconductor device having an emitter trench part E is shown. The conduction current density distribution of the semiconductor device having an emitter trench part E is shown. An example of the configuration of the semiconductor device 100 according to the third embodiment is shown. An example of the configuration of the semiconductor device 100 according to the fourth embodiment is shown. An example of the configuration of the semiconductor device 100 according to the fifth embodiment is shown.

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention to which the claims are made. Also, not all combinations of features described in the embodiments are essential to the means of solving the invention.

In the present specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". Of the two main surfaces of the substrate, layer or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "top", "bottom", "front", and "back" are not limited to the direction of gravity or the direction of mounting on a substrate or the like when mounting a semiconductor device.

In the present specification, technical matters may be described using orthogonal coordinate axes of X-axis, Y-axis, and Z-axis. In the present specification, the plane parallel to the upper surface of the semiconductor substrate is defined as the XY plane, and the depth direction of the semiconductor substrate is defined as the Z axis. In the present specification, the case where the semiconductor substrate is viewed in the Z-axis direction is referred to as a plan view.

In each embodiment, an example in which the first conductive type is N type and the second conductive type is P type is shown, but the first conductive type may be P type and the second conductive type may be N type. In this case, the conductive types such as the substrate, the layer, and the region in each embodiment have opposite polarities.

As used herein, it means that in the layer or region labeled with n or p, electrons or holes are a large number of carriers, respectively. Further, + and-attached to n and p mean that the doping concentration is higher and the doping concentration is lower than that of the layer or region to which it is not attached, respectively.

FIG. 1A shows an example of the configuration of the semiconductor device 100 according to the first embodiment. The semiconductor device 100 of this example is a semiconductor chip including a transistor unit 70 and a diode unit 80. For example, the semiconductor device 100 is a reverse conduction IGBT (RC-IGBT: Reverse Conducting IGBT).

The transistor portion 70 is a region having an emitter region 12 and a gate trench portion 40. The transistor portion 70 of this example is a region in which a collector region provided on the lower surface side of the semiconductor substrate 10 is projected onto the upper surface of the semiconductor substrate 10, but the region is not limited to this. The collector region has a second conductive type. The collector area of this example is P + type as an example. The transistor unit 70 includes a transistor such as an IGBT.

The diode section 80 includes a diode such as a freewheeling diode (FWD: Free Wheel Diode) provided adjacent to the transistor section 70 on the upper surface of the semiconductor substrate 10. The diode portion 80 of this example is a region in which the cathode region 82 is projected onto the upper surface of the semiconductor substrate 10, and is a region other than the transistor portion 70, but is not limited to this.

In FIG. 1A, a region around a chip end portion on the edge side of the semiconductor device 100 is shown, and other regions are omitted. In this example, for convenience, the negative edge in the X-axis direction will be described, but the same applies to the other edges of the semiconductor device 100.

The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, or the like. The semiconductor substrate 10 of this example is a silicon substrate.

The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter trench portion 60, a well region 11, an emitter region 12, a base region 14, and a contact region 15 on the upper surface of the semiconductor substrate 10. Further, the semiconductor device 100 of this example includes an emitter electrode 52 and a gate metal layer 50 provided above the upper surface of the semiconductor substrate 10.

The emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal. For example, at least a portion of the emitter electrode 52 may be formed of aluminum, aluminum-silicon alloy or aluminum-silicon-copper alloy. At least a partial region of the gate metal layer 50 may be formed of aluminum, aluminum-silicon alloy or aluminum-silicon-copper alloy. The emitter electrode 52 and the gate metal layer 50 may have a barrier metal formed of titanium, a titanium compound, or the like in the lower layer of a region formed of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

The emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with the interlayer insulating film interposed therebetween. The interlayer insulating film is omitted in FIG. 1A. The interlayer insulating film is provided with a contact hole 49, a contact hole 54, and a contact hole 56 penetrating.

The contact hole 49 connects the gate metal layer 50 and the gate runner 48. A plug made of tungsten or the like may be formed inside the contact hole 49.

The gate runner 48 connects the gate metal layer 50 and the gate trench portion 40 of the transistor portion 70. In one example, the gate runner 48 is connected to the gate conductive portion in the gate trench portion 40 and the dummy conductive portion in the dummy trench portion 30 on the upper surface of the semiconductor substrate 10. The gate runner 48 is not connected to the emitter conductive portion in the emitter trench portion 60. For example, the gate runner 48 is formed of polyether that is doped with impurities or the like.

The gate runner 48 of this example is provided from below the contact hole 49 to the tip of the gate trench portion 40. An interlayer insulating film such as an oxide film is provided between the gate runner 48 and the upper surface of the semiconductor substrate 10. At the tip of the gate trench portion 40, the gate conductive portion is exposed on the upper surface of the semiconductor substrate 10. The gate trench portion 40 comes into contact with the gate runner 48 at the exposed portion of the gate conductive portion.

The contact hole 56 connects the emitter electrode 52 and the emitter conductive portion in the emitter trench portion 60. A plug made of tungsten or the like may be provided inside the contact hole 56.

The connecting portion 25 is provided between the emitter electrode 52 and the emitter conductive portion. The connection portion 25 is a conductive material such as polysilicon doped with impurities. The connecting portion 25 is provided above the upper surface of the semiconductor substrate 10 via an interlayer insulating film such as an oxide film.

The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (Y-axis direction in this example). The gate trench portion 40 of this example has two stretched portions 41 and two stretched portions that are parallel to the upper surface of the semiconductor substrate 10 and stretched along a stretching direction (X-axis direction in this example) perpendicular to the arrangement direction. It may have a connection portion 43 to connect the 41. The gate trench portion 40 of this example is electrically connected to the gate metal layer 50. Further, the gate trench portion 40 is in contact with the emitter region 12.

It is preferable that at least a part of the connecting portion 43 is provided in a curved shape. By connecting the ends of the two stretched portions 41 of the gate trench portion 40, the electric field concentration at the ends of the stretched portion 41 can be relaxed. At the connecting portion 43 of the gate trench portion 40, the gate runner 48 may be connected to the gate conductive portion.

Similar to the gate trench portion 40, the dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (Y-axis direction in this example). Like the gate trench portion 40, the dummy trench portion 30 of this example may have a U-shape on the upper surface of the semiconductor substrate 10. That is, the dummy trench portion 30 may have two stretching portions 31 that stretch along the stretching direction and a connecting portion 33 that connects the two stretching portions 31. The dummy trench portion 30 is electrically connected to the gate metal layer 50. However, the dummy trench portion 30 is different from the gate trench portion 40 in that it is not in contact with the emitter region 12. For example, the semiconductor device 100 can adjust the capacitance between the gate and the emitter by adjusting the ratio of the gate trench portion 40 and the dummy trench portion 30.

Like the gate trench portion 40, the emitter trench portions 60 are arranged at predetermined intervals along a predetermined arrangement direction (Y-axis direction in this example). Like the gate trench portion 40, the emitter trench portion 60 of this example may have a U-shape on the upper surface of the semiconductor substrate 10. That is, the emitter trench portion 60 may have two stretched portions 61 that stretch along the stretching direction and a connecting portion 63 that connects the two stretched portions 61. The emitter trench portion 60 is electrically connected to the emitter electrode 52. For example, by providing the emitter trench portion 60 in the diode portion 80, the potential around the emitter trench portion 60 is less likely to fluctuate.

The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the emitter trench portion 60, the well region 11, the emitter region 12, the base region 14, and the contact region 15.

The well region 11 is a second conductive type region provided on the upper surface side of the semiconductor substrate 10 with respect to the drift region 18 described later. The well region 11 is P + type as an example. The well region 11 is provided in a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40, the dummy trench portion 30, and the emitter trench portion 60. A part of the gate trench portion 40, the dummy trench portion 30, and the emitter trench portion 60 on the gate metal layer 50 side is provided in the well region 11. The bottoms of the ends of the gate trench portion 40, the dummy trench portion 30, and the emitter trench portion 60 in the extending direction may be covered with the well region 11.

The contact hole 54 is provided in the transistor portion 70 above each region of the emitter region 12 and the contact region 15. Further, the contact hole 54 is provided above the base region 14 in the diode portion 80. The contact hole 54 is provided above the contact area 15 in the boundary area 81. As described above, the interlayer insulating film is provided with one or a plurality of contact holes 54. The one or more contact holes 54 may be provided by being stretched in the stretching direction. In Example 1, the contact region 15 is provided on the upper surface of the boundary region 81, but the base region 14 may be provided on the upper surface of the boundary region 81 as in the diode portion 80. This applies not only to Example 1 but also to Examples 2 to 5 described later.

The boundary region 81 is provided in a region where the transistor portion 70 and the diode portion 80 are adjacent to each other. In the present specification, the boundary region 81 is a region in which the transistor portion 70 and the diode portion 80 are provided in adjacent regions to prevent mutual interference. Specifically, the boundary region 81 has a device structure different from the device structure of the transistor unit 70 (so-called MOS structure) and the device structure of a diode such as a freewheeling diode of the diode unit 80. Therefore, the boundary region 81 has a device structure different from the device structure of the transistor portion 70 and the device structure of the diode portion 80, and the device structure and the diode portion in which the channel of the transistor portion 70 is formed in the arrangement direction of the trench portion. It may be a region located between the device structure of 80 diodes.

The device structure of the boundary region 81, which is different from the device structure of the transistor portion 70 and the device structure of the diode portion 80, is, for example, the emitter region 12, the contact region 15, the storage region 16, the trench portion, and the depth of the trench portion, which will be described later. It refers to a region having a device structure different from that of the transistor portion 70 and the diode portion 80 at at least one point of the lifetime killer, the buffer region 20, the cathode region 82, and the collector region 22. As a structural difference in terms of the trench portion, for example, there is a deviation from any periodic structure (repeated structure) of the trench portion of the transistor portion 70 and the trench portion of the diode portion 80. As in this example, the device structure different from the device structure of the transistor part 70 and the device structure of the diode part 80 is only in a single range of the transistor part 70 and the diode part 80 (for example, between a single trench). Even if attention is paid to the periodic structure (repeated structure) of the transistor portion 70 and the diode portion 80, the region may be different from the pattern.

Further, the boundary region 81 may be 10 μm or more and 100 μm or less, and may be 50 μm or more and 100 μm or less. The base point of the length of the boundary region 81 can be, for example, a gate trench portion 40 in which a channel of the transistor portion 70 is formed, and a region of 10 μm or more and 100 μm or less from the gate trench portion 40 toward the diode portion 80. May be the boundary region 81.

The thickness of the semiconductor substrate 10 may be determined according to the withstand voltage of the semiconductor device 100, and the width of the boundary region 81 in the Y-axis direction may be determined according to the thickness of the semiconductor substrate 10. Specifically, the higher the withstand voltage of the semiconductor device 100, the larger the width of the boundary region 81 in the Y-axis direction may be. Further, the width of the boundary region 81 in the Y-axis direction may be determined according to the flow of carriers and the amount of carriers in the semiconductor substrate 10. Specifically, the larger the amount of carriers flowing per unit time between the transistor section 70 and the diode section 80, the wider the width of the boundary region 81 in the Y-axis direction may be. Further, as the amount of carriers in the semiconductor substrate 10 increases, the width of the boundary region 81 in the Y-axis direction may be increased.

The boundary region 81 may have a plurality of mesa portions. More preferably, the boundary region 81 may have 4 or more and 10 or less mesa portions. The base point of the mesa portion of the boundary region 81 can be, for example, the gate trench portion 40 in which the channel of the transistor portion 70 is formed, and 4 or more and 10 or less from the gate trench portion 40 toward the diode portion 80. The mesa portion of the above may be used as the boundary region 81. The width of one mesa portion in the Y-axis direction may be about 10 μm. The length of the four mesas with the three trenches sandwiched in the Y-axis direction may be 50 μm, and the length of the five mesas with the four trenches sandwiched in the Y-axis direction. The size may be 50 μm. Further, the length of the eight mesas portions sandwiching the seven trench portions in the Y-axis direction may be 100 μm, and the length of the ten mesas portions sandwiching the nine trench portions in the Y-axis direction may be 100 μm. May have a length of 100 μm.

By providing the boundary region 81 having a structure different from the non-boundary region 83 of the transistor portion 70 or the diode portion 80, it is possible to reduce current interference with the transistor portion 70 or the diode portion 80. In one example, the larger the width of the boundary region 81 in the Y-axis direction, the more effectively the current interference can be reduced.

In the first embodiment, the boundary region 81 is provided in the diode portion 80. Further, in the first embodiment, the boundary region 81 is a region between the gate trench portion 40 and the emitter trench portion 60 that does not have the emitter region 12. Since the boundary region 81 does not have the emitter region 12, it becomes difficult for the semiconductor device 100 to latch up. The boundary region 81 includes a region in which the gate trench portion 40 of the transistor portion 70 is arranged at a constant cycle in the Y-axis direction and a region in which the emitter trench portion 60 of the diode portion 80 is arranged in a constant cycle in the Y-axis direction. Refers to the area between.

The non-boundary region 83 is a region other than the boundary region 81 in the transistor portion 70 or the diode portion 80. In the first embodiment, since the boundary region 81 is provided in the diode portion 80, the region other than the boundary region 81 of the diode portion 80 is referred to as a non-boundary region 83. In the first embodiment, the non-boundary region 83 is a region different from the boundary region 81 and has an emitter trench portion 60. As described above, the non-boundary region 83 includes a region in which the cathode region 82 is projected onto the upper surface of the semiconductor substrate 10 and the emitter trench portion 60 is arranged at a constant cycle. Since the transistor portion 70 is not provided with the boundary region 81, in this case, the transistor portion 70 as a whole is a non-boundary region.

The dummy trench portion 30 is provided in the boundary region 81. However, the dummy trench portion 30 may also be provided in the non-boundary region 83. The dummy trench portion 30 may be provided only in the non-boundary region 83. Further, the boundary region 81 may be provided with a gate trench portion 40 or an emitter trench portion 60. It should be noted that half or more or all of the trench portions located within the range of the boundary region 81 may be the dummy trench portions 30.

The first mesa portion 91, the second mesa portion 92, and the third mesa portion 93 are mesas portions provided adjacent to each trench portion in the Y-axis direction in a plane parallel to the upper surface of the semiconductor substrate 10. .. The mesa portion is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion from the upper surface of the semiconductor substrate 10 to the depth of the deepest bottom portion of each trench portion. The extended portion of each trench portion may be used as one trench portion. That is, the region sandwiched between the two stretched portions may be the mesa portion.

The first mesa portion 91 is provided adjacent to at least one of the gate trench portion 40 and the emitter trench portion 60 in the transistor portion 70. Further, the first mesa portion 91 of this example is provided adjacent to the transistor portion 70 also in the boundary region 81. The first mesa portion 91 has a well region 11, an emitter region 12, a base region 14, and a contact region 15 on the upper surface of the semiconductor substrate 10. In the first mesa portion 91, the emitter region 12 and the contact region 15 are alternately provided in the stretching direction.

The second mesa portion 92 is a mesa portion provided in the boundary region 81. The second mesa portion 92 has a well region 11, a base region 14, and a contact region 15 on the upper surface of the semiconductor substrate 10. In the first embodiment, the second mesa portion 92 does not have the emitter region 12, but may have the emitter region 12. Further, in the first embodiment, the second mesa portion 92 has the contact region 15, but the contact region 15 does not have to be provided.

The third mesa portion 93 is provided in the diode portion 80 in a region sandwiched between the adjacent emitter trench portions 60. The third mesa portion 93 has a well region 11 and a base region 14 on the upper surface of the semiconductor substrate 10.

The base region 14 is a second conductive type region provided on the upper surface side of the semiconductor substrate 10. The base region 14 is P-type as an example. The base region 14 may be provided on both ends of the first mesa portion 91 and the second mesa portion 92 in the X-axis direction on the upper surface of the semiconductor substrate 10. However, as shown in FIG. 1B, the base region 14 is introduced over almost the entire surface of the active region in the cross section. Note that FIG. 1A shows only one end of the base region 14 in the X-axis direction.

The emitter region 12 is provided in contact with the gate trench portion 40 on the upper surface of the first mesa portion 91. The emitter region 12 may be provided in the Y-axis direction from one of the two trench portions extending in the X-axis direction across the first mesa portion 91 to the other. The emitter region 12 is also provided below the contact hole 54. The emitter region 12 of this example is the first conductive type. The emitter region 12 is N + type as an example.

The contact region 15 is a second conductive type region having a higher doping concentration than the base region 14. The contact region 15 of this example is a P + type as an example. The contact region 15 of this example is provided on the upper surface of the first mesa portion 91. The contact region 15 may be provided in the Y-axis direction from one of the two trench portions extending in the X-axis direction across the first mesa portion 91 to the other. The contact region 15 may or may not be in contact with the gate trench portion 40. Further, the contact region 15 may or may not be in contact with the emitter trench portion 60. The contact region 15 of this example is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact area 15 is also provided below the contact hole 54.

Further, the contact region 15 may also be provided on the upper surface of the second mesa portion 92. The area of the contact region 15 provided on the upper surface of one second mesa portion 92 is larger than the area of the contact region 15 provided on the upper surface of one first mesa portion 91. The contact region 15 on the upper surface of the second mesa portion 92 may be provided over the entire region sandwiched between the base regions 14 provided at both ends of the second mesa portion 92 in the X-axis direction.

The cathode region 82 is a first conductive type region provided on the lower surface side of the semiconductor substrate 10 in the diode portion 80. The cathode region 82 of this example is N + type as an example. The region where the cathode region 82 is provided in a plan view is indicated by a chain double-dashed line.

FIG. 1B is a diagram showing an example of a'a'cross sections in FIG. 1A. The aa'cross section is a YZ plane that passes through the emitter region 12, the base region 14, and the contact region 15 in the transistor portion 70 and the diode portion 80. The semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the aa'cross section. The emitter electrode 52 is provided on the upper surface 21 of the semiconductor substrate 10 and the upper surface of the interlayer insulating film 38.

The drift region 18 is a first conductive type region provided on the semiconductor substrate 10. The drift region 18 of this example is N-type as an example. The drift region 18 may be a region remaining in the semiconductor substrate 10 without forming another doping region. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

The buffer region 20 is a first conductive type region provided below the drift region 18. The buffer area 20 of this example is N-type as an example. The doping concentration in the buffer region 20 is higher than the doping concentration in the drift region 18. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductive type and the cathode region 82 of the first conductive type.

The collector region 22 is a second conductive type region provided on the lower surface side of the semiconductor substrate 10 in the transistor portion 70. The collector area 22 is a P + type as an example. The collector area 22 of this example is provided below the buffer area 20.

The cathode region 82 is provided below the buffer region 20 in the diode portion 80. The boundary R is a boundary between the collector region 22 and the cathode region 82. The boundary R may coincide with or be different from the boundary between the transistor portion 70 and the diode portion 80.

The collector electrode 24 is formed on the lower surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as metal.

The storage region 16 is a first conductive type region provided above the drift region 18 in the first mesa portion 91 and the second mesa portion 92. The storage area 16 of this example is N-type as an example. The storage area 16 is provided in contact with the gate trench portion 40. The storage region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. By providing the storage region 16, the carrier injection promoting effect (IE effect) can be enhanced and the on-voltage of the transistor unit 70 can be reduced. The storage area 16 may be provided in the third mesa section 93.

The base region 14 is a second conductive type region provided above the storage region 16 in the first mesa portion 91, the second mesa portion 92, and the third mesa portion 93. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 of the third mesa portion 93 is a so-called anode region.

The emitter region 12 is provided between the base region 14 and the upper surface 21 in the first mesa portion 91. The emitter region 12 is provided in contact with the gate trench portion 40. The doping concentration of the emitter region 12 is higher than the doping concentration of the drift region 18. An example of a dopant in the emitter region 12 is arsenic (As). The emitter region 12 may or may not be provided in the second mesa portion 92.

The contact region 15 is provided above the accumulation region 16 in the first mesa portion 91 and the second mesa portion 92. The contact region 15 is provided in contact with the gate trench portion 40 and the dummy trench portion 30 in the first mesa portion 91 and the second mesa portion 92.

The one or more gate trench portions 40 and the one or more dummy trench portions 30 are provided on the upper surface 21. Each trench portion is provided from the upper surface 21 to the drift region 18. In the region where at least one of the emitter region 12, the base region 14, the contact region 15 and the storage region 16 is provided, each trench portion also penetrates these regions and reaches the drift region 18. The fact that the trench portion penetrates the doping region is not limited to those manufactured in the order of forming the doping region and then forming the trench portion. Those in which the doping region is formed between the trench portions after the trench portion is formed are also included in those in which the trench portion penetrates the doping region.

The gate trench portion 40 has a gate trench formed on the upper surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed so as to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench and inside the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 and the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered with an interlayer insulating film 38 on the upper surface 21.

The gate conductive portion 44 includes a region facing the adjacent base region 14 on the first mesa portion 91 side with the gate insulating film 42 interposed therebetween in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel, which is an inversion layer of electrons, is formed on the surface layer of the interface of the base region 14 in contact with the gate trench.

The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench formed on the upper surface 21 side, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is formed so as to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 and the semiconductor substrate 10. The dummy trench portion 30 is covered with the interlayer insulating film 38 on the upper surface 21.

The emitter trench portion 60 may have the same structure as the gate trench portion 40 and the dummy trench portion 30. The emitter trench portion 60 has an emitter trench formed on the upper surface 21 side, an emitter insulating film 62, and an emitter conductive portion 64. The emitter insulating film 62 is formed so as to cover the inner wall of the emitter trench. The emitter conductive portion 64 is formed inside the emitter trench and inside the emitter insulating film 62. The emitter insulating film 62 insulates the emitter conductive portion 64 and the semiconductor substrate 10. The emitter trench portion 60 is covered with an interlayer insulating film 38 on the upper surface 21.

The interlayer insulating film 38 is provided above the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is provided with one or a plurality of contact holes 54 for electrically connecting the emitter electrode 52 and the semiconductor substrate 10. Similarly, the other contact holes 49 and the contact holes 54 may be provided so as to penetrate the interlayer insulating film 38. An emitter electrode 52 is provided above the interlayer insulating film 38.

The semiconductor device 100 of this example adjusts the capacitance between the gate and the emitter by adjusting the ratio of the gate trench portion 40 and the dummy trench portion 30. In the semiconductor device 100, the gate-emitter capacitance can be increased by increasing the ratio of the dummy trench portion 30, and the gate-emitter capacitance can be reduced by decreasing the ratio of the dummy trench portion 30. For example, when the number of gate trench portions 40 is G and the number of dummy trench portions 30 is D, the following equation holds.
0.01 <D / (D + G) <0.2

The number of gate trench portions 40 refers to the number of stretched portions 41. That is, even when a plurality of stretched portions 41 are connected by the connecting portion 43 to form one gate trench portion 40, the number of the plurality of stretched portions 41 is substantially the number of gate trenches. It is the number of parts 40. Therefore, the number of gate trench portions 40 coincides with the number of gate trench portions 40 in the aa'cross section as shown in FIG. 1B.

Similarly, the number of dummy trench portions 30 is also substantially the same even when a plurality of stretched portions 31 are connected by the connecting portion 33 to form one dummy trench portion 30. The number of the plurality of stretched portions 31 is the number of the dummy trench portions 30. Therefore, the number of dummy trench portions 30 coincides with the number of buffer regions 20 in the aa'cross section, as shown in FIG. 1B.

FIG. 2A is an example of a top view of the semiconductor device 100 according to the second embodiment. FIG. 2B is a diagram showing an example of a bb'cross section in FIG. 2A. The semiconductor device 100 of the second embodiment is different from the semiconductor device 100 of the first embodiment in that the boundary region 81 is provided in the transistor portion 70. In the semiconductor device 100 of the second embodiment, since the boundary region 81 is provided in the transistor portion 70, the region other than the boundary region 81 of the transistor portion 70 is referred to as a non-boundary region 83. Since the diode portion 80 is not provided with the boundary region 81, in this case, the diode portion 80 as a whole is a non-boundary region.

In the second embodiment, the non-boundary region 83 is a region different from the boundary region 81 and has a gate trench portion 40 and an emitter trench portion 60. As described above, the non-boundary region 83 includes a region in which the collector region 22 is projected onto the upper surface of the semiconductor substrate 10 and the gate trench portion 40 and the emitter trench portion 60 are arranged at regular intervals.

The dummy trench portion 30 is provided in the boundary region 81. However, the dummy trench portion 30 may also be provided in the non-boundary region 83. The dummy trench portion 30 may be provided only in the non-boundary region 83. Further, the boundary region 81 may be provided with a gate trench portion 40 or an emitter trench portion 60.

As described above, providing the boundary region 81 in the transistor portion 70 means that the cathode region 82 is relatively short and the collector region 22 is long. Therefore, the electrons emitted from the emitter region 12 easily flow into the collector region 22, and the on-voltage can be reduced.

The boundary region 81 may be provided so as to straddle the transistor portion 70 and the diode portion 80. In this case, a non-boundary region 83 other than the boundary region 81 is provided in each of the transistor portion 70 and the diode portion 80.

FIG. 3 is a modification of the semiconductor device 100. In the semiconductor device 100 of this example, the contact hole 54 is not provided above at least a part of the second mesa portion 92 adjacent to the dummy trench portion 30 in the boundary region 81. In the semiconductor device 100 of this example, the contact hole 54 is not provided above all the second mesa portions 92 adjacent to the dummy trench portion 30 in the boundary region 81. That is, the second mesa portion 92 adjacent to the dummy trench portion 30 is not electrically connected to the emitter electrode 52. It should be noted that the fact that the contact hole 54 is not provided in a part or all of the mesa portion of the boundary region 81 may be applied to Examples 1 and 2 and Examples 3 to 5 described later.

FIG. 4 is a top view of the semiconductor device 500 according to the comparative example. The semiconductor device 500 of this example is different from the semiconductor device 100 of the first embodiment in that it does not have a dummy trench portion 30. The semiconductor device 500 includes a transistor unit 570 and a diode unit 580.

The semiconductor device 500 has an emitter trench portion 60 on the boundary side of the diode portion 580 with the transistor portion 570. That is, the semiconductor device 500 of this example does not have the dummy trench portion 30 in the boundary region 81. That is, since the trench portion other than the gate trench portion 40 is not connected to the gate metal layer 50, the capacity between the gate and the emitter is smaller than that of the semiconductor device 100 according to the first embodiment.

Here, if noise is generated in the semiconductor device 500 while the semiconductor device 500 is operating in FWD, a potential difference of the threshold voltage Vth or more is generated, and the transistor portion 570 may be erroneously turned on. The smaller the gate-emitter capacitance, the greater the influence of noise on the semiconductor device 500. If the transistor portion 570 is erroneously turned on, a short-circuit current flows during reverse recovery to enter the short-circuit mode, and the semiconductor device 500 may be destroyed.

On the other hand, since the semiconductor device 100 has the dummy trench portion 30, the capacity between the gate and the emitter increases. As a result, even when noise is generated in the semiconductor device 100, the transistor portion 70 is less likely to be erroneously turned on. In this way, providing the dummy trench portion 30 is equivalent to providing the noise cut capacitor. As a result, the influence of noise on the semiconductor device 100 is reduced.

FIG. 5 shows an example of an overall chip view of the semiconductor device 500 according to the comparative example. The semiconductor device 500 of this example includes a plurality of transistor units 570 and a plurality of diode units 580.

In the semiconductor device 500 of this example, the width Wd of the diode portion 580 in the Y-axis direction is smaller than the width Wt of the transistor portion 570 in the Y-axis direction. Further, in this example, the width of the transistor portion 570 in the X-axis direction and the width of the diode portion 580 in the X-axis direction are equal. The total area of the plurality of diode portions 580 is smaller than the total area of the plurality of transistor portions 570.

In the semiconductor device 500, the current on the transistor portion 570 side may gradually concentrate on the diode portion 580 side during switching. In this case, the semiconductor device 500 may locally generate heat and be destroyed. In this way, the current flows uniformly at the time of turn-off, but the current may be concentrated by trying to flow in the cathode region with time. In the semiconductor device 500, the width Wd of the diode portion 580 in the Y-axis direction is smaller than the width Wt of the transistor portion 570 in the Y-axis direction, so that heat generation due to current concentration is remarkable. In particular, when switching at a high current density, the semiconductor device 500 may be destroyed.

FIG. 6 shows an example of an overall view of the chip of the semiconductor device 100. The semiconductor device 100 of this example includes a plurality of transistor units 70 and a plurality of diode units 80. The semiconductor device 100 includes an edge termination region 102 and an outer region 104 outside the active region in which the transistor portion 70 and the diode portion 80 are provided.

The edge termination region 102 relaxes the electric field concentration on the upper surface side of the semiconductor substrate 10. For example, the edge termination region 102 has a guard ring, a field plate, a resurf, and a combined structure thereof.

The outer region 104 is provided adjacent to the transistor portion 70 and the diode portion 80. For example, the outer region 104 includes a gate pad, a sense unit, and a temperature detection unit.

The semiconductor device 100 of this example includes 15 transistor units 70 and 12 diode units 80. In the semiconductor device 100 of this example, the width Wd of the diode portion 80 in the Y-axis direction is equal to or greater than the width Wt of the transistor portion 70 in the Y-axis direction, and is preferably larger than the width Wt in the Y-axis direction. For example, the width Wd of the diode portion 80 in the Y-axis direction may be 500 μm or more, 1000 μm or more, or 1500 μm or more. Further, in this example, the width of the transistor portion 70 in the X-axis direction and the width of the diode portion 80 in the X-axis direction are equal. In the semiconductor device 100 of this example, the total area of the diode portion 80 is equal to or larger than the total area of the transistor portion 70, and is preferably larger than the total area of the transistor portion 70.

In the semiconductor device 100 of this example, since the width Wd of the diode portion 80 in the Y-axis direction is equal to or larger than the width Wt of the transistor portion 70 in the Y-axis direction, the current flowing through the transistor portion 70 reaches the cathode region 82 of the diode portion 80. The current can be relaxed by flowing the current. Therefore, in the semiconductor device 100 of this example, the concentration of the current is relaxed, so that the semiconductor device 100 is less likely to be destroyed.

The total area of the diode portion 80 may be larger than 1.2 times, larger than 1.5 times, or larger than 2.0 times the total area of the transistor portion 70. The ratio of the total area of the transistor unit 70 to the total area of the diode unit 80 is set from the viewpoint of a trade-off between the conduction loss of the semiconductor device 100 and the current concentration. That is, the larger the total area of the transistor portion 70, the smaller the conduction loss tends to be. On the other hand, as the total area of the diode portion 80 increases, the current concentration tends to be relaxed.

When the semiconductor device 100 has a diode unit 80 having a total area equal to or larger than the total area of the transistor unit 70, the gate-emitter capacitance is smaller than when the total area of the diode unit 80 is smaller than the total area of the transistor unit 70. .. However, in the semiconductor device 100 of this example, the reduction of the capacitance between the gate and the emitter can be suppressed by providing the dummy trench portion 30 in the boundary region 81.

In the semiconductor device 100, when the size of the semiconductor chip is fixed, the total area of the diode section 80 may be equal to or larger than the total area of the transistor section 70, and the number of the transistor section 70 and the diode section 80 may be reduced. good. As a result, the region of the interface between the transistor portion 70 and the diode portion 80, that is, the boundary region 81 for preventing mutual interference between the transistor portion 70 and the diode portion 80 is reduced, so that the current loss is reduced.

The semiconductor device 100 of this example includes more transistor units 70 than the diode unit 80 in the Y-axis direction. As a result, transistor portions 70 are arranged at both ends in the Y-axis direction. By providing the transistor portions 70 at both ends in the Y-axis direction, current concentration in the diode portion 80 is less likely to occur.

For example, the semiconductor device 100 of this example includes five transistor units 70 and four diode units 80 in the Y-axis direction. However, the number of the transistor portion 70 and the diode portion 80 in the Y-axis direction is not limited to this. For example, the number of the transistor unit 70 and the diode unit 80 may be four and three, three and two, or two and one. Further, the number of the transistor portion 70 and the diode portion 80 may be six and five, seven and six, or eight and seven. The number of the transistor portion 70 and the diode portion 80 may be the same in the Y-axis direction.

Further, the semiconductor device 100 includes three rows each of a transistor unit 70 and a diode unit 80 in the X-axis direction. However, the number of rows of the transistor portion 70 and the diode portion 80 in the X-axis direction is not limited to this. For example, the number of rows of the transistor portion 70 and the diode portion 80 in the X-axis direction may be one row, two rows, four rows, five rows, or more. There may be.

FIG. 7A is a graph showing the current density distribution. The vertical axis indicates the current density [A / cm ² ], and the horizontal axis indicates an arbitrary position in the Y-axis direction.

The distribution D1 shows the current density distribution when the semiconductor device 100 is used. The semiconductor device 100 of this example shows a case where the ratio of the total area of the transistor unit 70 to the total area of the diode unit 80 is 20:40. That is, the total area of the diode portion 80 corresponds to about 66% of the total area of the transistor portion 70 and the diode portion 80.

The distribution D2 shows the current density distribution when the semiconductor device 100 is used. The semiconductor device 100 of this example shows a case where the ratio of the total area of the transistor unit 70 to the total area of the diode unit 80 is 20:20. That is, the total area of the diode portion 80 corresponds to 50% of the total area of the transistor portion 70 and the diode portion 80.

The distribution D3 shows the current density distribution when the semiconductor device 500 is used. The semiconductor device 500 of this example shows a case where the ratio of the total area of the transistor unit 570 to the total area of the diode unit 580 is 20: 6. That is, the total area of the diode portion 580 corresponds to about 23% of the total area of the transistor portion 570 and the diode portion 580.

Comparing the distributions D1 to D3, the maximum value of the current density decreases as the ratio of the diode portion 80 increases. That is, the semiconductor device 100 can reduce the maximum value of the current density by setting the total area of the diode unit 80 to be equal to or larger than the total area of the transistor unit 70.

FIG. 7B is a graph showing turn-off waveforms of the semiconductor device 100 and the semiconductor device 500. This graph shows the time change of the collector current Ic [A / cm ² ] and the collector-emitter voltage Vce. The collector current Ic of the semiconductor device 100 is larger than the collector current Ic of the semiconductor device 500. That is, the semiconductor device 100 can realize switching with a higher current density than the semiconductor device 500 by making the width of the diode section 80 larger than the width of the transistor section 70.

8A to 8D are diagrams for comparing the conduction current density distribution when the ratio of the gate trench portion G and the emitter trench portion E is changed. The vertical axis shows the conduction current density distribution [A / cm ² ], and the horizontal axis shows the positions in the Y-axis direction near the transistor portion and the diode portion. The gate trench portion G is a trench portion that is electrically connected to the gate metal layer 50 and is provided in contact with the emitter region 12. The emitter trench portion E is a trench portion electrically connected to the emitter electrode 52.

FIG. 8A shows the conduction current density distribution of a full-gate semiconductor device. In the semiconductor device of this example, all the trench portions are gate trench portions G. That is, in the semiconductor device of this example, all the trench portions are electrically connected to the gate metal layer 50.

FIG. 8B shows the conduction current density distribution of the semiconductor device having the emitter trench portion E. In the semiconductor device of this example, the gate trench portion G and the emitter trench portion E are provided at a ratio of 2: 1. That is, in the semiconductor device of this example, the number of gate trench portions G is larger than the number of emitter trench portions E.

FIG. 8C shows the conduction current density distribution of the semiconductor device having the emitter trench portion E. In the semiconductor device 500 of this example, the gate trench portion G and the emitter trench portion E are provided at a ratio of 1: 1. That is, in the semiconductor device of this example, the number of gate trench portions G is equal to the number of emitter trench portions E.

FIG. 8D shows the conduction current density distribution of the semiconductor device having the emitter trench portion E. In the semiconductor device 500 of this example, the gate trench portion G and the emitter trench portion E are provided at a ratio of 1: 2. That is, in the semiconductor device of this example, the number of gate trench portions G is smaller than the number of emitter trench portions E.

Referring to the conduction current density distributions of FIGS. 8A to 8D, the conduction current density distribution tends to be widened by increasing the ratio of the emitter trench portion E to that of the gate trench portion G. For example, the conduction current density distribution in FIG. 8A tends to be localized to a specific region as compared with other examples. Further, by increasing the ratio of the emitter trench portion E, the channel region is reduced, so that the maximum value of the conduction current tends to increase.

Here, an example of a method for designing a semiconductor device 100 in which the influence of noise is reduced while suppressing current concentration is shown. In a full-gate semiconductor device, all the trench portions are electrically connected to the gate metal layer 50, and the potential around the trench portions may fluctuate. Therefore, it is preferable that the semiconductor device has both a gate trench portion G and an emitter trench portion E. However, as shown in FIGS. 8A to 8D, when the ratio of the emitter trench portion E to that of the gate trench portion G is increased, the maximum value of the conduction current density distribution tends to increase.

If the ratio of the total area of the diode unit 80 to the total area of the transistor unit 70 is increased in order to suppress the maximum value of the conduction current density distribution, the destruction of the semiconductor device 100 can be suppressed. In particular, in the first embodiment, the boundary region 81 is provided in the diode portion 80. By providing the boundary region 81 in the diode portion 80, the cathode region 82 becomes relatively long and the collector region 22 becomes short. Therefore, the electrons emitted from the emitter region 12 tend to flow into the cathode region 82, and the maximum value of the current density can be effectively reduced.

On the other hand, if the ratio of the total area of the diode portion 80 to the total area of the transistor portion 70 is increased, the capacitance between the gate and the emitter decreases. Therefore, by providing the dummy trench portion 30 in the boundary region 81, the semiconductor device 100 can secure the capacitance between the gate and the emitter while relaxing the current concentration by increasing the diode portion 80. As a result, it is possible to realize the semiconductor device 100 having less influence of noise while suppressing the destruction of the element due to the current concentration.

The dummy trench portion 30 described above is not limited to the boundary region 81 in which the transistor portion 70 and the diode portion 80 are adjacent to each other, but extends in the X-axis direction toward the edge termination region 102 of the transistor portion 70 adjacent to the edge termination region 102. It may be provided so as to do so. That is, a dummy trench portion 30 that is not in contact with the emitter region 12 may be provided on the edge termination region 102 side of the transistor portion 70 adjacent to the edge termination region 102. The edge end region 102 side of the transistor portion 70 in which the dummy trench portion 30 is provided is shown by a broken line as an edge adjacent region 84. The edge adjacent region 84 is a region adjacent to the edge end region 102 on the positive side or the negative side of the transistor portion 70 in the Y-axis direction. As a result, the capacitance between the gate and the emitter can be secured, and an invalid region that does not function as a transistor can be formed on the edge termination region 102 side of the transistor portion 70, and the concentration of carriers can be suppressed. Therefore, the number of dummy trench portions 30 inserted in the edge adjacent region 84 may be larger than the number of dummy trench portions 30 inserted in the boundary region 81. Further, the dummy trench portion 30 may be provided only in the edge adjacent region 84. In providing the dummy trench portion 30 in the edge adjacent region 84, the width Wt of the transistor portion 70 in the Y-axis direction and the width Wd of the diode portion 80 in the Y-axis direction are not limited.

FIG. 9 shows an example of the configuration of the semiconductor device 100 according to the third embodiment. The semiconductor device 100 of this example is different from the semiconductor device 100 according to the first embodiment in that it includes a top surface lifetime killer 95 and a bottom surface lifetime killer 96.

The top lifetime killer 95 and the bottom lifetime killer 96 are used to adjust the lifetime of the carrier. The upper surface lifetime killer 95 and the lower surface lifetime killer 96 are provided by injecting ions from the upper surface side or the lower surface side of the semiconductor substrate 10. For example, the upper surface lifetime killer 95 and the lower surface lifetime killer 96 are formed by injecting helium.

The upper surface lifetime killer 95 is provided on the upper surface side of the semiconductor substrate 10. For example, the upper surface lifetime killer 95 of the third embodiment is provided in the diode portion 80. The upper surface lifetime killer 95 of this example is provided extending from the non-boundary region 83 to at least a part of the boundary region 81. The upper surface lifetime killer 95 can reduce the tail current and reduce the reverse recovery loss Err by reducing the carrier lifetime on the anode region side of the diode portion 80.

The upper surface lifetime killer 95 may or may not be provided in the transistor portion 70. That is, the upper surface lifetime killer 95 of this example is provided extending from the non-boundary region 83 to the middle of the boundary region 81, but may be provided extending to the boundary R or beyond the boundary R. It may be provided by extending to the transistor portion 70. Further, in this example, the region provided on the lower surface side of the semiconductor substrate 10 is projected onto the upper surface of the semiconductor substrate 10, the region is projected onto the transistor portion 70, and the cathode region 82 is projected onto the upper surface of the semiconductor substrate 10. The region other than the portion 70 is the diode portion 80. However, the region where the upper surface lifetime killer 95 is not provided may be the transistor portion 70, and the region where the upper surface lifetime killer 95 is provided may be the diode portion 80.

The bottom surface lifetime killer 96 is provided on the bottom surface side of the semiconductor substrate 10. The bottom surface lifetime killer 96 of this example is provided in both the transistor portion 70 and the diode portion 80. The concentration of the bottom surface lifetime killer 96 may be lower on the transistor portion 70 side than on the diode portion 80 side. For example, the concentration of the lower surface lifetime killer 96 in the boundary region 81 of the diode portion 80 is lower than the concentration of the lower surface lifetime killer 96 in the non-boundary region 83 of the diode portion 80. As a result, the current easily flows in the cathode region 82, and the concentration of the current in the transistor portion 70 is easily relaxed.

The cathode region 82 is provided so as to extend toward the transistor portion 70 from the upper surface lifetime killer 95. As a result, the current easily flows in the cathode region 82, and the concentration of the current in the transistor portion 70 is easily relaxed.

Further, the concentration of the cathode region 82 may be higher on the transistor portion 70 side than on the diode portion 80 side. For example, the concentration of the cathode region 82 in the boundary region 81 of the diode portion 80 is higher than the concentration of the cathode region 82 in the non-boundary region 83 of the diode portion 80. As a result, the current is more likely to flow in the cathode region 82, and the concentration of the current in the transistor portion 70 is more likely to be relaxed.

FIG. 10 shows an example of the configuration of the semiconductor device 100 according to the fourth embodiment. The semiconductor device 100 of this example differs from the semiconductor device 100 according to the first embodiment in the structure of the boundary region 81.

The storage region 16 is provided in the transistor portion 70. However, the storage area 16 is not provided in the boundary area 81. That is, the storage region 16 is not provided in the second mesa portion 92 adjacent to the dummy trench portion 30. On the other hand, the second mesa portion 92 is provided with a contact region 15. Since the semiconductor device 100 of this example does not have the storage region 16 in the second mesa portion 92 sandwiched between the dummy trench portions 30, holes can be easily pulled out to the emitter electrode 52 in the boundary region 81.

FIG. 11 shows an example of the configuration of the semiconductor device 100 according to the fifth embodiment. In the semiconductor device 100 of this example, the structure of the dummy trench portion 30 is different from that of the semiconductor device 100 according to the first embodiment.

The dummy trench portion 30 has a shape different from that of the gate trench portion 40 and the emitter trench portion 60. The dummy trench portion 30 of this example can adjust the gate-emitter capacitance of the semiconductor device 100 by adjusting the insulating film in the trench and the trench depth.

The film thickness of the dummy insulating film 32 is thinner than that of the gate insulating film 42 and the emitter insulating film 62. This increases the capacity between the gate and emitter of the semiconductor device 100. In this example, the film thickness of the dummy insulating film 32 is reduced without changing the width of the trench formed on the upper surface side of the semiconductor substrate 10. However, by increasing the width of the trench for providing the gate trench portion 40 and the emitter trench portion 60 and increasing the film thickness of the gate insulating film 42 and the emitter insulating film 62, the film of the dummy insulating film 32 is relatively thick. The thickness may be reduced.

The trench depth of the dummy trench portion 30 is deeper than the trench depth of the gate trench portion 40 and the trench depth of the emitter trench portion 60. This increases the capacity between the gate and emitter of the semiconductor device 100. In this example, the trench depth of the dummy trench portion 30 is deepened, but by making the depth of the trench for providing the gate trench portion 40 and the emitter trench portion 60 shallow, the dummy trench portion is relatively relatively deep. The trench depth of 30 may be increased.

In the semiconductor device 100 of this example, the gate-emitter capacitance can be increased by reducing the film thickness of the dummy insulating film 32 and increasing the trench depth of the dummy trench portion 30. As a result, the influence of noise on the semiconductor device 100 is reduced. The semiconductor device 100 may increase the gate-emitter capacitance by adjusting either the film thickness of the dummy insulating film 32 or the trench depth of the dummy trench portion 30.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that the form with such changes or improvements may be included in the technical scope of the present invention.

The order of execution of each process such as operation, procedure, step, and step in the apparatus, system, program, and method shown in the claims, specification, and drawings is particularly "before" and "prior to". It should be noted that it can be realized in any order unless the output of the previous process is used in the subsequent process. Even if the scope of claims, the specification, and the operation flow in the drawings are explained using "first", "next", etc. for convenience, it means that it is essential to carry out in this order. It's not a thing.

10 ... Semiconductor substrate, 11 ... Well region, 12 ... Emitter region, 14 ... Base region, 15 ... Contact region, 16 ... Storage region, 18 ... Drift region, 20 ... Buffer area, 21 ... Top surface, 22 ... Collector area, 23 ... Bottom surface, 24 ... Collector electrode, 25 ... Connection part, 30 ... Dummy trench part, 31 ... -Stretched portion, 32 ... Dummy insulating film, 33 ... Connection portion, 34 ... Dummy conductive portion, 38 ... Interlayer insulating film, 40 ... Gate trench portion, 41 ... Stretched portion, 42 ... Gate insulating film, 43 ... Connection part, 44 ... Gate conductive part, 48 ... Gate runner, 49 ... Contact hole, 50 ... Gate metal layer, 52 ... Emitter Electrodes, 54 ... contact holes, 56 ... contact holes, 60 ... emitter trenches, 61 ... stretched parts, 62 ... emitter insulating film, 63 ... connection parts, 64 ... Emitter conductive part, 70 ... Transistor part, 80 ... Diode part, 81 ... Boundary region, 82 ... Cathode region, 83 ... Non-boundary region, 84 ... Edge adjacent region, 91. 1st mesa part, 92 ... 2nd mesa part, 93 ... 3rd mesa part, 95 ... upper surface lifetime killer, 96 ... lower surface lifetime killer, 100 ... semiconductor device, 102 ... edge termination region, 104 ... outer region, 500 ... semiconductor device, 570 ... transistor section, 580 ... diode section

Claims (10)

A semiconductor device having a transistor part and a diode part.
The transistor portion and the diode portion are formed in an adjacent region, and have a boundary region for preventing interference between the transistor portion and the diode portion.
The transistor portion and the diode portion include a plurality of trench portions arranged in a predetermined arrangement direction.
The diode portion includes a first conductive type cathode region on a surface opposite to the front surface side of the semiconductor substrate.
The width of the diode portion in the arrangement direction is larger than the width of the transistor portion in the arrangement direction.
The cathode region is a semiconductor device provided so as to extend to the boundary region in the arrangement direction. The semiconductor device according to claim 1, wherein the width of the diode portion is 1500 μm or more in the arrangement direction. Equipped with multiple transistor sections and multiple diode sections,
The semiconductor device according to claim 1 or 2, wherein the total area of the plurality of diode portions is larger than the total area of the plurality of transistor portions. A gate metal layer provided above the upper surface of the semiconductor substrate and
An emitter electrode provided above the upper surface of the semiconductor substrate and
In the transistor portion, a first conductive type emitter region provided on the upper surface side of the semiconductor substrate and
A gate trench portion provided on the upper surface side of the semiconductor substrate in the transistor portion, electrically connected to the gate metal layer, and in contact with the emitter region.
The diode portion further includes an emitter trench portion provided on the upper surface side of the semiconductor substrate and electrically connected to the emitter electrode.
The semiconductor device according to any one of claims 1 to 3, wherein the emitter trench portion is also arranged in the transistor portion between the gate trench portions at a constant cycle. The semiconductor device according to claim 4, further comprising a dummy trench portion provided on the upper surface side of the semiconductor substrate, electrically connected to the gate metal layer, and not in contact with the emitter region. The semiconductor device according to any one of claims 1 to 5, wherein the boundary region is a region having a device structure different from the device structure of the transistor portion and the device structure of the diode portion. An interlayer insulating film provided above the upper surface side of the semiconductor substrate, and
The transistor portion and the diode portion are further provided with a contact hole provided in the interlayer insulating film between the trench portions and in which an emitter electrode is embedded.
The semiconductor device according to any one of claims 1 to 6, wherein the interlayer insulating film between the trench portions in the boundary region is not provided with the contact hole. The diode portion has the boundary region and the non-boundary region.
The semiconductor device according to any one of claims 1 to 7, wherein the concentration of the cathode region in the boundary region of the diode portion is higher than the concentration of the cathode region in the non-boundary region of the diode portion. Further, a lower surface lifetime killer provided on the side opposite to the upper surface side of the semiconductor substrate is further provided.
The diode portion has the boundary region and the non-boundary region.
The semiconductor according to any one of claims 1 to 8, wherein the concentration of the lower surface lifetime killer in the boundary region of the diode portion is lower than the concentration of the lower surface lifetime killer in the non-boundary region of the diode portion. Device. On the upper surface side of the semiconductor substrate, a top surface lifetime killer introduced at least in the non-boundary region of the diode portion is further provided.
The semiconductor device according to any one of claims 1 to 9, wherein the cathode region is provided so as to extend toward the transistor portion from the upper surface lifetime killer.

Images