JP2019106506A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device including a transistor part and a diode part.SOLUTION: A semiconductor device including a transistor part and a diode part has: a boundary region formed in a region where the transistor part and the diode part are adjacent to each other, for preventing interference between the transistor part and the diode part; and a plurality of trenches arranged in a predetermined arrangement direction in the transistor part and the diode part. The diode part may include a first conductivity type cathode region on a surface of a substrate opposite to a surface side. A width of the diode part in the arrangement direction may be greater than a width of the transistor part in the arrangement direction. The cathode region may extend to the boundary region in the arrangement direction.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a semiconductor device.

Conventionally, a semiconductor device having a transistor portion and a diode portion is known (see, for example, Patent Document 1).
Patent Document 1 International Publication No. 2015/068203

  In a semiconductor device having a transistor portion and a diode portion (so-called reverse conducting IGBT), it is required to improve the breakdown resistance of the element by reducing the influence of noise or reducing the concentration of current. In particular, it is an object of the present invention to provide a semiconductor device capable of alleviating current concentration of the semiconductor device.

  According to a first aspect of the present invention, there is provided a semiconductor device having a transistor portion and a diode portion, wherein the transistor portion and the diode portion are formed in an adjacent region and a boundary for preventing interference between the transistor portion and the diode portion. Provided is a semiconductor device having a region, and a transistor portion and a diode portion including a plurality of trench portions arranged in a predetermined arrangement direction. The diode portion may include a cathode region of the first conductivity type on the surface opposite to the front surface side of the semiconductor substrate. The width in the arrangement direction of the diode parts may be larger than the width in the arrangement direction of the transistor parts. The cathode region may be extended to the boundary region in the arrangement direction.

  In the arrangement direction, the width of the diode portion may be 1500 μm or more.

  The semiconductor device may include a plurality of transistor portions and a plurality of diode portions. The total area of the plurality of diode parts may be larger than the total area of the plurality of transistor parts.

  The semiconductor device includes a gate metal layer provided above the upper surface of the semiconductor substrate, an emitter electrode provided above the upper surface of the semiconductor substrate, and a first conductive type provided on the upper surface side of the semiconductor substrate in the transistor portion. An emitter region and a gate trench portion provided on the upper surface side of the semiconductor substrate in the transistor portion, electrically connected to the gate metal layer, and in contact with the emitter region, and provided on the upper surface side of the semiconductor substrate in the diode portion And an electrically connected emitter trench portion. The emitter trench portion may be arranged between the gate trench portions in a constant cycle also in the transistor portion.

  The semiconductor device may further include a dummy trench portion provided on the upper surface side of the semiconductor substrate, electrically connected to the gate metal layer, and not in contact with the emitter region.

  The boundary region may be a region having a device structure different from the device structure of the transistor portion and the device structure of the diode portion.

  The semiconductor device may further include an interlayer insulating film provided above the upper surface side of the semiconductor substrate, and a contact hole provided in the interlayer insulating film between the trench portions and in which the emitter electrode is embedded in the transistor portion and the diode portion. A contact hole may not be provided in the interlayer insulating film between the trench portions in the boundary region.

  The diode part may have a boundary area and a non-boundary area. The concentration of the cathode region in the border region of the diode part may be higher than the concentration of the cathode region in the non border region of the diode part.

  The semiconductor device may further include a lower surface lifetime killer provided opposite to the upper surface side of the semiconductor substrate. The diode part may have a boundary area and a non-boundary area. The concentration of the lower surface lifetime killer in the boundary region of the diode portion may be lower than the concentration of the lower surface lifetime killer in the non boundary region of the diode portion.

  The semiconductor device may further include an upper surface lifetime killer introduced at least to a non-boundary region of the diode portion on the upper surface side of the semiconductor substrate. The cathode region may be provided so as to extend to the transistor portion side with respect to the upper surface lifetime killer.

  The above summary of the invention does not enumerate all of the features of the present invention. In addition, a subcombination of these feature groups can also be an invention.

FIG. 1 is an example of a top view of a semiconductor device 100 according to a first embodiment. FIG. 6 is an example of a cross-sectional view of the semiconductor device 100 according to the first embodiment; FIG. 16 is an example of a top view of a semiconductor device 100 according to a second embodiment. FIG. 18 is an example of a cross-sectional view of the semiconductor device 100 according to the second embodiment taken along the line b-b ′. 7 is a modified example of the semiconductor device 100. FIG. It is a top view of semiconductor device 500 concerning a comparative example. FIG. 16 shows an example of an entire chip view of a semiconductor device 500. An example of the chip | tip whole view of the semiconductor device 100 is shown. It is a graph which shows current density distribution. 15 is a graph showing turn-off waveforms of the semiconductor device 100 and the semiconductor device 500. The conduction current density distribution of a full gate semiconductor device is shown. 17 shows a conduction current density distribution of a semiconductor device having an emitter trench portion E. 17 shows a conduction current density distribution of a semiconductor device having an emitter trench portion E. 17 shows a conduction current density distribution of a semiconductor device having an emitter trench portion E. 15 shows an example of the configuration of a semiconductor device 100 according to a third embodiment. 15 illustrates an exemplary configuration of a semiconductor device 100 according to a fourth embodiment. 15 illustrates an exemplary configuration of a semiconductor device 100 according to a fifth embodiment.

  Hereinafter, the present invention will be described through the embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Moreover, not all combinations of features described in the embodiments are essential to the solution of the invention.

  In the present specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as “upper”, and the other side is referred to as “lower”. Of the two main surfaces of the substrate, layer or other member, one surface is referred to as the upper surface, and the other surface is referred to as the lower surface. The directions of “upper”, “lower”, “front”, and “back” are not limited to the direction of gravity or the direction of attachment to a substrate or the like when mounting a semiconductor device.

  In this specification, technical matters may be described using orthogonal coordinate axes of the X axis, the Y axis, and the Z axis. In this specification, a plane parallel to the upper surface of the semiconductor substrate is taken as an XY plane, and the depth direction of the semiconductor substrate is taken as the Z axis. In the present specification, a case where the semiconductor substrate is viewed in the Z-axis direction is referred to as a plan view.

  In each embodiment, an example in which the first conductivity type is N-type and the second conductivity type is P-type is shown, but the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the conductivity types of the substrate, layer, region and the like in the respective embodiments have opposite polarities.

  In the present specification, in the layer or region in which n or p is listed, it is meant that electrons or holes are the majority carrier, respectively. Also, + and-attached to n and p mean that the doping concentration is higher and the doping concentration is lower than that of the layer or region to which it is not attached, respectively.

  FIG. 1A shows an example of the configuration of a semiconductor device 100 according to a first embodiment. The semiconductor device 100 of this example is a semiconductor chip provided with a transistor unit 70 and a diode unit 80. For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT: Reverse Conducting IGBT).

  The transistor portion 70 is a region having the emitter region 12 and the gate trench portion 40. The transistor portion 70 in this example is a region obtained by projecting the collector region provided on the lower surface side of the semiconductor substrate 10 on the upper surface of the semiconductor substrate 10, but is not limited thereto. The collector region has a second conductivity type. The collector region of this example is, for example, of P + type. The transistor unit 70 includes a transistor such as an IGBT.

  The diode unit 80 includes a diode such as a free wheel diode (FWD) provided adjacent to the transistor unit 70 on the upper surface of the semiconductor substrate 10. The diode section 80 in this example is an area obtained by projecting the cathode region 82 on the upper surface of the semiconductor substrate 10 and is an area other than the transistor section 70, but is not limited to this.

  In FIG. 1A, a region around the end of the chip, which is the edge side of the semiconductor device 100, is shown, and other regions are omitted. In this example, although the negative edge in the X-axis direction is described for convenience, the same applies to the other edges of the semiconductor device 100.

  The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride. The semiconductor substrate 10 of this example is a silicon substrate.

  The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter trench portion 60, a well region 11, an emitter region 12, a base region 14 and a contact region 15 on the upper surface of the semiconductor substrate 10. In addition, the semiconductor device 100 of the present example includes the emitter electrode 52 and the gate metal layer 50 provided above the upper surface of the semiconductor substrate 10.

  Emitter electrode 52 and gate metal layer 50 are formed of a material containing a metal. For example, at least a portion of the emitter electrode 52 may be formed of aluminum, aluminum-silicon alloy or aluminum-silicon-copper alloy. At least a partial region of the gate metal layer 50 may be formed of aluminum, aluminum-silicon alloy or aluminum-silicon-copper alloy. The emitter electrode 52 and the gate metal layer 50 may have a barrier metal formed of titanium, a titanium compound, or the like below the region formed of aluminum or the like. Emitter electrode 52 and gate metal layer 50 are provided separately from each other.

  Emitter electrode 52 and gate metal layer 50 are provided above semiconductor substrate 10 with an interlayer insulating film interposed therebetween. The interlayer insulating film is omitted in FIG. 1A. A contact hole 49, a contact hole 54 and a contact hole 56 are provided through the interlayer insulating film.

  The contact hole 49 connects the gate metal layer 50 and the gate runner 48. Inside the contact hole 49, a plug formed of tungsten or the like may be formed.

  The gate runner 48 connects the gate metal layer 50 and the gate trench portion 40 of the transistor portion 70. In one example, gate runner 48 is connected to the gate conductive portion in gate trench portion 40 and the dummy conductive portion in dummy trench portion 30 on the upper surface of semiconductor substrate 10. Gate runner 48 is not connected to the emitter conductive portion in emitter trench portion 60. For example, the gate runner 48 is formed of polysilicon doped with an impurity.

  The gate runner 48 in this example is provided from the lower side of the contact hole 49 to the tip of the gate trench portion 40. An interlayer insulating film such as an oxide film is provided between the gate runner 48 and the upper surface of the semiconductor substrate 10. The gate conductive portion is exposed on the top surface of the semiconductor substrate 10 at the tip of the gate trench portion 40. The gate trench portion 40 contacts the gate runner 48 at the exposed portion of the gate conductive portion.

  Contact hole 56 connects emitter electrode 52 and the emitter conductive portion in emitter trench portion 60. Inside the contact hole 56, a plug formed of tungsten or the like may be provided.

  The connection portion 25 is provided between the emitter electrode 52 and the emitter conductive portion. The connection portion 25 is a conductive material such as polysilicon doped with an impurity. The connection portion 25 is provided above the upper surface of the semiconductor substrate 10 via an interlayer insulating film such as an oxide film.

  The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the Y-axis direction). The gate trench portion 40 in this example is two extending portions 41 extending in parallel with the upper surface of the semiconductor substrate 10 and extending along an extending direction (in this example, the X-axis direction) perpendicular to the arrangement direction It may have a connecting portion 43 connecting 41. The gate trench portion 40 in this example is electrically connected to the gate metal layer 50. Further, the gate trench portion 40 is in contact with the emitter region 12.

  The connecting portion 43 is preferably provided at least in part in a curved shape. By connecting the end portions of the two extension portions 41 of the gate trench portion 40, the electric field concentration at the end portions of the extension portion 41 can be alleviated. At the connection portion 43 of the gate trench portion 40, the gate runner 48 may be connected to the gate conductive portion.

  Similar to the gate trench portion 40, the dummy trench portions 30 are arrayed at predetermined intervals along a predetermined array direction (in the present example, the Y-axis direction). The dummy trench portion 30 in the present example may have a U-shape on the upper surface of the semiconductor substrate 10 as in the gate trench portion 40. That is, the dummy trench portion 30 may have two extending portions 31 extending in the extending direction and a connecting portion 33 connecting the two extending portions 31. The dummy trench portion 30 is electrically connected to the gate metal layer 50. However, the dummy trench portion 30 is different from the gate trench portion 40 in that the dummy trench portion 30 is not in contact with the emitter region 12. For example, the semiconductor device 100 can adjust the gate-emitter capacitance by adjusting the ratio between the gate trench portion 40 and the dummy trench portion 30.

  The emitter trench portions 60 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the Y-axis direction), similarly to the gate trench portions 40. The emitter trench portion 60 in the present example may have a U-shape on the top surface of the semiconductor substrate 10 as with the gate trench portion 40. That is, the emitter trench portion 60 may have two extension portions 61 extending in the extension direction and a connection portion 63 connecting the two extension portions 61. Emitter trench portion 60 is electrically connected to emitter electrode 52. For example, by providing the emitter trench portion 60 in the diode portion 80, the potential around the emitter trench portion 60 is less likely to swing.

  Emitter electrode 52 is provided above gate trench portion 40, dummy trench portion 30, emitter trench portion 60, well region 11, emitter region 12, base region 14 and contact region 15.

  The well region 11 is a region of the second conductivity type provided on the upper surface side of the semiconductor substrate 10 than the drift region 18 described later. Well region 11 is, for example, of P + type. Well region 11 is provided in a predetermined range from the end of the active region on the side where gate metal layer 50 is provided. The diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40, the dummy trench portion 30 and the emitter trench portion 60. A partial region of gate trench portion 40, dummy trench portion 30 and emitter trench portion 60 on the side of gate metal layer 50 is provided in well region 11. The bottoms of the ends in the extending direction of the gate trench portion 40, the dummy trench portion 30, and the emitter trench portion 60 may be covered with the well region 11.

  Contact hole 54 is provided above each of emitter region 12 and contact region 15 in transistor portion 70. Further, the contact hole 54 is provided above the base region 14 in the diode section 80. Contact hole 54 is provided above contact region 15 in boundary region 81. Thus, one or more contact holes 54 are provided in the interlayer insulating film. One or more contact holes 54 may be provided extending in the extending direction. In the first embodiment, the contact region 15 is provided on the upper surface of the boundary region 81, but the base region 14 may be provided on the upper surface of the boundary region 81 as in the diode section 80. This applies not only to the first embodiment but also to the second to fifth embodiments described later.

  The boundary region 81 is provided in a region where the transistor portion 70 and the diode portion 80 are adjacent to each other. In the present specification, the boundary region 81 is provided in the region where the transistor portion 70 and the diode portion 80 are adjacent to each other, and is a region for preventing mutual interference. Specifically, the boundary region 81 has a device structure different from the device structure of the transistor unit 70 (so-called MOS structure) and the device structure of a diode such as a free wheel diode of the diode unit 80. Therefore, boundary region 81 has a device structure different from the device structure of transistor portion 70 and the device structure of diode portion 80, and the device structure and diode portion in which the channel of transistor portion 70 is formed in the arrangement direction of the trench portions. It may be a region located between the 80 diode device structure.

  The device structure of the transistor unit 70 and the device structure of the boundary region 81 different from the device structure of the diode unit 80 are, for example, the emitter region 12, the contact region 15, the storage region 16, the trench portion, and the depth of the trench portion, which will be described later. It refers to a region having a device structure different from the transistor unit 70 and the diode unit 80 in at least one of the lifetime killer, the buffer region 20, the cathode region 82, and the collector region 22. As a difference in structure in terms of the trench portion, for example, it is offset from any periodic structure (repeated structure) of the trench portion of the transistor portion 70 and the trench portion of the diode portion 80. As in this example, the device structure of the transistor unit 70 and the device structure of the diode unit 80 are different from the device structure of the diode unit 80 only in a single range (for example, between single trenches) of the transistor unit 70 and the diode unit 80. Even if the periodic structure (repetitive structure) of the transistor portion 70 or the diode portion 80 is noted, the area may be different from the pattern.

  The boundary region 81 may be 10 μm to 100 μm, and may be 50 μm to 100 μm. The base point of the length of the boundary region 81 can be, for example, the gate trench portion 40 in which the channel of the transistor portion 70 is formed, and a region of 10 μm to 100 μm from the gate trench portion 40 toward the diode portion 80 May be used as the boundary area 81.

  The thickness of the semiconductor substrate 10 may be determined in accordance with the withstand voltage of the semiconductor device 100, and the width in the Y-axis direction of the boundary region 81 may be determined in accordance with the thickness of the semiconductor substrate 10. Specifically, the width of the boundary region 81 in the Y-axis direction may be increased as the withstand voltage of the semiconductor device 100 is increased. Further, the width in the Y-axis direction of boundary region 81 may be determined according to the flow of carriers and the amount of carriers in semiconductor substrate 10. Specifically, the width of the boundary region 81 in the Y-axis direction may be increased as the amount of carriers flowing per unit time increases between the transistor unit 70 and the diode unit 80. Further, the width of the boundary region 81 in the Y-axis direction may be increased as the amount of carriers in the semiconductor substrate 10 is increased.

  Boundary region 81 may have a plurality of mesas. More preferably, boundary region 81 may have four or more and ten or less mesas. The base point of the mesa portion of the boundary region 81 can be, for example, the gate trench portion 40 in which the channel of the transistor portion 70 is formed, and four or more and ten or less from the gate trench portion 40 toward the diode portion 80. The mesa portion may be used as the boundary area 81. The width in the Y-axis direction of one mesa may be about 10 μm. The length of four mesa portions sandwiching three trench portions in the Y axis direction may be 50 μm, and the length of five mesa portions sandwiching four trench portions in the Y axis direction May be 50 μm. In addition, the length of eight mesa portions sandwiching seven trench portions in the Y-axis direction may be 100 μm, and ten mesa portions sandwiching nine trench portions in the Y-axis direction. The length may be 100 μm.

  By providing the boundary region 81 having a structure different from that of the transistor portion 70 or the non-boundary region 83 of the diode portion 80, interference of current with the transistor portion 70 or the diode portion 80 can be reduced. In one example, the larger the width of the boundary region 81 in the Y-axis direction, the more effectively the current interference can be reduced.

  In the first embodiment, the boundary area 81 is provided in the diode section 80. Further, in the first embodiment, the boundary region 81 is a region not having the emitter region 12 between the gate trench portion 40 and the emitter trench portion 60. Since the boundary region 81 does not have the emitter region 12, the semiconductor device 100 is less likely to latch up. Boundary region 81 includes a region in which gate trench portions 40 of transistor portion 70 are arranged in a fixed cycle in the Y-axis direction, and a region in which emitter trench portions 60 in diode unit 80 are arranged in a fixed cycle in the Y-axis direction. Refers to the area between

  The non-boundary region 83 is a region other than the boundary region 81 in the transistor portion 70 or the diode portion 80. In the first embodiment, since the boundary area 81 is provided in the diode section 80, the area other than the boundary area 81 of the diode section 80 is referred to as a non-boundary area 83. In the first embodiment, the non-boundary region 83 is a region having the emitter trench portion 60 in a region different from the boundary region 81. As described above, the non-boundary region 83 includes a region in which the emitter trench portion 60 is arranged at a constant cycle among the regions where the cathode region 82 is projected on the upper surface of the semiconductor substrate 10. In addition, since the boundary region 81 is not provided in the transistor portion 70, in this case, the entire transistor portion 70 is a non-boundary region.

  Dummy trench portion 30 is provided in boundary region 81. However, the dummy trench portion 30 may be provided also in the non-boundary region 83. The dummy trench portion 30 may be provided only in the non-boundary region 83. Further, in the boundary region 81, a gate trench portion 40 or an emitter trench portion 60 may be provided. The half or more or all of the trench portions located in the range of the boundary region 81 may be the dummy trench portion 30.

  The first mesa portion 91, the second mesa portion 92, and the third mesa portion 93 are mesa portions provided adjacent to the respective trench portions in the Y-axis direction in a plane parallel to the upper surface of the semiconductor substrate 10. . The mesa portion may be a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion from the top surface of the semiconductor substrate 10 to the deepest bottom of each trench portion. The extension portion of each trench portion may be one trench portion. That is, the region between the two extending portions may be a mesa portion.

  The first mesa portion 91 is provided adjacent to at least one of the gate trench portion 40 and the emitter trench portion 60 in the transistor portion 70. In addition, the first mesa portion 91 of this example is provided adjacent to the transistor portion 70 also in the boundary region 81. The first mesa portion 91 has a well region 11, an emitter region 12, a base region 14, and a contact region 15 on the upper surface of the semiconductor substrate 10. In the first mesa portion 91, the emitter regions 12 and the contact regions 15 are alternately provided in the extending direction.

  The second mesa 92 is a mesa provided in the boundary area 81. The second mesa portion 92 has a well region 11, a base region 14 and a contact region 15 on the top surface of the semiconductor substrate 10. In the first embodiment, the second mesa portion 92 does not have the emitter region 12 but may have the emitter region 12. Further, in the first embodiment, the second mesa portion 92 has the contact region 15 but may not have the contact region 15.

  The third mesa portion 93 is provided in the region between the adjacent emitter trench portions 60 in the diode portion 80. The third mesa portion 93 has a well region 11 and a base region 14 on the upper surface of the semiconductor substrate 10.

  The base region 14 is a region of the second conductivity type provided on the upper surface side of the semiconductor substrate 10. The base region 14 is P-type as an example. The base regions 14 may be provided on both ends of the first mesa portion 91 and the second mesa portion 92 in the X-axis direction on the upper surface of the semiconductor substrate 10. However, as shown in FIG. 1B, the base region 14 is introduced substantially in the entire surface of the active region in the cross section. Note that FIG. 1A shows only one end of the base region 14 in the X-axis direction.

  Emitter region 12 is provided on the top surface of first mesa portion 91 in contact with gate trench portion 40. Emitter region 12 may be provided in the Y-axis direction from one of the two trench portions extending in the X-axis direction across first mesa portion 91 to the other. Emitter region 12 is also provided below contact hole 54. The emitter region 12 of this example is of the first conductivity type. Emitter region 12 is N + type as an example.

  The contact region 15 is a region of the second conductivity type having a doping concentration higher than that of the base region 14. The contact region 15 of this example is, for example, of P + type. The contact region 15 in the present example is provided on the top surface of the first mesa portion 91. The contact region 15 may be provided in the Y-axis direction from one of the two trench portions extending in the X-axis direction across the first mesa portion 91 to the other. Contact region 15 may or may not be in contact with gate trench portion 40. Contact region 15 may or may not be in contact with emitter trench portion 60. The contact region 15 in this example is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also provided below the contact hole 54.

  The contact region 15 may also be provided on the top surface of the second mesa 92. The area of the contact region 15 provided on the upper surface of one second mesa 92 is larger than the area of the contact region 15 provided on the upper surface of one first mesa 91. The contact region 15 on the upper surface of the second mesa 92 may be provided in the entire region sandwiched by the base regions 14 provided at both ends in the X-axis direction of the second mesa 92.

  The cathode region 82 is a region of the first conductivity type provided on the lower surface side of the semiconductor substrate 10 in the diode unit 80. The cathode region 82 in this example is, for example, of N + type. The area where the cathode area 82 is provided in a plan view is indicated by an alternate long and short dash line.

  FIG. 1B is a view showing an example of an aa ′ cross section in FIG. 1A. The aa ′ cross section is a YZ plane passing through the emitter region 12, the base region 14 and the contact region 15 in the transistor portion 70 and the diode portion 80. The semiconductor device 100 of this example has the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24 in the aa 'cross section. Emitter electrode 52 is provided on upper surface 21 of semiconductor substrate 10 and the upper surface of interlayer insulating film 38.

  The drift region 18 is a region of the first conductivity type provided in the semiconductor substrate 10. The drift region 18 in this example is, for example, N-type. Drift region 18 may be a region remaining in semiconductor substrate 10 without forming another doping region. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

  The buffer region 20 is a region of the first conductivity type provided below the drift region 18. The buffer area 20 of this example is N-type as an example. The doping concentration of buffer region 20 is higher than the doping concentration of drift region 18. Buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower surface side of base region 14 from reaching collector region 22 of the second conductivity type and cathode region 82 of the first conductivity type.

  The collector region 22 is a region of the second conductivity type provided on the lower surface side of the semiconductor substrate 10 in the transistor unit 70. Collector region 22 is, for example, of P + type. The collector region 22 of this example is provided below the buffer region 20.

  The cathode region 82 is provided below the buffer region 20 in the diode section 80. The boundary R is a boundary between the collector region 22 and the cathode region 82. The boundary R may or may not coincide with the boundary between the transistor portion 70 and the diode portion 80.

  The collector electrode 24 is formed on the lower surface 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as metal.

  The accumulation region 16 is a region of the first conductivity type provided above the drift region 18 in the first mesa portion 91 and the second mesa portion 92. The storage area 16 of this example is N-type as an example. Storage region 16 is provided in contact with gate trench portion 40. The storage region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of storage region 16 is higher than the doping concentration of drift region 18. By providing the storage region 16, the carrier injection promoting effect (IE effect) can be enhanced, and the on voltage of the transistor portion 70 can be reduced. The accumulation region 16 may be provided in the third mesa portion 93.

  The base region 14 is a region of the second conductivity type provided above the accumulation region 16 in the first mesa portion 91, the second mesa portion 92 and the third mesa portion 93. Base region 14 is provided in contact with gate trench portion 40. The base region 14 of the third mesa 93 is a so-called anode region.

  Emitter region 12 is provided between base region 14 and upper surface 21 in first mesa portion 91. Emitter region 12 is provided in contact with gate trench portion 40. The doping concentration of the emitter region 12 is higher than the doping concentration of the drift region 18. An example of the dopant of the emitter region 12 is arsenic (As). Emitter region 12 may not be provided in second mesa portion 92, and may not be provided.

  The contact region 15 is provided above the accumulation region 16 in the first mesa portion 91 and the second mesa portion 92. The contact region 15 is provided in contact with the gate trench portion 40 and the dummy trench portion 30 in the first mesa portion 91 and the second mesa portion 92.

  One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the upper surface 21. Each trench portion is provided from the upper surface 21 to the drift region 18. In the region where at least one of the emitter region 12, the base region 14, the contact region 15 and the storage region 16 is provided, each trench also penetrates these regions to reach the drift region 18. The fact that the trench portion penetrates the doping region is not limited to the one manufactured in the order of forming the doping region and then forming the trench portion. After forming the trench portion, those in which the doping region is formed between the trench portions are also included in those in which the trench portion penetrates the doping region.

  The gate trench portion 40 has a gate trench formed on the upper surface 21, a gate insulating film 42 and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate insulating film 42 inside the gate trench. The gate insulating film 42 insulates the gate conductive portion 44 and the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. Gate trench portion 40 is covered with interlayer insulating film 38 on upper surface 21.

  The gate conductive portion 44 includes a region facing the adjacent base region 14 on the first mesa portion 91 side with the gate insulating film 42 in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel, which is an inversion layer of electrons, is formed in the surface layer of the interface in contact with the gate trench in the base region 14.

  The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32 and a dummy conductive portion 34 formed on the upper surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 and the semiconductor substrate 10. The dummy trench portion 30 is covered with the interlayer insulating film 38 on the upper surface 21.

  Emitter trench portion 60 may have the same structure as gate trench portion 40 and dummy trench portion 30. Emitter trench portion 60 has an emitter trench formed on the upper surface 21 side, an emitter insulating film 62 and an emitter conductive portion 64. Emitter insulating film 62 is formed to cover the inner wall of the emitter trench. Emitter conductive portion 64 is formed in the inside of the emitter trench, and is formed inward of emitter insulating film 62. Emitter insulating film 62 insulates emitter conductive portion 64 from semiconductor substrate 10. Emitter trench portion 60 is covered with interlayer insulating film 38 on upper surface 21.

  The interlayer insulating film 38 is provided above the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is provided with one or more contact holes 54 for electrically connecting the emitter electrode 52 and the semiconductor substrate 10. Similarly, other contact holes 49 and contact holes 54 may be provided through the interlayer insulating film 38. An emitter electrode 52 is provided above the interlayer insulating film 38.

The semiconductor device 100 of this example adjusts the gate-emitter capacitance by adjusting the ratio of the gate trench 40 and the dummy trench 30. In the semiconductor device 100, the gate-emitter capacitance can be increased by increasing the ratio of the dummy trench portion 30, and the gate-emitter capacitance can be reduced by decreasing the ratio of the dummy trench portion 30. For example, assuming that the number of gate trench portions 40 is G and the number of dummy trench portions 30 is D, the following equation holds.
0.01 <D / (D + G) <0.2

  The number of gate trench portions 40 refers to the number of extension portions 41. That is, even when one gate trench portion 40 is configured by connecting the plurality of extension portions 41 by the connection portion 43, substantially the number of the plurality of extension portions 41 is the gate trench It becomes the number of parts 40. Therefore, the number of gate trench portions 40 matches the number of gate trench portions 40 in the aa ′ cross section as shown in FIG. 1B.

  Further, the number of dummy trench portions 30 is also substantially the same even when one dummy trench portion 30 is configured by connecting the plurality of extension portions 31 by the connection portion 33, The number of the plurality of extended portions 31 is the number of the dummy trench portions 30. Therefore, the number of dummy trench portions 30 matches the number of buffer regions 20 in the aa ′ cross section as shown in FIG. 1B.

  FIG. 2A is an example of a top view of the semiconductor device 100 according to the second embodiment. FIG. 2B is a view showing an example of the bb ′ cross section in FIG. 2A. The semiconductor device 100 according to the second embodiment is different from the semiconductor device 100 according to the first embodiment in that the boundary region 81 is provided in the transistor section 70. In the semiconductor device 100 according to the second embodiment, the boundary area 81 is provided in the transistor section 70, so the area other than the boundary area 81 of the transistor section 70 is referred to as a non-boundary area 83. In addition, since the boundary area 81 is not provided in the diode part 80, the whole diode part 80 is a non-boundary area in this case.

  In the second embodiment, the non-boundary region 83 is a region having the gate trench portion 40 and the emitter trench portion 60 in a region different from the boundary region 81. As described above, the non-boundary region 83 includes a region in which the gate trench portion 40 and the emitter trench portion 60 are arranged at a constant cycle among the regions where the collector region 22 is projected onto the upper surface of the semiconductor substrate 10.

  Dummy trench portion 30 is provided in boundary region 81. However, the dummy trench portion 30 may be provided also in the non-boundary region 83. The dummy trench portion 30 may be provided only in the non-boundary region 83. Further, in the boundary region 81, a gate trench portion 40 or an emitter trench portion 60 may be provided.

  As described above, providing the boundary region 81 in the transistor portion 70 means that the cathode region 82 becomes relatively short and the collector region 22 becomes relatively long. Therefore, electrons emitted from the emitter region 12 can easily flow into the collector region 22, and the on voltage can be lowered.

  The boundary region 81 may be provided across the transistor portion 70 and the diode portion 80. In this case, non-boundary regions 83 other than the boundary region 81 are provided in each of the transistor portion 70 and the diode portion 80.

  FIG. 3 is a modification of the semiconductor device 100. As shown in FIG. In the semiconductor device 100 of this example, in the boundary region 81, the contact hole 54 is not provided above at least a part of the second mesa portion 92 adjacent to the dummy trench portion 30. In the semiconductor device 100 of the present example, in the boundary region 81, the contact hole 54 is not provided above all the second mesa portions 92 adjacent to the dummy trench portion 30. That is, the second mesa portion 92 adjacent to the dummy trench portion 30 is not electrically connected to the emitter electrode 52. Note that not providing the contact hole 54 in part or all of the mesa portion of the boundary region 81 may be applied to the first and second embodiments and the third to fifth embodiments described later.

  FIG. 4 is a top view of the semiconductor device 500 according to the comparative example. The semiconductor device 500 of this example is different from the semiconductor device 100 of the first embodiment in that the dummy trench portion 30 is not provided. The semiconductor device 500 includes a transistor portion 570 and a diode portion 580.

  The semiconductor device 500 includes an emitter trench portion 60 on the side of the diode portion 580 with the transistor portion 570. That is, the semiconductor device 500 of this example does not have the dummy trench portion 30 in the boundary region 81. That is, since the trench portion other than the gate trench portion 40 is not connected to the gate metal layer 50, the capacitance between the gate and the emitter is smaller than that of the semiconductor device 100 according to the first embodiment.

  Here, when noise is generated in the semiconductor device 500 while the semiconductor device 500 is in the FWD operation, a potential difference higher than the threshold voltage Vth may be generated, and the transistor portion 570 may be erroneously turned on. As the gate-emitter capacitance is smaller, the influence of noise on the semiconductor device 500 is increased. If the transistor portion 570 is erroneously turned on, a short circuit current may flow during reverse recovery, causing a short circuit mode, and the semiconductor device 500 may be broken.

  On the other hand, since the semiconductor device 100 has the dummy trench portion 30, the capacitance between the gate and the emitter is increased. As a result, even if noise is generated in the semiconductor device 100, it is difficult for the transistor portion 70 to turn on erroneously. Thus, providing the dummy trench portion 30 is equivalent to providing the noise cut capacitor. Thereby, the influence of noise on the semiconductor device 100 is reduced.

  FIG. 5 shows an example of an entire chip view of a semiconductor device 500 according to a comparative example. The semiconductor device 500 of this example includes a plurality of transistor units 570 and a plurality of diode units 580.

  In the semiconductor device 500 of this example, the width Wd of the diode unit 580 in the Y-axis direction is smaller than the width Wt of the transistor unit 570 in the Y-axis direction. Further, in this example, the width in the X-axis direction of the transistor portion 570 and the width in the X-axis direction of the diode portion 580 are equal. The total area of the plurality of diode units 580 is smaller than the total area of the plurality of transistor units 570.

  In the semiconductor device 500, the current on the side of the transistor portion 570 may be gradually concentrated on the side of the diode portion 580 at the time of switching. In this case, the semiconductor device 500 may generate heat locally and be destroyed. As described above, the current flows uniformly at the time of turn-off, but the current may be concentrated by trying to flow to the cathode region with time. In the semiconductor device 500, since the width Wd in the Y-axis direction of the diode portion 580 is smaller than the width Wt in the Y-axis direction of the transistor portion 570, heat generation due to current concentration is remarkable. In particular, in the case of switching at a high current density, the semiconductor device 500 may be broken.

  FIG. 6 shows an example of the entire chip of the semiconductor device 100. The semiconductor device 100 of this example includes a plurality of transistor units 70 and a plurality of diode units 80. The semiconductor device 100 includes an edge termination region 102 and an outer region 104 outside the active region where the transistor portion 70 and the diode portion 80 are provided.

  The edge termination region 102 relieves the concentration of the electric field on the upper surface side of the semiconductor substrate 10. For example, the edge termination region 102 has a guard ring, a field plate, a resurf and a combination of these.

  The outer region 104 is provided adjacent to the transistor unit 70 and the diode unit 80. For example, the outer region 104 includes a gate pad, a sense unit, and a temperature detection unit.

  The semiconductor device 100 of this example includes fifteen transistor units 70 and twelve diode units 80. In the semiconductor device 100 of this example, the width Wd of the diode unit 80 in the Y-axis direction is equal to or greater than the width Wt of the transistor unit 70 in the Y-axis direction, and preferably larger than the width Wt in the Y-axis direction. For example, the width Wd of the diode unit 80 in the Y-axis direction may be 500 μm or more, 1000 μm or more, or 1500 μm or more. Further, in this example, the width in the X-axis direction of the transistor section 70 and the width in the X-axis direction of the diode section 80 are equal. In the semiconductor device 100 of this example, the total area of the diode unit 80 is equal to or larger than the total area of the transistor unit 70, and preferably larger than the total area of the transistor unit 70.

  In the semiconductor device 100 of this example, the width Wd of the diode unit 80 in the Y-axis direction is equal to or greater than the width Wt of the transistor unit 70 in the Y-axis direction. The current flow can also reduce the concentration of current. Therefore, in the semiconductor device 100 of this example, the concentration of the current is alleviated, so the semiconductor device 100 is less likely to be destroyed.

  The total area of the diode unit 80 may be larger than 1.2 times, larger than 1.5 times, or larger than 2.0 times the total area of the transistor unit 70. The ratio of the total area of the transistor unit 70 to the total area of the diode unit 80 is set in view of the trade-off between the conduction loss of the semiconductor device 100 and the current concentration. That is, the conduction loss tends to be reduced as the total area of the transistor section 70 becomes larger. On the other hand, the current concentration tends to be alleviated as the total area of the diode section 80 increases.

  When semiconductor device 100 has diode unit 80 having a total area equal to or larger than the total area of transistor unit 70, the capacitance between the gate and the emitter is smaller than in the case where the total area of diode unit 80 is smaller than the total area of transistor unit 70. . However, the semiconductor device 100 of this example can suppress the reduction of the gate-emitter capacitance by providing the dummy trench portion 30 in the boundary region 81.

  In the semiconductor device 100, when the size of the semiconductor chip is fixed, the total area of the diode unit 80 is equal to or larger than the total area of the transistor unit 70, and the number of the transistor unit 70 and the diode unit 80 is reduced. Good. As a result, the area of the interface between the transistor unit 70 and the diode unit 80, that is, the boundary region 81 for preventing mutual interference between the transistor unit 70 and the diode unit 80 is reduced, so that the loss of current is reduced.

  The semiconductor device 100 of this example includes more transistor units 70 than the diode units 80 in the Y-axis direction. Thus, the transistor sections 70 are disposed at both ends in the Y-axis direction. By providing the transistor sections 70 at both ends in the Y-axis direction, current concentration in the diode section 80 is less likely to occur.

  For example, the semiconductor device 100 in this example includes five transistor units 70 and four diode units 80 in the Y-axis direction. However, the number of transistor parts 70 and diode parts 80 in the Y-axis direction is not limited to this. For example, the number of transistor parts 70 and diode parts 80 may be four and three, or three and two, or two and one. In addition, the number of transistor portions 70 and diode portions 80 may be six and five, seven and six, or eight and seven. The number of transistor portions 70 and the number of diode portions 80 may be the same in the Y-axis direction.

  The semiconductor device 100 further includes three rows of the transistor portion 70 and the diode portion 80 in the X-axis direction. However, the number of rows of the transistor unit 70 and the diode unit 80 in the X-axis direction is not limited to this. For example, the number of rows of the transistor portion 70 and the diode portion 80 in the X-axis direction may be one row, two rows, four rows, five rows, or more. It may be.

FIG. 7A is a graph showing a current density distribution. The vertical axis indicates current density [A / cm ² ], and the horizontal axis indicates an arbitrary position in the Y-axis direction.

  The distribution D1 indicates the current density distribution when the semiconductor device 100 is used. The semiconductor device 100 of this example shows the case where the ratio of the total area of the transistor section 70 to the total area of the diode section 80 is 20:40. That is, the total area of the diode section 80 corresponds to about 66% of the total area of the transistor section 70 and the diode section 80.

  The distribution D2 indicates the current density distribution when the semiconductor device 100 is used. The semiconductor device 100 of this example shows the case where the ratio of the total area of the transistor section 70 to the total area of the diode section 80 is 20:20. That is, the total area of the diode unit 80 corresponds to 50% of the total area of the transistor unit 70 and the diode unit 80.

  The distribution D3 shows the current density distribution when the semiconductor device 500 is used. The semiconductor device 500 of this example shows the case where the ratio of the total area of the transistor portion 570 to the total area of the diode portion 580 is 20: 6. That is, the total area of the diode portion 580 corresponds to about 23% of the total area of the transistor portion 570 and the diode portion 580.

  When the distributions D1 to D3 are compared, the maximum value of the current density decreases as the ratio of the diode section 80 increases. That is, the semiconductor device 100 can reduce the maximum value of the current density by making the total area of the diode unit 80 equal to or larger than the total area of the transistor unit 70.

FIG. 7B is a graph showing turn-off waveforms of the semiconductor device 100 and the semiconductor device 500. This graph shows temporal changes in collector current Ic [A / cm ² ] and collector-emitter voltage Vce. The collector current Ic of the semiconductor device 100 is larger than the collector current Ic of the semiconductor device 500. That is, the semiconductor device 100 can realize switching with a higher current density than the semiconductor device 500 by making the width of the diode unit 80 larger than the width of the transistor unit 70.

8A to 8D are diagrams for comparing the conduction current density distribution when the ratio of the gate trench portion G to the emitter trench portion E is changed. The ordinate represents the conduction current density distribution [A / cm ² ], and the abscissa represents the position in the Y-axis direction near the transistor portion and the diode portion. The gate trench portion G is a trench portion electrically connected to the gate metal layer 50 and provided in contact with the emitter region 12. The emitter trench portion E is a trench portion electrically connected to the emitter electrode 52.

  FIG. 8A shows the conduction current density distribution of a full gate semiconductor device. In the semiconductor device of this example, all the trench portions are gate trench portions G. That is, in the semiconductor device of this example, all the trench portions are electrically connected to the gate metal layer 50.

  FIG. 8B shows the conduction current density distribution of the semiconductor device having the emitter trench portion E. In the semiconductor device of this example, the gate trench portion G and the emitter trench portion E are provided at a ratio of 2: 1. That is, in the semiconductor device of this example, the number of gate trench portions G is larger than the number of emitter trench portions E.

  FIG. 8C shows the conduction current density distribution of the semiconductor device having the emitter trench portion E. In the semiconductor device 500 of this example, the gate trench portion G and the emitter trench portion E are provided at a ratio of 1: 1. That is, in the semiconductor device of this example, the number of gate trench portions G is equal to the number of emitter trench portions E.

  FIG. 8D shows the conduction current density distribution of the semiconductor device having the emitter trench portion E. In the semiconductor device 500 of this example, the gate trench portion G and the emitter trench portion E are provided at a ratio of 1: 2. That is, in the semiconductor device of this example, the number of gate trench portions G is smaller than the number of emitter trench portions E.

  Referring to the conduction current density distributions of FIGS. 8A to 8D, the conduction current density distribution tends to be broadened by increasing the ratio of the emitter trench E to the gate trench G. For example, the conduction current density distribution of FIG. 8A tends to localize to a specific region as compared to other examples. Further, by increasing the ratio of the emitter trench portion E, the channel region is reduced, so the maximum value of the conduction current tends to increase.

  Here, an example of a method for designing the semiconductor device 100 in which the influence of noise is reduced while suppressing the current concentration will be described. In a full gate semiconductor device, all the trench portions are electrically connected to the gate metal layer 50, and the potential around the trench portions may be unstable. Therefore, the semiconductor device preferably has both the gate trench portion G and the emitter trench portion E. However, as shown in FIGS. 8A to 8D, when the ratio of the emitter trench portion E to the gate trench portion G is increased, the maximum value of the conduction current density distribution tends to increase.

  The breakdown of the semiconductor device 100 can be suppressed by increasing the ratio of the total area of the diode section 80 to the total area of the transistor section 70 in order to suppress the maximum value of the conduction current density distribution. In particular, in the first embodiment, the boundary area 81 is provided in the diode section 80. By providing the boundary region 81 in the diode section 80, the cathode region 82 becomes relatively long and the collector region 22 becomes short. Therefore, electrons emitted from the emitter region 12 can easily flow into the cathode region 82, and the maximum value of the current density can be effectively reduced.

  On the other hand, when the ratio of the total area of the diode unit 80 to the total area of the transistor unit 70 is increased, the gate-emitter capacitance is reduced. Therefore, in the semiconductor device 100, by providing the dummy trench portion 30 in the boundary region 81, it is possible to secure the gate-emitter capacitance while relaxing the concentration of current by the increase of the diode portion 80. As a result, the semiconductor device 100 less affected by noise can be realized while suppressing destruction of the element due to current concentration.

  The dummy trench portion 30 described above extends not only in the boundary region 81 where the transistor portion 70 and the diode portion 80 are adjacent but also in the X axis direction toward the edge termination region 102 side of the transistor portion 70 adjacent to the edge termination region 102. It may be provided to That is, the dummy trench portion 30 which is not in contact with the emitter region 12 may be provided on the edge termination region 102 side of the transistor portion 70 adjacent to the edge termination region 102. The edge termination region 102 side of the transistor portion 70 in which the dummy trench portion 30 is provided is illustrated by a broken line as an edge adjacent region 84. The edge adjacent region 84 is a region adjacent to the edge termination region 102 on the positive side or the negative side of the transistor section 70 in the Y-axis direction. As a result, it is possible to secure the capacitance between the gate and the emitter, to form an ineffective region not functioning as a transistor on the edge termination region 102 side of the transistor section 70, and to suppress concentration of carriers. Therefore, the number of dummy trench portions 30 inserted in edge adjacent region 84 may be larger than the number of dummy trench portions 30 inserted in boundary region 81. Also, the dummy trench portion 30 may be provided only in the edge adjacent region 84. In providing the dummy trench portion 30 in the edge adjacent region 84, the width Wt in the Y-axis direction of the transistor portion 70 and the width Wd in the Y-axis direction of the diode portion 80 are not limited.

  FIG. 9 shows an example of the configuration of the semiconductor device 100 according to the third embodiment. The semiconductor device 100 according to this embodiment is different from the semiconductor device 100 according to the first embodiment in that the upper surface lifetime killer 95 and the lower surface lifetime killer 96 are provided.

  The upper surface lifetime killer 95 and the lower surface lifetime killer 96 are used to adjust the lifetime of the carrier. The upper surface lifetime killer 95 and the lower surface lifetime killer 96 are provided by implanting ions from the upper surface side or the lower surface side of the semiconductor substrate 10. For example, the upper surface lifetime killer 95 and the lower surface lifetime killer 96 are formed by injection of helium.

  The upper surface lifetime killer 95 is provided on the upper surface side of the semiconductor substrate 10. For example, the upper surface lifetime killer 95 of the third embodiment is provided in the diode unit 80. The upper surface lifetime killer 95 in this example is provided so as to extend from the non-boundary region 83 to at least a part of the boundary region 81. The top surface lifetime killer 95 can reduce the tail current and reduce the reverse recovery loss Err by reducing the carrier lifetime on the anode region side of the diode section 80.

  The upper surface lifetime killer 95 may or may not be provided in the transistor unit 70. That is, although the upper surface lifetime killer 95 of this example is provided extending from the non-boundary region 83 to the middle of the boundary region 81, it may be provided extending to the boundary R, or the boundary R may be exceeded. It may be extended to the transistor portion 70. Further, in this example, the area obtained by projecting the collector area provided on the lower surface side of the semiconductor substrate 10 on the upper surface of the semiconductor substrate 10 is an area obtained by projecting the transistor section 70 and the cathode area 82 on the upper surface of the semiconductor substrate 10 The region other than the portion 70 is a diode portion 80. However, the region where the upper surface lifetime killer 95 is not provided may be the transistor portion 70, and the region where the upper surface lifetime killer 95 is provided may be the diode portion 80.

  The lower surface lifetime killer 96 is provided on the lower surface side of the semiconductor substrate 10. The lower surface lifetime killer 96 of this example is provided in both the transistor unit 70 and the diode unit 80. The concentration of the lower surface lifetime killer 96 may be lower on the transistor unit 70 side than on the diode unit 80 side. For example, the concentration of the lower surface lifetime killer 96 in the boundary region 81 of the diode unit 80 is lower than the concentration of the lower surface lifetime killer 96 in the non-boundary region 83 of the diode unit 80. As a result, the current easily flows to the cathode region 82, and the concentration of the current in the transistor portion 70 is easily alleviated.

  The cathode region 82 is provided to extend closer to the transistor portion 70 than the upper surface lifetime killer 95. As a result, the current easily flows to the cathode region 82, and the concentration of the current in the transistor portion 70 is easily alleviated.

  Further, the concentration of the cathode region 82 may be higher on the transistor section 70 side than on the diode section 80 side. For example, the concentration of the cathode region 82 in the boundary region 81 of the diode unit 80 is higher than the concentration of the cathode region 82 in the non-boundary region 83 of the diode unit 80. As a result, the current can more easily flow to the cathode region 82, and the concentration of the current in the transistor portion 70 can be easily alleviated.

  FIG. 10 shows an example of the configuration of the semiconductor device 100 according to the fourth embodiment. The semiconductor device 100 of this example differs from the semiconductor device 100 according to the first embodiment in the structure of the boundary region 81.

  The accumulation region 16 is provided in the transistor unit 70. However, the storage area 16 is not provided in the boundary area 81. That is, the storage region 16 is not provided in the second mesa portion 92 adjacent to the dummy trench portion 30. On the other hand, the contact region 15 is provided in the second mesa portion 92. In the semiconductor device 100 of this example, since the storage region 16 is not provided in the second mesa portion 92 sandwiched by the dummy trench portion 30, holes can be easily extracted to the emitter electrode 52 in the boundary region 81.

  FIG. 11 illustrates an example of the configuration of the semiconductor device 100 according to the fifth embodiment. The semiconductor device 100 of this example is different from the semiconductor device 100 according to the first embodiment in the structure of the dummy trench portion 30.

  The dummy trench portion 30 has a shape different from that of the gate trench portion 40 and the emitter trench portion 60. The dummy trench portion 30 in this example can adjust the gate-emitter capacitance of the semiconductor device 100 by adjusting the insulating film in the trench and the trench depth.

  The thickness of the dummy insulating film 32 is smaller than that of the gate insulating film 42 and the emitter insulating film 62. Thereby, the gate-emitter capacitance of the semiconductor device 100 is increased. In this example, the thickness of the dummy insulating film 32 is reduced without changing the width of the trench formed on the upper surface side of the semiconductor substrate 10. However, the film thickness of the dummy insulating film 32 is relatively increased by increasing the film thickness of the gate insulating film 42 and the emitter insulating film 62 by increasing the width of the trench for providing the gate trench portion 40 and the emitter trench portion 60. The thickness may be reduced.

  The trench depth of the dummy trench portion 30 is deeper than the trench depth of the gate trench portion 40 and the trench depth of the emitter trench portion 60. Thereby, the gate-emitter capacitance of the semiconductor device 100 is increased. In this example, although the trench depth of the dummy trench portion 30 is made deeper, the dummy trench portion is relatively made relatively by making the depth of the trench for providing the gate trench portion 40 and the emitter trench portion 60 shallow. The trench depth of 30 may be increased.

  In the semiconductor device 100 of the present example, the gate-emitter capacitance can be increased by reducing the film thickness of the dummy insulating film 32 and increasing the trench depth of the dummy trench portion 30. Thus, the influence of noise on the semiconductor device 100 is reduced. In the semiconductor device 100, the gate-emitter capacitance may be increased by adjusting either the film thickness of the dummy insulating film 32 or the trench depth of the dummy trench portion 30.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It is apparent to those skilled in the art that various changes or modifications can be added to the above embodiment. It is also apparent from the scope of the claims that the embodiments added with such alterations or improvements can be included in the technical scope of the present invention.

  The execution order of each process such as operations, procedures, steps, and steps in the apparatuses, systems, programs, and methods shown in the claims, the specification, and the drawings is particularly “before”, “preceding” It is to be noted that “it is not explicitly stated as“ etc. ”and can be realized in any order as long as the output of the previous process is not used in the later process. With regard to the flow of operations in the claims, the specification and the drawings, even if it is described using “first,” “next,” etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

10: semiconductor substrate, 11: well region, 12: emitter region, 14: base region, 15: contact region, 16: storage region, 18: drift region, 20 ··· Buffer region, 21 · · · upper surface, 22 · · · collector region, 23 · · · lower surface, 24 · · · collector electrode, 25 · · · connection portion, 30 · · · dummy trench portion, 31 · · · · Stretched portion 32 · · · Dummy insulating film, 33 · · · Connection portion, 34 · · · Dummy conductive portion, 38 · · · · · · · · · · · · · gate trench portion, 41 · · · stretch portion, 42: gate insulating film, 43: connection portion, 44: gate conductive portion, 48: gate runner, 49: contact hole, 50: gate metal layer, 52: emitter Electrode 54, contact hole, 6 contact hole 60 emitter trench 61 extended portion 62 emitter insulating film 63 connection portion 64 emitter conductive portion 70 transistor Portions 80: Diode portions 81: Boundary regions 82: Cathode regions 83: Non boundary regions 84: Edge adjacent regions 91: First mesa portion 92 · · Second mesa, 93 · · · third mesa, 95 · · · upper surface life time killer, 96 · · · lower surface life time killer, 100 · · · semiconductor devices, 102 · · · · edge termination region, 104 ... Outside region, 500 ... semiconductor device, 570 ... transistor portion, 580 ... diode portion

Claims (10)

A semiconductor device having a transistor portion and a diode portion,
The transistor portion and the diode portion are formed in a region adjacent to each other, and has a boundary region that prevents interference between the transistor portion and the diode portion.
The transistor unit and the diode unit include a plurality of trench units arranged in a predetermined arrangement direction.
The diode portion has a cathode region of the first conductivity type on the surface opposite to the front surface side of the semiconductor substrate,
The width of the diode portion in the arrangement direction is larger than the width of the transistor portion in the arrangement direction,
The semiconductor device, wherein the cathode region is extended to the boundary region in the arrangement direction. The semiconductor device according to claim 1, wherein a width of the diode unit is 1500 μm or more in the arrangement direction. It has multiple transistor parts and multiple diode parts,
The semiconductor device according to claim 1, wherein a total area of the plurality of diode parts is larger than a total area of the plurality of transistor parts. A gate metal layer provided above the upper surface of the semiconductor substrate;
An emitter electrode provided above the upper surface of the semiconductor substrate;
An emitter region of a first conductivity type provided on the upper surface side of the semiconductor substrate in the transistor portion;
A gate trench portion provided on the upper surface side of the semiconductor substrate in the transistor portion, electrically connected to the gate metal layer, and in contact with the emitter region;
An emitter trench portion provided on the upper surface side of the semiconductor substrate in the diode portion and electrically connected to the emitter electrode;
The semiconductor device according to any one of claims 1 to 3, wherein the emitter trench portion is arranged between the gate trench portions in a constant cycle also in the transistor portion. The semiconductor device according to claim 4, further comprising a dummy trench portion provided on the upper surface side of the semiconductor substrate, electrically connected to the gate metal layer, and not in contact with the emitter region. The semiconductor device according to any one of claims 1 to 5, wherein the boundary region is a region having a device structure different from the device structure of the transistor unit and the device structure of the diode unit. An interlayer insulating film provided above the upper surface side of the semiconductor substrate;
The transistor portion and the diode portion further include a contact hole provided in the interlayer insulating film between the trench portions and in which an emitter electrode is embedded.
The semiconductor device according to any one of claims 1 to 6, wherein the contact hole is not provided in the interlayer insulating film between the trench portions in the boundary region. The diode portion has the boundary region and a non-boundary region,
The semiconductor device according to any one of claims 1 to 7, wherein a concentration of the cathode region in the boundary region of the diode portion is higher than a concentration of the cathode region in the non-boundary region of the diode portion. The semiconductor device further comprises a lower surface lifetime killer provided opposite to the upper surface side of the semiconductor substrate,
The diode portion has the boundary region and a non-boundary region,
The semiconductor according to any one of claims 1 to 8, wherein a concentration of the lower surface lifetime killer in the boundary region of the diode portion is lower than a concentration of the lower surface lifetime killer in the non-boundary region of the diode portion. apparatus. The semiconductor device further comprises an upper surface lifetime killer introduced on at least a non-boundary region of the diode portion on the upper surface side of the semiconductor substrate,
The semiconductor device according to any one of claims 1 to 9, wherein the cathode region is provided so as to extend further to the transistor portion side than the upper surface lifetime killer.