JP6218735B2 - 空間変動電荷分布を用いた半導体ダイの間隔の決定 - Google Patents

空間変動電荷分布を用いた半導体ダイの間隔の決定 Download PDF

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JP6218735B2
JP6218735B2 JP2014534638A JP2014534638A JP6218735B2 JP 6218735 B2 JP6218735 B2 JP 6218735B2 JP 2014534638 A JP2014534638 A JP 2014534638A JP 2014534638 A JP2014534638 A JP 2014534638A JP 6218735 B2 JP6218735 B2 JP 6218735B2
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Prior art keywords
semiconductor die
spatial
time
driver
charge distribution
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Japanese (ja)
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JP2014530365A5 (https=
JP2014530365A (ja
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サザーランド，イバン・イー
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オラクル・インターナショナル・コーポレイション
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B7/00—Measuring arrangements characterised by the use of electric or magnetic techniques
    • G01B7/02—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring length, width or thickness
    • G01B7/023—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring length, width or thickness for measuring distance between sensor and object
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B7/00—Measuring arrangements characterised by the use of electric or magnetic techniques
    • G01B7/14—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring distance or clearance between spaced objects or spaced apertures
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B7/00—Measuring arrangements characterised by the use of electric or magnetic techniques
    • G01B7/30—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring angles or tapers; for testing the alignment of axes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07221—Aligning
    • H10W72/07223—Active alignment, e.g. using optical alignment using marks or sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/293—Configurations of stacked chips characterised by non-galvanic coupling between the chips, e.g. capacitive coupling

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)
  • Transducers For Ultrasonic Waves (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
JP2014534638A 2011-10-05 2012-10-02 空間変動電荷分布を用いた半導体ダイの間隔の決定 Active JP6218735B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/253,893 US9076663B2 (en) 2011-10-05 2011-10-05 Determining spacing using a spatially varying charge distribution
US13/253,893 2011-10-05
PCT/US2012/058487 WO2013052502A1 (en) 2011-10-05 2012-10-02 Determining spacing of semiconductor dies using a spatially varying charge distribution

Publications (3)

Publication Number Publication Date
JP2014530365A JP2014530365A (ja) 2014-11-17
JP2014530365A5 JP2014530365A5 (https=) 2015-10-15
JP6218735B2 true JP6218735B2 (ja) 2017-10-25

Family

ID=47143279

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014534638A Active JP6218735B2 (ja) 2011-10-05 2012-10-02 空間変動電荷分布を用いた半導体ダイの間隔の決定

Country Status (6)

Country Link
US (1) US9076663B2 (https=)
EP (1) EP2764539B1 (https=)
JP (1) JP6218735B2 (https=)
CN (1) CN103918075B (https=)
TW (1) TWI562300B (https=)
WO (1) WO2013052502A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9076663B2 (en) * 2011-10-05 2015-07-07 Oracle International Corporation Determining spacing using a spatially varying charge distribution
US8918752B2 (en) * 2011-12-14 2014-12-23 Oracle International Corporation Determining alignment using a spatially varying charge distribution

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2777632B2 (ja) * 1989-12-29 1998-07-23 株式会社日立製作所 記録方法及び記録装置
DE4200076A1 (de) * 1992-01-03 1993-08-05 Siemens Ag Passiver oberflaechenwellen-sensor, der drahtlos abfragbar ist
JP3052594B2 (ja) * 1992-08-24 2000-06-12 株式会社村田製作所 静電センサの感度調整方法および静電センサ
US6728113B1 (en) * 1993-06-24 2004-04-27 Polychip, Inc. Method and apparatus for non-conductively interconnecting integrated circuits
US6812046B2 (en) * 2002-07-29 2004-11-02 Sun Microsystems Inc. Method and apparatus for electronically aligning capacitively coupled chip pads
US6710436B1 (en) * 2002-12-12 2004-03-23 Sun Microsystems, Inc. Method and apparatus for electrostatically aligning integrated circuits
US7425836B2 (en) * 2006-08-23 2008-09-16 Sun Microsystems, Inc. Measuring chip-to-chip capacitance differentials by demodulating signals over a capacitance bridge
US7649255B2 (en) * 2006-12-06 2010-01-19 Sun Microsystems, Inc. Determining chip separation by comparing coupling capacitances
US7786427B2 (en) * 2008-05-06 2010-08-31 Oracle America, Inc. Proximity optical memory module having an electrical-to-optical and optical-to-electrical converter
US9182782B2 (en) * 2011-09-22 2015-11-10 Oracle International Corporation Synchronizing timing of communication between integrated circuits
US9076663B2 (en) * 2011-10-05 2015-07-07 Oracle International Corporation Determining spacing using a spatially varying charge distribution
US8918752B2 (en) * 2011-12-14 2014-12-23 Oracle International Corporation Determining alignment using a spatially varying charge distribution

Also Published As

Publication number Publication date
EP2764539A1 (en) 2014-08-13
US9076663B2 (en) 2015-07-07
WO2013052502A1 (en) 2013-04-11
CN103918075A (zh) 2014-07-09
JP2014530365A (ja) 2014-11-17
EP2764539B1 (en) 2018-02-28
TWI562300B (en) 2016-12-11
TW201334134A (zh) 2013-08-16
CN103918075B (zh) 2017-02-15
US20130088212A1 (en) 2013-04-11

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