JP6166769B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP6166769B2 JP6166769B2 JP2015242094A JP2015242094A JP6166769B2 JP 6166769 B2 JP6166769 B2 JP 6166769B2 JP 2015242094 A JP2015242094 A JP 2015242094A JP 2015242094 A JP2015242094 A JP 2015242094A JP 6166769 B2 JP6166769 B2 JP 6166769B2
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- Japan
- Prior art keywords
- gold
- electrode pad
- wire loop
- gold ball
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
- H01L2224/48991—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on the semiconductor or solid-state body to be connected
- H01L2224/48992—Reinforcing structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
図1〜図4は、本発明の第1の実施形態に係る半導体装置の製造方法の工程を概略的に示す縦断面図であり、図5は、図4の構造体を概略的に示す平面図である。
図7は、本発明の第2の実施形態に係る半導体装置の製造方法の工程を概略的に示す縦断面図であり、図8は、図7の構造体を概略的に示す平面図であり、図9は、本発明の第2の実施形態に係る半導体装置及びその製造方法を説明するための要部拡大図である。
図10は、本発明の第3の実施形態に係る半導体装置の製造方法の工程を概略的に示す縦断面図であり、図11は、図10の構造体を概略的に示す平面図であり、図12は、第3の実施形態に係る半導体装置及びその製造方法を説明するための要部拡大図である。
Claims (3)
- 矩形の主面と前記主面の一辺に対応して設けられた電極パッドとを備えた半導体チップと、
前記電極パッドに対応して設けられ、前記半導体チップと離間して配置された外部電極と、
前記電極パッドに接続された第1の金球からなる一端と、前記電極パッドの対応する前記外部電極に接続された他端と、前記一辺を跨いで前記第1の金球と前記他端とを接続するワイヤと、を備えたワイヤループと、
前記ワイヤと前記第1の金球の頂部とに接続された底部を有する第2の金球と、
を有し、
前記主面に対し垂直方向に投影された前記第2の金球の中心位置は、前記主面に対し垂直方向に投影された前記第1の金球の中心位置に対して、前記ワイヤの長手方向にずれており且つ前記電極パッドの前記一辺側に位置し、
前記第2の金球は、前記主面に対し垂直方向に投影された前記第2の金球に対応する領域が、前記主面に対し垂直方向に投影された前記第1の金球に対応する領域の前記一辺とは反対側の端面を露出させる位置に、配置され、
前記ワイヤは前記第1の金球と前記第2の金球とに挟まれている
ことを特徴とする半導体装置。 - 前記電極パッドの表面から前記第2の金球の頂部までの高さは、前記電極パッドの表面と同一平面上から前記ワイヤループの最上部までの高さよりも高いことを特徴とする請求項1に記載の半導体装置。
- 前記電極パッドと前記外部電極との間に位置する前記主面上には、絶縁膜が形成されていることを特徴とする請求項1又は2に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015242094A JP6166769B2 (ja) | 2015-12-11 | 2015-12-11 | 半導体装置 |
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JP2015242094A JP6166769B2 (ja) | 2015-12-11 | 2015-12-11 | 半導体装置 |
Related Parent Applications (1)
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JP2013111057A Division JP5890798B2 (ja) | 2013-05-27 | 2013-05-27 | 半導体装置及びその製造方法 |
Publications (2)
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JP2016034048A JP2016034048A (ja) | 2016-03-10 |
JP6166769B2 true JP6166769B2 (ja) | 2017-07-19 |
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JP2015242094A Active JP6166769B2 (ja) | 2015-12-11 | 2015-12-11 | 半導体装置 |
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JP (1) | JP6166769B2 (ja) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3659406B2 (ja) * | 2001-06-07 | 2005-06-15 | セイコーエプソン株式会社 | バンプ構造とバンプの製造方法 |
JP4105996B2 (ja) * | 2003-07-25 | 2008-06-25 | 株式会社新川 | ワイヤボンディング方法 |
US7475802B2 (en) * | 2004-04-28 | 2009-01-13 | Texas Instruments Incorporated | Method for low loop wire bonding |
JP2008117888A (ja) * | 2006-11-02 | 2008-05-22 | Rohm Co Ltd | 電子部品、およびワイヤボンディング方法 |
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