JP6154824B2 - ステートマシンラチスにおけるブール型論理 - Google Patents
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- H—ELECTRICITY
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/045—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using logic state machines, consisting only of a memory or a programmable logic device containing the logic for the controlled machine and in which the state of its outputs is dependent on the state of its inputs or part of its own output states, e.g. binary decision controllers, finite state controllers
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- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
- G06F9/4498—Finite state machines
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
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- H03K—PULSE TECHNIQUE
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- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Description
Claims (8)
- 入力ブロックと、
出力ブロックと、
複数のブロックと、
前記入力ブロック、前記出力ブロック及び前記複数のブロック間にそれぞれ設けられ、前記入力ブロック、前記出力ブロック及び前記複数のブロック相互間の信号の送受信を制御する複数のブロック間スイッチと、
を備え、前記複数のブロックは各々が、
複数の行と、
前記複数の行にそれぞれ対応して設けられる複数のブロック内スイッチであって、前記複数のブロック間スイッチのうちの対応する少なくとも1つのブロック間スイッチ及び前記複数のブロック内スイッチ間で信号の送受信を行うように構成された前記複数のブロック内スイッチと、
を備え、前記複数の行のうち第一の行が、
前記第一の行に対応する前記ブロック内スイッチに接続される第一行相互接続導体と、
それぞれが、前記第一行相互接続導体に並列に接続され、受信したデータストリームの少なくとも一部分の分析結果を前記第一行相互接続導体に出力するように構成された複数の第一プログラマブル素子と、
前記複数の第一プログラマブル素子と並列に前記第一行相互接続導体に接続された第一ブール型論理セルであって、前記第一ブール型論理セルは前記第一行相互接続導体を介して、少なくとも前記複数の第一プログラマブル素子からの出力を入力として受けて論理演算を実行する前記第一ブール型論理セルと、
を備えるデバイス。 - 前記複数の行に含まれる第二の行が、
前記第二の行に対応する前記ブロック内スイッチに接続される第二行相互接続導体と、
それぞれが、前記第二行相互接続導体に並列に接続され、受信したデータストリームの少なくとも一部分の分析結果を前記第二行相互接続導体に出力するように構成された複数の第二プログラマブル素子と、
前記複数の第二プログラマブル素子と並列に前記第二行相互接続導体に接続された第二ブール型論理セルであって、前記第二ブール型論理セルは前記第二行相互接続導体を介して、少なくとも前記複数の第二プログラマブル素子からの出力を入力として受けて論理演算を実行する前記第二ブール型論理セルと、
を備える請求項1に記載のデバイス。 - 前記第二ブール型論理セルは、前記複数の第二プログラマブル素子からの出力に加え、前記第二行相互接続導体、前記第二の行に対応する前記ブロック内スイッチ、前記第一の行に対応する前記ブロック内スイッチ及び前記第一行相互接続導体を介して、前記複数の第一プログラマブル素子からの出力を入力として受けて論理演算を実行する請求項2に記載のデバイス。
- 前記複数の行に含まれる第三の行が、
前記第三の行に対応する前記ブロック内スイッチに接続される第三行相互接続導体と、
それぞれが、前記第三行相互接続導体に並列に接続され、受信したデータストリームの少なくとも一部分の分析結果を前記第三行相互接続導体に出力するように構成された複数の第三プログラマブル素子と、
前記複数の第三プログラマブル素子と並列に前記第三行相互接続導体に接続されたカウンタであって、前記カウンタは前記第三行相互接続導体、前記第三の行に対応する前記ブロック内スイッチ、前記第一の行に対応する前記ブロック内スイッチ及び前記第一行相互接続導体を介して、前記第一ブール型論理セルに接続される前記カウンタと、
を備える請求項1に記載のデバイス。 - 前記第一ブール型論理セルは、複数のプログラマブルビットの値に応じて互いに異なる論理演算を実行可能に構成される請求項1に記載のデバイス。
- 前記第一ブール型論理セルは、前記第一ブール型論理セルから出力される信号を生成する最終出力回路を備え、前記最終出力回路は前記複数のプログラマブルビットのいずれか一つに応じてANDゲートもしくはORゲートのいずれかとされる請求項5に記載のデバイス。
- 前記第一ブール型論理セルは、前記第一ブール型論理セルの前記入力をマスクするマスキング入力信号を受ける請求項1に記載のデバイス。
- 前記第一ブール型論理セルは、前記複数のプログラマブルビットのいずれか一つに応じて前記第一ブール型論理セルの前記入力の論理を反転する請求項5に記載のデバイス。
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US13/327,510 US8593175B2 (en) | 2011-12-15 | 2011-12-15 | Boolean logic in a state machine lattice |
US13/327,510 | 2011-12-15 | ||
PCT/US2012/067992 WO2013090092A1 (en) | 2011-12-15 | 2012-12-05 | Boolean logic in a state machine lattice |
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JP2015508588A JP2015508588A (ja) | 2015-03-19 |
JP6154824B2 true JP6154824B2 (ja) | 2017-06-28 |
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US (4) | US8593175B2 (ja) |
EP (1) | EP2791835B1 (ja) |
JP (1) | JP6154824B2 (ja) |
KR (1) | KR101873619B1 (ja) |
CN (2) | CN108256164B (ja) |
TW (1) | TWI489779B (ja) |
WO (1) | WO2013090092A1 (ja) |
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US8593175B2 (en) | 2013-11-26 |
US20150365091A1 (en) | 2015-12-17 |
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JP2015508588A (ja) | 2015-03-19 |
KR20140102274A (ko) | 2014-08-21 |
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US20140077838A1 (en) | 2014-03-20 |
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