TWI317486B - Architecture for finite state machine decomposition - Google Patents

Description

1317486 '• Nine, invention description: [Technical field to which the invention pertains] The present invention relates to a circuit decomposition architecture, in particular, a low power: decomposition architecture of a finite state machine circuit. [Prior Art] » Cutting a finite state machine _ cutting her machine; FSM) circuit into a sub-state machine (SUb-machine) circuit, which has been proven to effectively reduce the average power of the overall finite state machine circuit. (average p〇wer). The principle is that when the finite state machine is in operation, only the state machine circuit of the second state is driven, and the other * need to be made: the operation of the under-glyph circuit is used to reduce the overall finite shape. (switching activities), thereby achieving the goal of reducing the average power. In the literature, most of them only discuss how to reduce the average 'power' of finite state machine circuits. The present invention proposes a new improved architecture that can not only reduce the average finite shape of the body, but also reduce the finite state machine. The peak power of the circuit (peak power;). As the complexity of the integrated circuit and Wang Zuosheng increase, the problem of power consumption becomes more and more serious and more and more important. The dynamic power consumption is dominated by the signal switching action in the circuit. The principle is that the logic value of the circuit is rounded up. 5 8 1317486 • When there is a change, the parasitic capacitance will be charged and discharged via VDD or Vss. Therefore, the dynamic power consumption has a proportional relationship with the signal switching action in the circuit. : A finite state machine can be defined as a set of six sets {I, S, δ, 〇, λ, S〇}, where the set of I-inputs is the set of S-states, and the δ-system IxS— 2s is the function of the state transition 'the output of the output system, the λ system lxS-^20 is the output function, and finally S〇eS is the set of the initial state. A finite state machine can also be described by a state transition graph (STG). The finite state machine STG can be recorded as Gm (Vm, Em), where the set of Vm nodes (node) represents M State set; Em = {<u, v>, u, set of edges, each side represents a state u jumping from M to another state v 'all sides are A set of inputs and outputs are indicated, which in the STG diagram represent changes in the input trigger state and produce a relative output. φ For the finite state machine circuit, an effective way to switch the action of the health is to turn off the part of the overall finite state machine circuit that is not used temporarily, that is, '豸-have a profitable circuit. The circuit, and only drives the material - and stops other state machine circuits that do not need to be used. However, it is worthy of being tolerant that the 'statement circuit that is segmented out and the finite shape of the original tradition are not divided, and the system of facial recordings is also present. The circuit starts or reaches the state of another state machine circuit, which will make the circuit more complicated in segmentation and design. 8 6 1317486 · · · A finite state machine circuit cutting method is called "sequential logic decomposition (SLD)" cutting structure (as shown in the first a figure, shown) to a finite state machine The circuit is cut into two sub-finite state machines M1, ^ M2 as an example, which uses the clocks of the secondary finite state machines M1 and M2 to stop the register of the finite state machine M1 or M2 which is not needed to be used. Thereby, the input of the combined circuit of the next state of the finite state machine M1 or M2 of the stopped clock is not changed, thereby reducing the input signal change of the overall circuit of the sub-finite state machine M1, M2. More details can be See JC Monterio and AL Oliveria, "Finite State Machine Decomposition for Low

Power55, Proc. Design Automaton Conference, 1998, pp. 758-763 and L. Benini and G. De Micheli, "State Assignment for Low Power Dissipation", in the Solid-State Circuits, IEEE Journal of

Volume 30, Issue 3, 1995, pp. 258-268 ° and another finite state machine circuit is cut by a "combinational logic decomposition (CLD)" cutting architecture (eg. Show). Taking the two finite state machines M1, M2 cut as an example, it uses several AND gates to block the input of the secondary finite state machine M1 or M2 that is not needed. For example, when the secondary finite state machine M1 circuit is in the off state, the decoder sends a logic signal to the third gate of the secondary finite state machine M1 circuit, thereby inputting the secondary finite state machine M1 circuit. Becomes a logic 0. If the sub-finite state machine M1 circuit is still turned off after the 1317486 state, the input to the sub-finite state machine M1 circuit will also be a logic 0. In this way, the decomposition architecture can also reduce the input switching frequency of the input finite state machine ΜΙ, M2 to reduce the signal switching action in the circuit. For more details, see SH Chow, YC Ho, T. Hwang and CL Liu, "Low Power Realization of Finite State Machine-A Decomposition Approach'', ACM TODAES, vol. 1, 1996, pp. 315-340. According to the above-mentioned combination logic decomposition cutting structure, if the gate and the gate are used to control the action of the secondary finite state machine M1, M2, when one of the secondary finite state machines M1 or M2 is to be turned off, the gate will be forced to be shut down. The input of the finite state machine M1 or M2 is all logical 〇. Therefore, at the moment when the secondary finite state machines M1 and M2 are transferred, the two finite state machines M1 and M2 will have the switching action of the input signal. The effect is equivalent to the operation of two sub-finite state machines M1, M2. For example, when jumping from the sub-finite state machine mi to the sub-finite state machine M2, the gate before the sub-finite state machine M1 forces the sub-finite state machine Ml All the inputs are all logical, and at the same time, the storage state registers FF, FF1, ff2 t pour the content value into the secondary finite state machine M2. Therefore, the moment when the secondary finite state machine M1 shifts to M2 The secondary finite state machine M1, M2 will have the switching action of the input signal, this phenomenon will cause a large peak power (because the secondary finite state machine Μι, m2 - change). In view of the above finite state machine circuit decomposition The shortcomings of the architecture 'there is a need to continue to develop new improved circuit decomposition architectures to overcome the lack of (4) various 1317486 techniques. Therefore, how to avoid the state switching of finite state machine circuits and how to reduce the peak power and average power of finite state machine circuits Etc., this technology: the problem that the field will inevitably encounter, and the problem to be solved by the present invention. [Invention] In view of the above-mentioned background of the invention, in order to meet the needs of certain interests in the industry, φ the present invention & The decomposition architecture of the state machine circuit solves the problem that the conventional finite state machine circuit decomposition architecture fails to achieve. The present invention discloses a decomposition architecture of a finite state machine circuit, which selects an output state according to a selection signal by a storage module. Signal and flash other unselected status signals, thereby 'changing only one The input of the finite state machine circuit reduces the peak power and average power of the finite cancer computer circuit; and adjusts the signal transmission time by a buffer module, so that this state signal and this selection The signal can be received by the storage module at the same time, thereby avoiding delay errors caused by the difference in the level of signal processing. The present invention provides a decomposition architecture of a finite state machine circuit, which includes: a plurality of finite state machine modules, Receiving a plurality of first state signals and a first input signal, and correspondingly outputting a plurality of second state signals, a plurality of output signals, and a plurality of first selection signals; and a selection module receiving the second states The signal, the output signals, the first selection signals and a second selection signal 1317486', and selecting one of the second status signals according to the second selection signal, one of the output signals and the One of the first selection signals is output; a temporary storage module receives the second status signal outputted by the selection module and the first selection signal And outputting the second state signal and the second selection signal; the decoding module receives the second selection signal and outputs a third selection signal after decoding; and a storage module receives a second input signal The second state signal and the third selection signal 'and output the first state signal and the first input h number 'where the storage module replaces the first input signal with the second input signal and The second status signal replaces the first status signal selected by the third selection signal. The invention further provides a decomposition architecture of a finite state machine circuit, comprising: two finite state machine modules, corresponding to receiving two first state signals and a first input signal, and correspondingly outputting two second state signals, two The output signal and the two first selection signals; the plurality of multiplexers correspondingly receive the two second state signals, the two output signals, the two first selection signals and a second selection signal, and accordingly the second selection signal Selecting one of the two second state signals, one of the two output signals and one of the two first selection signals; the plurality of flip-flops corresponding to the second state signal receiving the outputs of the plurality of multiplexers And the first selection signal 'and temporarily storing the first state signal and the second selection signal; a decoder receiving the second selection signal 'and decoding and outputting a third selection signal; a plurality of storage devices, Correspondingly receiving a second round-in signal, the second state signal 1317486 and the third selection signal 'and outputting the two first state signals and the first input signal' The storage device replaces the first input signal with the second input signal and replaces the first state signal selected by the third selection signal with the second state signal; and a buffer module is used to make the second The status signal and the third selection signal can be simultaneously output to the storage devices. [Embodiment] The direction of the invention discussed herein is a decomposition architecture of a finite state machine circuit. In order to fully understand the present invention, detailed steps and compositions will be set forth in the following description. It is apparent that the practice of the invention is not limited to the specific details familiar to those skilled in the art. On the other hand, well-known components or steps are not described in detail to avoid unnecessarily limiting the invention. The preferred embodiments of the present invention will be described in detail below, but the present invention may be widely practiced in other embodiments, and the scope of the present invention is not limited, and the scope of the invention is Prevail. Referring to the first figure, which is a schematic block diagram of a preferred embodiment of the present invention. a plurality of finite state machine modules, M: 2, ..., Mn, corresponding to receiving a plurality of first state signals and a first wheeling signal (where the first input signal is coupled with the plurality of first state signals) A plurality of signals 丨〇4) are formed, and a plurality of second state signals 112, a plurality of output signals 116, and a plurality of first selection signals 114 are correspondingly rotated. In this embodiment, the finite state machine module Μι, 11 1317486 '* M2, ..., Mn is formed by cutting a finite state machine circuit 110, and its architecture can be cut according to the actual wire. , is not limited to the structure of the paste, where η 22 and η are natural numbers. In this embodiment, the first input signal system includes a 1-bit data (丨> i and i is a natural number); each first state signal includes a j-bit data (j > 〇 and j a natural number); each second state signal 112 includes a j-bit data; each output signal 116 includes a q-bit data (q > 0 and q is a natural number); and each first selection signal The 114 series contains _k • bit data (k > 〇 and k is a natural number), where each m-bit signal 1〇4 is composed of an i-bit first input signal and a j-bit first state The signal consists of m = i + j ' and the relationship between the number k of the first selection signal 114 and the number η of the finite state machine modules Μ, M2, ..., Mn is n$2k. The selection module 120 receives the second state signal 112, the output signal 116, the first selection signal 114 and a second selection signal 134, and selects the second state signals 112 according to the second selection signal 134. 1. Outputting one of the output call signals 116 and one of the first selection signals 114, wherein the signals 124 (including the second state signal and the first selection signal) and the output signal 122 of the selection module 120 are limited by One of the state machine modules, M2, ..., Mn is generated. In this embodiment, the second selection signal 134 is a relative to the first selection signal 114; the bit data, the p-bit k is 124 is selected by a j-bit first state signal and a k-bit first selection The signal 114 is composed of p=j+k° 12 1317486. A temporary storage module 130 receives the number of the selection module 120 (including the second status signal and the first selection signal), and is temporarily stored. The first state signal 132 and the second selection signal 134 are rotated. A decoding module 140 receives the second selection signal 134 ′ output by the temporary storage module 并且 30 and outputs a third selection signal 142 after decoding, wherein the second selection § § 142 includes an r bit data. (r = 2k). A storage module 150 receives a second input signal 1 〇 2, a second status signal 132 output by the temporary storage module 130, and a first selection 佗 142 rotated by the decoding module 14 ,, and the output is limited. The state machine module Mi, Ms, ..., μ corresponds to a plurality of signals 104 (first state signal and first input signal) received. In this embodiment, the storage module 150 replaces the first input signal with the second input signal 1〇2, and replaces the first status signal selected by the third selection signal 142 with the second status signal 132, that is, stores The module 15 selects a first state signal according to the third selection signal 142, and replaces the first state signal with the second state signal 132, while the other unselected first state signals remain unchanged, thereby Changing the input of a finite state machine module avoids simultaneous changes in all input states of the finite state machine circuit 11 to reduce the peak power and average p0wer of the finite state machine circuit 11(). A buffer module 160' is configured to enable the second status signal 132 output by the temporary storage module 130 and the third selection signal 142 output by the decoding module 14 to arrive at the storage module 150' at the same time, thereby avoiding The number of stages of signal processing is different and 1317486 produces a delay error. In this embodiment, the buffer module 16 is configured to delay the clock (6) of the circuit of the second state signal 132 by the temporary storage module 130, and the time of the delayed clock 162 is equal to the decoding module 14 and the second The time required for the selection signal 134 to be decoded into the third selection signal 142, whereby the second state signal 132 output by the temporary storage module 13 is simultaneously with the third selection signal 142 rotated by the decoding module 14 Output to the storage module 150 to avoid delay errors due to different levels of signal processing. In another embodiment, the buffer module 16 can be added between the temporary storage module 130 and the storage module 150 as a data buffer of the second status signal 132, thereby making the signal processing level the same. To avoid the above delay errors. Please refer to the third figure, which is a state transition graph (STG) of a finite state machine. In the present embodiment, this finite state machine is only used to illustrate the example of the present invention, which is not intended to limit the implementation of the present invention. The finite state machine system includes seven states, which are respectively S1 (state 〇〇〇), S2 (state 001), S3 (state 111), S4 (state 010), and S5 (state 1). 0), S6 (state 011) and S7 (state 101), wherein the 7 states are divided into subsets of two states S' = {Sl, S4, S6} and S" = {S2, S3, S5 , S7}, and then use S' and S respectively to form a decomposition structure of the finite state machine module Mi, Μ, which will be described later. When S1 (state 000) input is 〇, the state changes to S6 (state is oil) and the output is 00; when S1 input is 1, the state changes to S4 (state is 01〇) and 1317486 · output is (eight). When the S4 (state 010) input is 〇, the state changes to S6 (state 011) and the output is 00; when the S4 input is 1, the state changes to S6 and the output is 10. When the input of S6 (state 011) is 〇, the state becomes Sl (state 〇〇〇) ' and the output is 01; and when the S6 input is 1, the state becomes S2 of different subsets (state 001) and the output Is 01. When S2 (state 001) is rounded, the state changes to S5 (state is 1〇〇) and the output is 00; when S2 input is 1, the state changes to S3 (state is m) and the output is 〇〇. When the S3 (state 111) input is 〇, the state changes to S5 (state is 1 〇〇) and the output is 〇〇; when the S3 input is 1, the state changes to S7 (state 101) and the output is 〇〇. When the input of S5 (state 1〇〇) is 〇, the state becomes Sl of different subsets (state is 〇〇〇) and the output is 1〇; when the input of S5 is 1, the state becomes S2 (state is 〇〇1) And the output is 1〇. When S7 (state 101) input is 〇, the state changes to S5 (state is 1〇〇) and the output is 00, and when S7 input is 1, the state becomes S6 of different subsets (shape is 011) and the output Is 10. The following list is the truth table of the finite state machine mentioned above, • The FFO field controls the content value of the finite state machine module and the register FFO of the m2 switch (refer to the following description).

Current state D2D1D0 Input next state Q2Q1Q0 Round FFO Ml S1 000 0 S6 011 ___〇〇〇-1 S4 010 00 0 15 1317486 S4 010 0 S6 011 00 0 1 S6 011 10 0 S6 011 0 S1 000 01 0 1 S2 001 01 1 M2 S2 001 0 S5 100 00 1 1 S3 111 00 1 S3 111 0 S5 100 00 1 1 S7 101 00 1 S5 100 0 S1 000 10 0 1 S2 001 10 1 S7 101 0 S5 100 00 1 1 S6 011 10 0 Table 1 The truth table of the above finite state machine

Please refer to the fourth figure, which is an exploded structural diagram of a preferred finite state machine circuit implemented according to the embodiment of the third embodiment of the present invention. The two finite state machine modules M2 receive corresponding two first state signals and a first input signal (where the first input signal is respectively matched with the two first state signals), and correspondingly output two second states The signal, the two output signals and the two first selection signals. Among them, the finite state machine module Μ!, Μ 2 system is cut into a finite state machine circuit 11〇, and its architecture can be cut according to actual needs, and is not limited to the dicing 1317486 architecture, for example :Ml has the state subset of S, = {Sl, S4, S6}; and M2 has the state subset of s - {S2, S3, S5, S7} above. In this embodiment, the first input signal includes an i-bit data (i > and i is a natural number); each first state signal includes a j-bit data (j > 0 and j is a natural number); each second state signal system includes a j-bit data; each output signal includes a q-bit data (q> and q is a natural number); and each of the first selection signals includes one K-bit data (k>0 and k is a natural number), where i==1, j=3, 1, q=2, but it is not limited thereto, and the like can be adjusted according to actual needs, and the first The relationship between the number of bits k of the selection signal and the number n of finite state machine modules is η $ 2k. a plurality of multiplexer MUXs (corresponding to the selection module 12A of the second figure), corresponding to receiving the second state signal, the output signal, the first selection signal and a second selection signal 'and according to the second selection signal Selecting one of the two second state signals, one of the output signals and one of the first selection signals, and in the embodiment, the second state signal, the first selection signal output by the multiplexer MUX The output signal is generated by one of the finite state machine modules M1, M2. Further, the second selection signal is a k-bit data relative to the first selection signal, but is not limited thereto. A plurality of flip-flops FF3, FF2, FF1, FFO (cf. the temporary storage module 130 of the second figure) are corresponding to receiving the first-shaped hetero-signal and the first selection signal outputted by the plurality of multiplexers MUX, and temporarily And storing the second state signal (outputted by FF3=(S) 17 1317486 FF2 and FH) and the second selection signal (by output), the second selection signal being the control finite state machine module Mi, The content value of the register FFO of the M2 switch. a decoder (comprising the decoding module 14A of the second figure) receives the second selection signal output by the flip-flop FFO, and decodes and outputs a third selection signal, where 'this second selection signal includes A 1* bit data (r = 2k). Therefore, when k=l, the third selection signal of the two bits can directly control the switches of the two finite state machine modules M1 and M2. A plurality of latches (comprising the storage module 15A of the second figure) are corresponding to receiving a second input signal, a second state signal output by the flip-flops FF3, FF2, and FF1, and a third output by the decoder. The signal is selected, and the two first state signals corresponding to the two finite state machine modules M1 and M2 and the first input signal are output. In this embodiment, the latches replace the first input signal with the second input signal, and replace the first state signal selected by the third selection signal with the second state signal, that is, the latches. The second state signal is transmitted to the open finite state machine module M1 or M2 according to the third selection signal to replace the original first state signal, and the other unselected first state signals remain unchanged. Only the input of a finite state machine module is changed to avoid simultaneous changes in all input states of the finite state machine circuit 11 and to reduce the peak power and average power of the finite state machine circuit. In another embodiment, the plurality of latches described above may be replaced by a storage device such as a memory. 18 1317486 A buffer (the storage group _, _ in the second figure enables the second status signal output by FF3, FF2, FF1 and the third selection signal rotated by the decoding HHO to simultaneously reach a plurality of flashes, Therefore, the signal processing stage is prevented from being turned off and a delay error is generated. In this embodiment, the clock of the 〇3/FF1 is delayed, and the delayed clock system is equal to the decompressor (10). The second selection signal is decoded into a pulse system required for the third selection money, whereby the second state signal output by the flip-flops FF3 FFFF1 and the third selection signal output by the decoder (10) can be simultaneously output to the plurality of challenge locks. In order to avoid the above-mentioned delay error, please refer to the fifth A diagram and the fifth b diagram, which are respectively the fourth embodiment shown in the third figure, with the conventional combinational logic decomposition (CLD) and the fourth The decomposition of the diagram is implemented in the letter of perception. These two waveforms are used to illustrate the relationship between the signals shown in the longitudinal direction, while the horizontal system represents the time axis, as for other unlabeled units (such as voltage units, time units). ) are omitted here for the sake of simplicity. Please refer to the fifth. In Figure A, at the time of Ts, the state jumps from S6 of the finite state machine module M1 to S2 of the finite state machine module m2, and the signal MI-ΟΝ changes from 1 (indicating that the finite state machine module is turned off) M1), the signal M2—ON changes from 0 to 1 (indicating that the finite state machine module μ is turned on), therefore, the M1 input changes from ion to 'the M2 input changes from 0000 to □. The state jumps from S5 of M2 to S1 of M1, and the signal Μ1_ΟΝ changes from 0 to 1 (indicating that M1 is turned on), and the signal μ2_ΟΝ changes from 1 (indicating that 19 1317486 M2 is turned off), therefore, the M1 input changes from 〇〇〇〇. 〇〇, and the M2 input changes from 0100 to 0000. At the time T13, the state jumps from S6 of M1 to S2 of M2, and; the signal Ml_ΟΝ changes from 1 to 〇 (indicating that M1 is turned off), and the signal M2_ON changes from 0 to 1; Indicates that M2 is turned on. Therefore, the M1 input changes from 1011 to 0000, and the M2 input changes from 0000 to 1001. Please refer to Figure 5B. At the T5 time, the state jumps from the finite state machine | module M1 to the limited S2 of the state machine module M2, and the signal

Ml_〇N changes from 1 to 0 (indicating that the finite state machine module M1 is turned off), and the signal M2_ON changes from 0 to 1 (indicating that the finite state machine module M2 is turned on), therefore, the M1 input changes from 1011 to 1011, and the M2 input Change from xxxx to 1001. At time T9, the state jumps from S5 of M2 to S1 of M1, and the signal Μ1_ΟΝ changes from 0 to 1 (indicating that M1 is turned on), and the signal Μ2_ΟΝ changes from 1 to 0 (indicating that M2 is turned off), therefore, the M1 input changes from 1011 to 0000. And the M2 input changes from 0100 to 0100. At the time T13, the state jumps from S6 of M1 to S2 of M2, and the B signal Μ1_ΟΝ changes from 1 to 0 (indicating that M1 is turned off), and the signal M2_ON changes from 0 to 1. (Indicating that M2 is turned on) 'So, M1 is input from 1011. Change 1011, and the M2 input changes from 0100 to 1001. The state changes between M1 and M2. The input value of M1 changes M2. The input value changes Ml_M2 1011—0000 0000—1001 20 1317486 M2—Ml 〇〇〇〇—〇〇〇〇0100—0000 Ml—M2 1011—0000 0000—1001 Table 2A uses the cutting logic of the combinatorial logic decomposition. When the state transitions between M1 and M2, the state of the input value change of the input finite state machine modules M1 and M2 transfers M1 to each other between M1 and M2. Input value change M2 input value change Ml -> M2 1011 - 1011 xxxx - 1001 1011 - ^ 0000 0100 - 0100 1011 - 1011 0100 - 1001 Table 2 B uses the decomposition diagram of the fourth figure, the state is between Ml, M2 During the transfer, input the change of the input value of the finite state machine module Ml, M2 (any value or random value of the xxxx table). Table 2A and Table 2B are respectively the cutting structure using the combinational logic decomposition and the use of the fourth figure. The decomposition architecture, when the state transitions between the finite state machine modules M1 and M2, inputs the change of the input values of the finite state machine modules M1 and M2. According to the above waveform diagram and the following table data, in the fifth A diagram and the second table A, when the state transition between M1 and M2, the input of M1 and 1317486 M2 will change at the same time, at this time, mi and M2 will be There is a signal switching action 'that is to increase the peak power of the circuit. On the other hand, in the fifth B and the table B, when M1 and M2 are mutually transferred, the input of M1 and M2 does not change at the same time, and there must be an input of Μ or M2.疋 Stay still', for example: When the current state is transferred from M1 to M2, the input of Ml is ion-maintained. Thus, the decomposition architecture of the present invention provides a significant reduction in peak power for the overall finite state machine circuit.

M1 input value change M2 input value change 1 1000->1010 1 0000-1001 2 1010-1011 2 1001—0001 3 1011—0000 3 0001-^0100 4 〇〇〇〇一〇〇11 4 0100—0000 5 0011—1011 5 0000—1001 6 1011—0000 6 1001—1111 7 1111—1101 8 1101—0101 9 0101—0100 Table 3A uses the combination logic to decompose the cutting architecture, and all the input changes of M2 22 1317486

M1 input value change M2 input value change 1 1000-1010 1 χχχχ^ΙΟΟΙ 2 1010—1011 2 1001—0001 3 1011—^0000 3 0001—0100 4 0000-^0011 4 0100-^1001 5 0011—4011 5 1001—1111 6 1111—1101 7 1101-^0101 8 0101—0100

Table 3B uses the decomposition structure of the fourth figure, all the input changes of the μB M2 (any value or random value of the xxxx table). Table 3Α and Table 3 are respectively the cutting structure using the combinational logic decomposition and the decomposition using the fourth figure. Architecture, finite state machine module Ml, M2 all input changes. In terms of average power (average power), the average power is related to the total number of input changes of M1 and M2. Therefore, comparing Table 3A and Table 3B, it can be found from Table 3A that when using the combination logic decomposition (CLD) cutting architecture, the sum of the number of changes in the Ml and M2 rounds is 15; It was found that when using the decomposition architecture of the present invention, the sum of the number of input changes of VII and M2 is 13. Thus the decomposition architecture of the present invention is directed to the overall finite state machine circuit

The average power of 23 1317486 has a significantly reduced effect. Please refer to the sixth figure, which is a signal waveform diagram of the embodiment shown in the third figure, which is decomposed by the fourth figure and implemented with different inputs. This waveform diagram is only used to illustrate the relationship between the signals shown in the longitudinal direction, and the horizontal system represents the time axis. Other unlabeled units (such as voltage units and time units) are omitted here for illustration. concise. At time D, the state jumps from S6 of the finite state machine module to S2 of the finite state machine module m2, and the signal Μ1") Ν changes from 1 (indicating that the finite state machine module M1 is turned off) The signal M2J3N changes from 〇 to 1 (indicating that the finite state machine module M2 is turned on), therefore, the M1 input changes from l〇u to 1001, and the M2 input changes from χχχχ1 to 1. At the time of the tu, the state jumps from S7 of M2 to S6 of M1, and the signal Μ1_ΟΝ changes from 0 to 1 (the table turns on M1), and the signal M2_ON changes from 1 (the table turns off M2), therefore, the M1 input is from 1011. Change 1011 ' and the M2 input changes from 1101 to 11〇1. At the time of τ13, the state jumps from S6 of M1 to S2 of M2, and the signal Μ1_ΟΝ changes from 1 to 〇 (the table does not turn off M1) 'Signal Μ2_ΟΝ changes from 0 to 1 (indicating that M2 is turned on), therefore, the M1 input changes from 1011 〇11, and the m2 input changes from n〇1 to 1〇〇1. According to this waveform diagram, the input of the finite state machine module Mi, M2 does not change at the same time, for example: at the time point Ts, only the input of m2 is changed; at the time point, only the input of M2 is changed; At the time point T11, the input of the finite state machine module M2 maintains the original input. Obviously, the invention may have many modifications and differences of 24 8 1317486 in accordance with the description in the above embodiments. The shame needs to be understood within the scope of its additional paste requirements, and the present invention can be widely practiced in other embodiments in addition to the detailed and detailed description above. The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the invention. Any equivalent changes or modifications made by the spirit of the present invention should include the following. The towel is within the scope of the patent. [Simplified Schematic] The first A picture is a conventional sequential logic decomposition (SLD) cutting architecture of the finite state machine circuit; the first B picture is a conventional combinational logic decomposition of the finite state machine circuit ( The cut-off architecture of the combinational logic decomposition; CLD); the second diagram is a schematic system block diagram of a preferred embodiment of the present invention; the third diagram is a state transition diagram of a finite state machine (state Du Jie 8 out 11 graph; The fourth diagram is a preferred decomposition architecture diagram of the embodiment of the present invention according to the third embodiment; the fifth diagram is the signal implemented by the conventional combination logic decomposition scheme. Waveform diagram

25 1317486 Figure 5B is a signal waveform diagram of the embodiment of the third figure implemented by the decomposition architecture of the fourth figure; and the embodiment of the third figure of the sixth figure is implemented by the decomposition structure of the fourth figure and implemented with different inputs. Signal waveform diagram.

[Description of main component symbols] 110 finite state machine circuit 120 selection module 130 temporary storage module 140 decoding module 150 storage module 160 buffer module 102 second input signal 104 first input signal and first state signal 112, 132 Second state signal 114 first select signal 116, 122 output signal 124 second state signal and first select signal 134 second select signal 142 third select signal 162 delay clock 26

Claims (1)

1317486 X. Patent application scope: 1. A decomposition architecture of a finite state machine circuit, comprising: a plurality of finite state machine modules, corresponding to receiving a plurality of first state signals and a first wheeling signal, and corresponding outputs a plurality of second state signals, a plurality of rounding signals, and a plurality of first selection signals; the selecting module receiving the plurality of second state signals, the plurality of output signals, the plurality of first selection signals, and a first a selection signal, the selection module selects one of the plurality of second state signals according to the second selection signal, and one of the plurality of output signals and one of the plurality of first selection signals are rotated; The storage module receives the second status signal outputted by the selection module and the first selection signal and temporarily stores the second status signal and the second selection signal; a decoding module receives the second selection Signaling and decoding a third selection signal; and a storage module receiving a second input signal, the second status signal, and the third selection signal And outputting the plurality of first state signals and the first wheeling signal, wherein the storage module replaces the first input signal with the second input signal, and replaces the third selection signal with the second state signal The first state signal is selected. 2. According to the decomposition architecture of the finite state machine circuit of claim 1, further comprising a buffer module, wherein the buffer module is configured to enable the second state signal and the third selection signal to be simultaneously output to the storage Module. 3. A decomposition architecture of a finite state machine circuit, comprising: 27 Φ: 1317486 two finite state touch modules, corresponding to receiving two first state signals and a first input signal, and correspondingly outputting two second state signals, Two output signals and two first selection signals; a plurality of multiplexers corresponding to receiving the two second state signals, the two output signals, the two first-select signals and the second selection signal Selecting one of the two second state signals, one of the two output signals, and one of the two first selection signals according to the second selection signal; the plurality of flip-flops corresponding to receiving the plurality of multi-guards Transducing the second state signal and the first selection signal, and temporarily storing the second state signal and the second selection signal; the decoder receiving the second selection signal, and decoding and outputting a third selection signal; The plurality of storage devices are configured to receive the second input signal, the second status signal and the second selection signal, and output the two first status signals and the first input signal, The plurality of storage devices replace the first round-in signal with the second input signal, and replace the first state signal selected by the third selection signal with the second state signal; and a buffer module is used The second state signal and the third selection signal can be simultaneously rotated to the plurality of storage devices. 4. The decomposition architecture of a finite state machine circuit according to claim 3, wherein the first input signal comprises an i-bit data, i > and i is a natural number. 5. According to the decomposition architecture of the finite state machine circuit of claim 3, wherein the 28 1317486 rain/state signal system respectively contains a j-bit data 'j > 〇 and j is a natural number. 6 The decomposition architecture of the finite state machine circuit according to claim 3, wherein the two second state signals respectively comprise a j-bit data, j > and j is a natural number. 7) The decomposition architecture of the finite state machine circuit according to item 3 of the patent application scope, wherein the two rounds of signal signals respectively comprise a q-bit data, qM and q are natural numbers. 8' is a decomposition architecture of a finite state machine circuit according to claim 3, wherein the sin-selection signal system comprises a k-bit data 'k > 〇 and k is a natural number. The decomposition architecture of the finite state machine circuit of claim 3, wherein the second selection signal comprises a k-bit data 'k>0 and k is a natural number. According to the decomposition architecture of the finite state machine circuit of claim 9th, the third selection signal is read to include an r bit data, r = 2k. The decomposition architecture of the finite state machine circuit according to item 3 of the patent application scope, wherein the plurality of storage devices are of a type comprising a latch. Lu 12. According to the decomposition structure of the finite state machine circuit of claim 3, wherein the type of reading a plurality of storage devices comprises a memory. According to the decomposition architecture of the finite state machine circuit of claim 3, wherein the second round-in signal includes an i-bit data, i > 0 and i is a natural number. 29 eg