JP6041928B2 - メモリ装置電源管理装置 - Google Patents
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
- G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
- G06F1/3215—Monitoring of peripheral devices
- G06F1/3225—Monitoring of peripheral devices of memory devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3275—Power saving in memory, e.g. RAM, cache
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Quality & Reliability (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Dram (AREA)
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- Semiconductor Memories (AREA)
Description
本発明に記載される様々な実施形態は、半導体メモリに関連する装置、システム、及び方法に関する。
されたスイッチ回路とを含む、ロジックダイとを備え、前記複数のメモリ保管庫コントローラの各々は、前記パケット命令に応じて対応するメモリ保管庫の動作を制御すると共に、前記動作レベルのモニター結果に応じて、対応するメモリ保管庫の電力状態を調整する、ことを特徴とするものである。
M)、静的ランダムアクセスメモリ(SRAM)、フラッシュメモリ等を含んでもよい。
からMVC106に到達するデータをバッファ処理するために、書き込みバッファ316が、PVCL310に結合される場合がある。MVC106は、読み出しバッファ317を更に含んでもよい。対応するメモリ保管庫110からMVC106に到達するデータをバッファ処理するために、読み出しバッファ317が、PVCL310に結合される場合がある。
ローラを利用して、メモリアレイのスタック内で個別のメモリ部分を制御する。上述されたように、メモリ部分の実施例としては、保管庫、ダイ、タイル等が挙げられる。
を落とす場合、それに関連する保管庫230の電源を落とす。同様に、プロセッサ又はプロセッサコアの電源をより高レベルにする場合は、それに関連する保管庫又は他のメモリ部分の電源が、より高い状態にされる。
102 メモリ保管庫
104、106 メモリ保管庫コントローラ(MVC)
110 メモリ保管庫
112、113、115 シリアル通信リンクインターフェース(SCLI)
114 ホストプロセッサ
116 スイッチ
117 メモリ構成制御レジスタ
138 デマルチプレクサ
200 積層ダイ3次元メモリアレイ
202 ロジックダイ
203 メモリアレイ
204 ダイ
205A、205B、205C タイル
208 タイル
212B、212C、212D タイル
224 導電経路
230 メモリ保管庫
240 メモリアレイ
310 プログラム可能な保管庫制御ロジック(PVCL)
314 メモリシーケンサ
315 メモリマップ
316 書き込みバッファ
317 読み出しバッファ
318 要求列
324 メモリマップロジック(MML)
326 動作追跡装置
328 TWI修復ロジック
500 情報処理システム
502 システムバス
504 チップ組立部品
506 メモリ装置
508 プロセッサ
509 表示装置
510 周辺部品
512 ハードドライブ
514 キーボード/コントローラ
Claims (12)
- 互いに積層されて積層ダイ3次元メモリアレイを形成する複数のメモリアレイダイであって、当該複数のメモリアレイダイの各々は、複数のメモリアレイタイルを含み、当該複数のメモリアレイタイルは、各々が、互いに異なる当該メモリアレイダイに形成された複数個の前記メモリアレイタイルを含む、複数のメモリ保管庫を形成する、複数のメモリアレイダイと、
前記積層ダイ3次元メモリアレイと共に積層されるロジックダイであって、前記複数のメモリ保管庫に対応して設けられた複数のメモリ保管庫コントローラと、前記複数のメモリ保管庫の少なくとも一部の動作レベルをモニターする少なくとも1つの動作追跡装置と、各々が、外部から供給されるパケット命令を受け取る複数のシリアル通信リンクインターフェースと、前記複数のシリアル通信リンクインターフェースと前記複数のメモリ保管庫コントローラとの間に接続されたスイッチ回路とを含む、ロジックダイとを備え、
前記複数のメモリ保管庫コントローラの各々は、前記パケット命令に応じて対応するメモリ保管庫の動作を制御すると共に、前記動作レベルのモニター結果に応じて、対応するメモリ保管庫の電力状態を調整する、ことを特徴とする装置。 - 前記複数のメモリ保管庫のそれぞれは、前記複数のメモリアレイダイの積層方向に1列に並んだ複数のメモリアレイタイルを含むことを特徴とする請求項1に記載の装置。
- 前記スイッチ回路は、前記複数のシリアル通信リンクインターフェースのそれぞれを、前記メモリ保管庫コントローラの1つに選択的に接続することを特徴とする請求項1又は2に記載の装置。
- 前記複数のメモリタイルの各々が、複数のメモリバンクを含むことを特徴とする請求項1乃至3のいずれか一項に記載の装置。
- 前記複数のメモリ保管庫コントローラの各々が、メモリシーケンサを含み、当該メモリシーケンサは、前記対応するメモリ保管庫の動作を制御するために、命令復号操作、メモリアドレス多重化操作、メモリアドレス逆多重化操作、メモリリフレッシュ操作、及び、メモリ保管庫事前読み出し操作の少なくとも1つを実行することを特徴とする請求項1乃至3のいずれか一項に記載の装置。
- 前記複数のメモリ保管庫コントローラは、前記複数のメモリ保管庫の動作を互いに独立に制御することを特徴とする請求項1乃至4のいずれか一項に記載の装置。
- 各々、前記複数のシリアル通信リンクインターフェースに対応して設けられ、対応する前記複数のシリアルリンク通信インターフェースと前記スイッチ回路との間に接続された複数のパケットデコーダを含むことを特徴とする請求項1乃至6のいずれか一項に記載の装置。
- 前記ロジックダイが、複数の前記動作追跡装置を含み、当該複数の動作追跡装置のそれぞれは、対応するメモリ保管庫コントローラに形成されると共に、当該対応するメモリ保管庫コントローラに対応する前記メモリ保管庫の動作レベルをモニターすることを特徴とする請求項1乃至7のいずれか一項に記載の装置。
- 前記複数のメモリ保管庫コントローラの各々は、前記動作レベルのモニター結果に応じて、自身及び前記対応するメモリ保管庫の電力状態をオフ状態とすることを特徴とする請求項1乃至8のいずれか一項に記載の装置。
- 前記複数のメモリ保管庫コントローラの各々は、前記動作レベルのモニター結果に応じて、前記対応するメモリ保管庫のリフレッシュ速度を変更することを特徴とする請求項1乃至8のいずれか一項に記載の装置。
- 前記ロジックダイが、前記複数のシリアル通信リンクインターフェースの1又は複数の電力状態を変更することを特徴とする請求項1乃至10のいずれか一項に記載の装置。
- 前記少なくとも1つの動作追跡装置が、前記複数のメモリ保管庫の少なくとも一部の動作レベルが所定の期間よりも長いか否かを検出して、前記動作レベルのモニター結果を生成することを特徴とする請求項1に記載の装置。
Applications Claiming Priority (2)
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US12/359,039 US9105323B2 (en) | 2009-01-23 | 2009-01-23 | Memory device power managers and methods |
US12/359,039 | 2009-01-23 |
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JP2011548138A Division JP5762312B2 (ja) | 2009-01-23 | 2010-01-22 | メモリ装置電源管理装置及び方法 |
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JP6041928B2 true JP6041928B2 (ja) | 2016-12-14 |
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JP2015095403A Active JP6041928B2 (ja) | 2009-01-23 | 2015-05-08 | メモリ装置電源管理装置 |
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US (2) | US9105323B2 (ja) |
EP (2) | EP3223281B1 (ja) |
JP (2) | JP5762312B2 (ja) |
KR (1) | KR101609311B1 (ja) |
CN (2) | CN104699226B (ja) |
TW (3) | TWI590255B (ja) |
WO (1) | WO2010085657A2 (ja) |
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US9583157B2 (en) | 2017-02-28 |
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