JP5957984B2 - Manufacturing method of semiconductor light emitting device - Google Patents

Manufacturing method of semiconductor light emitting device Download PDF

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JP5957984B2
JP5957984B2 JP2012054760A JP2012054760A JP5957984B2 JP 5957984 B2 JP5957984 B2 JP 5957984B2 JP 2012054760 A JP2012054760 A JP 2012054760A JP 2012054760 A JP2012054760 A JP 2012054760A JP 5957984 B2 JP5957984 B2 JP 5957984B2
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弘 満山
弘 満山
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Mitsubishi Electric Corp
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Description

本発明は、GaAs基板を割ることで形成される半導体発光素子の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor light emitting device formed by splitting a GaAs substrate.

近年、レーザダイオードや発光ダイオードに代表される半導体発光素子には、高出力、高効率、高信頼性が求められている。これらの要求を満たすためには素子の開発・設計段階での品質の作り込みが必要である。特に高出力の素子は電流及び光による負荷が大きいため結晶欠陥の増殖が早い。従って、信頼性を確保するためには、結晶欠陥を従来以上に減らす技術、結晶欠陥を無効化する技術が必要不可欠である。   In recent years, semiconductor light emitting devices represented by laser diodes and light emitting diodes are required to have high output, high efficiency, and high reliability. In order to satisfy these requirements, it is necessary to build quality in the development and design stages of the device. In particular, a high-power element has a large load due to current and light, so that crystal defects grow quickly. Therefore, in order to ensure reliability, a technique for reducing crystal defects more than before and a technique for invalidating crystal defects are indispensable.

半導体発光素子の製造工程には、基板を素子単位に分割する工程がある。この工程では、基板に分割用の溝を入れ(スクライブ)、この溝に沿って刃を当て加重を加えることで基板を割る(ブレイク)。この際に結晶を機械的に割るため破断面には大小さまざまなクラックが必然的に発生し、これらが元となって結晶欠陥が発生する。なお、結晶欠陥が素子領域に伝達するのを防ぐため、ダイシングラインの近傍に酸化膜などで充填した溝を形成することが提案されている(例えば、特許文献1参照)。   The manufacturing process of the semiconductor light emitting device includes a step of dividing the substrate into device units. In this step, a dividing groove is put in the substrate (scribing), and a blade is applied along the groove to apply a load to break the substrate (break). At this time, since the crystal is mechanically broken, various cracks are inevitably generated on the fracture surface, and crystal defects are generated based on these cracks. In order to prevent the crystal defect from being transmitted to the element region, it has been proposed to form a groove filled with an oxide film or the like in the vicinity of the dicing line (see, for example, Patent Document 1).

特開平4−251960号公報JP-A-4-251960

分割部分の結晶欠陥は、素子へ印加される電流や素子から発せられる光のエネルギーを受けて増殖するため、特に素子を高出力で動作させると欠陥の増殖速度も上がることになり、素子の信頼性を著しく低下させるという問題がある。また、ダイシングラインの近傍に溝を形成するとチップサイズが増大する。また、GaAs系の場合には物質の性質上良質な熱酸化膜を形成できない。   The crystal defects in the divided parts proliferate in response to the current applied to the element and the energy of light emitted from the element. Therefore, when the element is operated at a high output, the defect propagation rate increases, and the reliability of the element increases. There is a problem of significantly reducing the performance. Further, if a groove is formed in the vicinity of the dicing line, the chip size increases. In the case of GaAs, a high quality thermal oxide film cannot be formed due to the nature of the substance.

本発明は、上述のような課題を解決するためになされたもので、その目的はGaAs基板を割る際に発生する結晶欠陥が発光層に影響を与えないようにすることができる半導体発光素子の製造方法を得るものである。
The present invention has been made in order to solve the above-described problems, and an object of the present invention is to provide a semiconductor light emitting device capable of preventing a crystal defect generated when a GaAs substrate is broken from affecting a light emitting layer . A manufacturing method is obtained.

本発明に係る半導体発光素子の製造方法は、GaAs基板上に、発光層を有する半導体積層構造を形成する工程と、前記半導体積層構造に溝を形成する工程と、前記溝内で露出した前記発光層の一部を選択的にエッチングする工程と、前記発光層の一部を選択的にエッチングした後に、前記溝に沿って前記GaAs基板を割る工程とを備えることを特徴とする。   The method of manufacturing a semiconductor light emitting device according to the present invention includes a step of forming a semiconductor multilayer structure having a light emitting layer on a GaAs substrate, a step of forming a groove in the semiconductor multilayer structure, and the light emission exposed in the groove. A step of selectively etching a part of the layer; and a step of selectively etching the part of the light emitting layer and then splitting the GaAs substrate along the groove.

本発明により、GaAs基板を割る際に発生する結晶欠陥が発光層に影響を与えないようにすることができる。   According to the present invention, crystal defects generated when a GaAs substrate is broken can be prevented from affecting the light emitting layer.

本発明の実施の形態1に係る半導体発光素子の製造工程の断面図である。It is sectional drawing of the manufacturing process of the semiconductor light-emitting device based on Embodiment 1 of this invention. 本発明の実施の形態2に係る半導体発光素子の製造工程の断面図である。It is sectional drawing of the manufacturing process of the semiconductor light-emitting device based on Embodiment 2 of this invention. 本発明の実施の形態2に係る半導体発光素子の製造工程の断面図である。It is sectional drawing of the manufacturing process of the semiconductor light-emitting device based on Embodiment 2 of this invention. 本発明の実施の形態2に係る半導体発光素子の製造工程の断面図である。It is sectional drawing of the manufacturing process of the semiconductor light-emitting device based on Embodiment 2 of this invention. 本発明の実施の形態3に係る半導体発光素子の製造工程の断面図である。It is sectional drawing of the manufacturing process of the semiconductor light-emitting device based on Embodiment 3 of this invention. 本発明の実施の形態4に係る半導体発光素子の製造工程の断面図である。It is sectional drawing of the manufacturing process of the semiconductor light-emitting device based on Embodiment 4 of this invention. 本発明の実施の形態5に係る半導体発光素子の製造工程の断面図である。It is sectional drawing of the manufacturing process of the semiconductor light-emitting device based on Embodiment 5 of this invention.

本発明の実施の形態に係る半導体発光素子及びその製造方法について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。   A semiconductor light emitting device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

実施の形態1.
図1は、本発明の実施の形態1に係る半導体発光素子の製造工程の断面図である。まず、n型GaAs基板1上に、n型クラッド層2、発光層3、及びp型クラッド層4が積層された半導体積層構造5を形成する。次に、半導体積層構造5に溝6を形成する。
Embodiment 1 FIG.
FIG. 1 is a cross-sectional view of the manufacturing process of the semiconductor light emitting element according to Embodiment 1 of the present invention. First, a semiconductor laminated structure 5 in which an n-type cladding layer 2, a light emitting layer 3, and a p-type cladding layer 4 are laminated on an n-type GaAs substrate 1 is formed. Next, the groove 6 is formed in the semiconductor multilayer structure 5.

次に、発光層3の材質のみをエッチングする液を用いて、溝6内で露出した発光層3の一部を選択的にエッチングする。例えば発光層3がGaAs、クラッド層2,4がAlGaInPの場合、硫酸と過酸化水素水と純水の混合液を用いることで、発光層3のGaAsのみを選択的にエッチングすることができる。   Next, a part of the light emitting layer 3 exposed in the groove 6 is selectively etched using a liquid for etching only the material of the light emitting layer 3. For example, when the light emitting layer 3 is GaAs and the cladding layers 2 and 4 are AlGaInP, only GaAs of the light emitting layer 3 can be selectively etched by using a mixed solution of sulfuric acid, hydrogen peroxide solution and pure water.

次に、半導体積層構造5上に電極7を形成し、n型GaAs基板1の裏面に電極8を形成する。その後に、溝6に沿ってn型GaAs基板1を割る。こうして製造された素子では、n型GaAs基板1は分割部分9で割られ、分割部分9において発光層3の一部が半導体積層構造5の側面から内側に奥まっている。   Next, an electrode 7 is formed on the semiconductor multilayer structure 5, and an electrode 8 is formed on the back surface of the n-type GaAs substrate 1. Thereafter, the n-type GaAs substrate 1 is split along the groove 6. In the device manufactured in this way, the n-type GaAs substrate 1 is divided by the divided portion 9, and a part of the light emitting layer 3 is recessed inward from the side surface of the semiconductor multilayer structure 5 in the divided portion 9.

上記の構成によって、仮にn型GaAs基板1が大きく曲がって割れ、分割境界10が溝6より内側に入ったとしても、発光層3に分割境界10がかかって結晶欠陥が発生するのを防ぐことができる。よって、n型GaAs基板1を割る際に発生する結晶欠陥が発光層3に影響を与えないようにすることができる。この結果、高出力、高効率、高信頼性を実現することができる。   With the above configuration, even if the n-type GaAs substrate 1 is bent and cracked greatly and the dividing boundary 10 enters inside the groove 6, the dividing boundary 10 is applied to the light emitting layer 3 to prevent crystal defects from occurring. Can do. Therefore, it is possible to prevent crystal defects generated when the n-type GaAs substrate 1 is broken from affecting the light emitting layer 3. As a result, high output, high efficiency, and high reliability can be realized.

実施の形態2.
図2〜図4は、本発明の実施の形態2に係る半導体発光素子の製造工程の断面図である。まず、図2に示すように、n型GaAs基板1上に、発光層3を有する半導体積層構造5を形成する。次に、亜鉛などの不純物拡散により発光層3のバンドギャップを広げた窓領域11を形成する。窓領域11は発光層3より深く形成する。
Embodiment 2. FIG.
2-4 is sectional drawing of the manufacturing process of the semiconductor light-emitting device based on Embodiment 2 of this invention. First, as shown in FIG. 2, a semiconductor multilayer structure 5 having a light emitting layer 3 is formed on an n-type GaAs substrate 1. Next, a window region 11 in which the band gap of the light emitting layer 3 is widened by diffusion of impurities such as zinc is formed. The window region 11 is formed deeper than the light emitting layer 3.

次に、図3に示すように、プロトンなどのイオン注入により半導体積層構造5に高抵抗領域12を形成する。半導体積層構造5上に電極7を形成し、n型GaAs基板1の裏面に電極8を形成する。   Next, as shown in FIG. 3, a high resistance region 12 is formed in the semiconductor multilayer structure 5 by ion implantation of protons or the like. An electrode 7 is formed on the semiconductor multilayer structure 5, and an electrode 8 is formed on the back surface of the n-type GaAs substrate 1.

次に、図4に示すように、窓領域11及び高抵抗領域12内又はそれらの近傍において半導体積層構造5に溝6を形成する。次に、溝6に沿ってn型GaAs基板1を割る。こうして製造された素子では、分割部分9の近傍において半導体積層構造5に窓領域11と高抵抗領域12が設けられている。   Next, as shown in FIG. 4, the groove 6 is formed in the semiconductor multilayer structure 5 in or near the window region 11 and the high resistance region 12. Next, the n-type GaAs substrate 1 is divided along the groove 6. In the element manufactured in this way, the window region 11 and the high resistance region 12 are provided in the semiconductor multilayer structure 5 in the vicinity of the divided portion 9.

上記の構成によって、窓領域11の発光層3は周辺の発光層3から染み出してくる光を吸収しない。また、高抵抗領域12により分割部分9の近傍に電流が流れない。従って、分割部分9の近傍において光と電流の両方のエネルギーを遮断することができる。   With the above configuration, the light emitting layer 3 in the window region 11 does not absorb the light that oozes out from the peripheral light emitting layer 3. Further, no current flows in the vicinity of the divided portion 9 due to the high resistance region 12. Therefore, the energy of both light and current can be blocked in the vicinity of the divided portion 9.

これにより、仮にn型GaAs基板1が大きく曲がって割れ、分割境界10が溝6より内側に入り発光層3に結晶欠陥13が生成されたとしても、光および電流のエネルギーが加わらないため、結晶欠陥13の成長を止める又は遅らせることができる。よって、n型GaAs基板1を割る際に発生する結晶欠陥13が発光層3に影響を与えないようにすることができる。この結果、高出力、高効率、高信頼性を実現することができる。   As a result, even if the n-type GaAs substrate 1 is bent and cracked, and even if the dividing boundary 10 enters inside the groove 6 and the crystal defect 13 is generated in the light emitting layer 3, energy of light and current is not applied. The growth of the defect 13 can be stopped or delayed. Therefore, it is possible to prevent the crystal defect 13 generated when the n-type GaAs substrate 1 is broken from affecting the light emitting layer 3. As a result, high output, high efficiency, and high reliability can be realized.

実施の形態3.
図5は、本発明の実施の形態3に係る半導体発光素子の製造工程の断面図である。まず、n型GaAs基板1上に、発光層3を有する半導体積層構造5を形成する。次に、不純物拡散により発光層3のバンドギャップを広げた窓領域11を形成する。
Embodiment 3 FIG.
FIG. 5 is a cross-sectional view of the manufacturing process of the semiconductor light emitting element according to Embodiment 3 of the present invention. First, a semiconductor multilayer structure 5 having a light emitting layer 3 is formed on an n-type GaAs substrate 1. Next, a window region 11 in which the band gap of the light emitting layer 3 is widened by impurity diffusion is formed.

次に、半導体積層構造5上の一部に電極7を形成し、n型GaAs基板1の裏面に電極8を形成する。次に、窓領域11内又はその近傍において半導体積層構造5に溝6を形成する。ただし、電極7が溝6の近傍には存在しないようにする。次に、溝6に沿ってn型GaAs基板1を割る。   Next, an electrode 7 is formed on a part of the semiconductor multilayer structure 5, and an electrode 8 is formed on the back surface of the n-type GaAs substrate 1. Next, a groove 6 is formed in the semiconductor multilayer structure 5 in or near the window region 11. However, the electrode 7 should not be present in the vicinity of the groove 6. Next, the n-type GaAs substrate 1 is divided along the groove 6.

こうして製造された素子では、分割部分9の近傍に窓領域11が設けられ、半導体積層構造5上に設けられた電極7が分割部分9の近傍には存在しない。このように電極7が分割部分9の近傍には存在しないことで、分割部分9の近傍に電流が流れない。従って、実施の形態2と同様の効果を得ることができる。   In the element thus manufactured, the window region 11 is provided in the vicinity of the divided portion 9, and the electrode 7 provided on the semiconductor multilayer structure 5 does not exist in the vicinity of the divided portion 9. As described above, since the electrode 7 does not exist in the vicinity of the divided portion 9, no current flows in the vicinity of the divided portion 9. Therefore, the same effect as in the second embodiment can be obtained.

実施の形態4.
図6は、本発明の実施の形態4に係る半導体発光素子の製造工程の断面図である。実施の形態2と同様に窓領域11及び高抵抗領域12を形成し、かつ実施の形態1と同様に溝6内で露出した発光層3の一部を選択的にエッチングする。これにより、実施の形態1と実施の形態2の両方の効果を得ることができる。
Embodiment 4 FIG.
FIG. 6 is a cross-sectional view of the manufacturing process of the semiconductor light emitting element according to Embodiment 4 of the present invention. The window region 11 and the high resistance region 12 are formed as in the second embodiment, and a part of the light emitting layer 3 exposed in the groove 6 is selectively etched as in the first embodiment. Thereby, the effect of both Embodiment 1 and Embodiment 2 can be acquired.

実施の形態5.
図7は、本発明の実施の形態5に係る半導体発光素子の製造工程の断面図である。実施の形態3と同様に窓領域11を形成し、電極7が分割部分9の近傍に存在しないようにし、かつ実施の形態1と同様に溝6内で露出した発光層3の一部を選択的にエッチングする。これにより、実施の形態1と実施の形態3の両方の効果を得ることができる。
Embodiment 5 FIG.
FIG. 7 is a cross-sectional view of the manufacturing process of the semiconductor light emitting device according to the fifth embodiment of the present invention. The window region 11 is formed as in the third embodiment, the electrode 7 is not present in the vicinity of the divided portion 9, and a part of the light emitting layer 3 exposed in the groove 6 is selected as in the first embodiment. Etch. Thereby, the effect of both Embodiment 1 and Embodiment 3 can be acquired.

1 n型GaAs基板
3 発光層
5 半導体積層構造
6 溝
7 電極
9 分割部分
11 窓領域
12 高抵抗領域
1 n-type GaAs substrate 3 light emitting layer 5 semiconductor laminated structure 6 groove 7 electrode 9 divided portion 11 window region 12 high resistance region

Claims (3)

GaAs基板上に、発光層を有する半導体積層構造を形成する工程と、
前記半導体積層構造に溝を形成する工程と、
前記溝内で露出した前記発光層の一部を選択的にエッチングする工程と、
前記発光層の一部を選択的にエッチングした後に、前記溝に沿って前記GaAs基板を割る工程とを備えることを特徴とする半導体発光素子の製造方法。
Forming a semiconductor multilayer structure having a light emitting layer on a GaAs substrate;
Forming a groove in the semiconductor multilayer structure;
Selectively etching a part of the light emitting layer exposed in the groove;
And a step of selectively etching a part of the light emitting layer and then splitting the GaAs substrate along the groove.
不純物拡散により前記発光層のバンドギャップを広げた窓領域を形成する工程と、
イオン注入により前記半導体積層構造に高抵抗領域を形成する工程とを更に備え、
前記窓領域及び前記高抵抗領域内又はそれらの近傍に前記溝を形成することを特徴とする請求項1に記載の半導体発光素子の製造方法。
Forming a window region in which the band gap of the light emitting layer is widened by impurity diffusion;
A step of forming a high resistance region in the semiconductor multilayer structure by ion implantation,
The method for manufacturing a semiconductor light emitting element according to claim 1, wherein the groove is formed in or near the window region and the high resistance region.
不純物拡散により前記発光層のバンドギャップを広げた窓領域を形成する工程と、
前記半導体積層構造上の一部に電極を形成する工程とを更に備え、
前記窓領域内又はそれらの近傍に前記溝を形成し、
前記電極が前記溝の近傍には存在しないようにすることを特徴とする請求項1に記載の半導体発光素子の製造方法。
Forming a window region in which the band gap of the light emitting layer is widened by impurity diffusion;
Forming an electrode on a part of the semiconductor multilayer structure,
Forming the groove in or near the window region;
Producing how the semiconductor light-emitting device according to claim 1, wherein the electrode is so not present in the vicinity of the groove.
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