JP2006261266A - Semiconductor light emitting device and its manufacturing method, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor light emitting device which can prevent the reduction of luminance due to optical absorption. <P>SOLUTION: The semiconductor light emitting device is provided with a first conductive type first semiconductor layer 3, a light emitting layer 5 to generate a light, a second conductive type second semiconductor layer 8, and a transparent substrate 10 that is transparent for a light emitted from the light emitting layer 5 and of which bottom surface is directly joined with the second semiconductor layer 8, in this order. In the transparent substrate 10, a surface electrode 11 is provided in the partly area of its upper surface 10a. A groove 30 concaved against the outside on the upper surface 10a excluding an area occupied by the surface electrode 11. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor light emitting device and a method for manufacturing the same. Typically, the semiconductor light emitting device of the present invention is used in an electronic device such as an optical communication device, an information display panel, a CCD (Charge Coupled Device) camera auxiliary light source, an LCD (Liquid Crystal Display) backlight, or a lighting device. It is done.

  The present invention also relates to an electronic device including such a semiconductor light emitting element.

  In recent years, LEDs (Light Emitting Diodes), which are semiconductor light emitting elements, have been widely used in electronic devices such as optical communication devices, information display panels, CCD camera auxiliary light sources, LCD backlights, and lighting devices. It is important that the LEDs for these applications have high brightness. In particular, recently, LEDs have begun to be used for lighting equipment, and the need for higher brightness has further increased. One way to obtain high brightness is to increase the efficiency of the LED. The efficiency of the LED is determined by the internal quantum efficiency and the external emission efficiency. Among these, the external emission efficiency is greatly influenced by the element structure.

  In order to improve the external emission efficiency of the LED, there is a means of using a substrate transparent to the emission wavelength. As an AlGaInP (aluminum / gallium / indium / phosphorus) LED, a method for manufacturing an LED having a substrate transparent to the emission wavelength is shown in FIG. -302857)). In this LED manufacturing method, an AlGaInP-based light-emitting layer 102 is epitaxially grown on a GaAs (gallium arsenide) substrate 101 that is opaque with respect to the emission wavelength, and a GaP current diffusion layer 103 is grown thereon by several tens of μm. Subsequently, the GaAs substrate 101 opaque to the emission wavelength is removed, and the GaP substrate 105 is directly bonded to the removed surface by heat treatment. In FIG. 11, 180 indicates direct bonding. Reference numeral 106 denotes a substrate side electrode, and reference numeral 107 denotes a surface electrode.

  In this LED manufacturing method, the AlGaInP-based light emitting layer 102 is not lattice-matched to GaP, so once grown on the GaAs substrate 101, the GaAs substrate 101 is removed and the GaP substrate is bonded. . The thickness of the GaP current diffusion layer 103 grown on the light emitting layer 102 is set to about 50 μm to 100 μm in consideration of the growth time and the mechanical strength of the wafer after the GaAs substrate 101 is removed. When the thickness of the GaP current spreading layer 103 is 50 μm or less, it is very easy to break when handling a wafer, whereas when the thickness is 100 μm or more, the growth time becomes long and the cost of the LED increases. is there.

  However, even if the thickness of the GaP current diffusion layer 103 is 50 μm to 100 μm, the mechanical strength is not sufficient, and the problem that the wafer breaks during handling of the wafer has not been solved.

  In order to solve the above problem, another method for manufacturing an AlGaInP-based LED is shown in FIG. 12 (see Patent Document 2 (Japanese Patent No. 3230638)). In this LED manufacturing method, an AlGaInP-based light emitting layer 112 is epitaxially grown on a GaAs substrate 111 that is opaque to the light emission wavelength, and a GaP layer 113 is formed thereon. Then, a GaP substrate 114 that is transparent to the emission wavelength is disposed on the GaP layer 113 and is directly bonded by performing a heat treatment. Thereafter, the GaAs substrate 111 that is opaque to the emission wavelength is removed. In FIG. 12, 190 indicates direct bonding. Reference numeral 116 denotes a substrate side electrode, and reference numeral 117 denotes a surface electrode.

  Since this LED manufacturing method does not require handling of a wafer having a thickness of 50 μm to 100 μm, it is possible to solve the problem that the wafer breaks during the manufacturing process.

  By the way, another method for obtaining high brightness in the LED is to increase the current injected into the LED. However, when the current injected into the LED is increased, a problem of thermal saturation due to heat generation in the light emitting layer occurs. That is, as the injection current increases, the amount of heat generated in the light emitting layer exceeds the amount of heat released to the outside mainly through the die bond portion, so that the temperature of the light emitting layer rises and carriers overflow, The output is saturated.

  In order to solve this problem, an AlGaInP-based LED as shown in FIG. 13 has been proposed (Non-patent Document 1 (written by Koji Otsuka et al. “Replacement of light-emitting diode fluorescent tube 100 times brighter”). Nikkei Electronics, Nikkei BPP, October 21, 2002, p. 123-131)). In this LED, a Si (silicon) substrate 121 having a thermal conductivity approximately three times higher than that of a conventionally used GaAs substrate is attached to a semiconductor layer 125 including a light emitting layer 124 via a metal layer 122. In this LED, a semiconductor layer 125 is epitaxially grown on a GaAs substrate, a Si substrate 121 is attached via a metal layer 122, and then the GaAs substrate is removed. In FIG. 11, 126 is a substrate side electrode, 127 is a surface electrode, and 128 is a current blocking layer.

Since this LED does not have a relatively large thermal resistance due to the GaAs substrate, it is possible to greatly reduce the heat dissipation loss.
JP-A-6-302857 Japanese Patent No. 3230638 Koji Otsuka et al. “Light-Emitting Diodes 100 times Brighter than Replacing Fluorescent Tubes” Nikkei Electronics, Nikkei Beepee, Inc., October 21, 2002 p. 123-131

  However, the conventional LEDs shown in FIG. 11 to FIG. 13 have a problem that the luminance is reduced due to other causes described below.

  That is, the refractive index of the AlGaInP-based semiconductor material is about 3 to 3.5, while the refractive index of air is 1 and the resin is about 1.5. Therefore, there is a refractive index difference of 2 to 2.5 or 1.5 to 2 between the AlGaInP-based semiconductor layer constituting the LED chip and the surrounding air or resin (referred to as “chip interface”). Each exists. Due to this difference in refractive index, of the light generated in the LED chip, the light incident on the chip interface at an angle greater than the total reflection critical angle is totally reflected. The total reflection critical angle is about 17 ° when entering the air from the AlGaInP-based semiconductor layer and about 25 ° when entering the resin from the AlGaInP-based semiconductor layer.

  Here, in the conventional LED shown in FIGS. 11 and 12 (in which the GaP substrates 105 and 114 are directly joined), the shape of the chip 130 is a substantially rectangular parallelepiped as schematically shown in FIG. Of the light L generated by 131 (indicated by solid arrows), the proportion of light totally reflected at the chip interface 140 is relatively high. Specifically, the light L generated in the light emitting layer 131 is multiply reflected inside the chip, passes through the light emitting layer 131 a plurality of times, and is reflected by the plurality of electrodes 132 and 133. At this time, the light L is gradually absorbed by the light emitting layer 131 and the electrodes 132 and 133 at a plurality of positions A (indicated by broken line ellipses) as illustrated in FIG. Thus, as a result of the light being absorbed at the plurality of positions A, the luminance of the LED is lowered.

  In the conventional LED shown in FIG. 13 (with the Si substrate 121 attached), the thickness of the semiconductor layer 125 (excluding the light emitting layer 124) transparent to the emitted light is equal to the thickness of the entire LED. On the other hand, it is relatively thin. For this reason, the number of times that the light generated in the light emitting layer 124 passes through the light emitting layer 124 by multiple reflection and is reflected by the electrodes 126 and 127 is larger than that of the LED shown in FIGS. Therefore, the amount of absorption in the light emitting layer 124 and the electrodes 126 and 127 increases, and the decrease in the luminance of the LED increases.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor light emitting device capable of preventing a decrease in luminance due to light absorption and a method for manufacturing the same.

  Moreover, the subject of this invention is providing the electronic device provided with such a semiconductor light-emitting device.

In order to solve the above problems, a semiconductor light emitting device of the present invention is
A first conductive type first semiconductor layer, a light emitting layer for generating light, a second conductive type second semiconductor layer, and transparent to light from the light emitting layer, and in the second semiconductor layer A transparent substrate with the surfaces of 1 directly joined, in order,
The transparent substrate is provided with a surface electrode in a partial region of the second surface opposite to the first surface, and outside the region of the second surface other than the region occupied by the surface electrode. On the other hand, a recessed groove is provided.

  Here, the “outside” means the outside of the semiconductor light emitting element. Air or resin is usually present outside the semiconductor light emitting device.

  The first surface and the second surface of the transparent substrate are two surfaces facing each other.

  In the semiconductor light emitting device of the present invention, out of the light generated in the light emitting layer, if there is no groove, the light totally reflected by the second surface of the transparent substrate is emitted to the outside through the inner surface of the groove. be able to. That is, the external reflection efficiency can be increased by reducing the multiple reflection inside the element as compared with the conventional case. Therefore, the brightness of the semiconductor light emitting element can be increased.

  The semiconductor light emitting device of one embodiment takes the form of a substantially rectangular parallelepiped chip, and the groove forms an angle of substantially 45 ° with respect to the chip side surface along the second surface. It is characterized by extending.

  In the semiconductor light emitting device of this embodiment, the angle formed by the groove with respect to the side surface of the chip can further reduce the multiple reflection inside the device and increase the external emission efficiency. In addition, at the manufacturing stage of manufacturing a plurality of semiconductor light emitting elements on a wafer, a similar groove is formed over all the semiconductor light emitting elements on the wafer by forming, for example, a plurality of grooves side by side with a constant pitch using a dicing blade. can do. Therefore, this semiconductor light emitting device is easily manufactured.

  The semiconductor light-emitting device according to one embodiment is characterized in that the number of grooves is four or more per chip.

  In the semiconductor light emitting device of this embodiment, since the number of the grooves is four or more per chip, the multiple reflection inside the device can be further reduced, and the external emission efficiency can be increased.

  Further, it is desirable to set the number of the grooves to a multiple of four. If the number of the grooves is set to a multiple of 4, the same groove is formed over all the semiconductor light emitting elements on the wafer by using, for example, a dicing blade in the manufacturing stage of manufacturing a plurality of semiconductor light emitting elements on the wafer. (Details will be described later).

  The semiconductor light emitting device of one embodiment is characterized in that the depth of the groove is 50 μm or more.

  In the semiconductor light emitting device of this embodiment, since the depth of the groove is 50 μm or more, the side area of the groove can be increased. Therefore, it is possible to further reduce the multiple reflection inside the element and increase the external emission efficiency.

  In one embodiment, the semiconductor light emitting device is injected into a light emitting layer portion opposite to a region surrounded by two adjacent side surfaces of the chip and the groove other than the region occupied by the surface electrode in the second surface. It has a structure for concentrating current.

  Here, the “light emitting layer portion” means a part of the light emitting layer.

  In the semiconductor light-emitting device according to this embodiment, during operation, the semiconductor light-emitting device has a structure other than a region occupied by the surface electrode in the second surface and a region surrounded by two adjacent chip side surfaces and the groove. The injection current is concentrated on the opposing light emitting layer portions. Since the light emitting layer portion is in a region opposite to the surface electrode with respect to the groove in plan view, most of the light generated in the light emitting layer portion is formed on the inner surface of the groove before reaching the surface electrode. Through to the outside. Therefore, it is possible to further reduce the multiple reflection inside the element and increase the external emission efficiency.

In the semiconductor light emitting device of one embodiment,
Each of the grooves extends along the second surface substantially parallel to the corresponding chip side surface;
A structure in which the injection current is concentrated on a light emitting layer portion facing the region sandwiched between the chip side surface and the groove corresponding to the chip side surface other than the region occupied by the surface electrode in the second surface. It is characterized by having.

  In the semiconductor light emitting device of this embodiment, during operation, the structure is sandwiched between the chip side surface and the groove corresponding to the chip side surface, except for the region occupied by the surface electrode in the second surface. The injected current is concentrated on the light emitting layer portion facing the region. Since the light emitting layer portion is in a region opposite to the surface electrode with respect to the groove in plan view, most of the light generated in the light emitting layer portion is formed on the inner surface of the groove before reaching the surface electrode. Through to the outside. Therefore, it is possible to further reduce the multiple reflection inside the element and increase the external emission efficiency.

In the semiconductor light-emitting device of one embodiment, the light emitting layer was formed by _{(Al y Ga 1-y)} z In 1-z P ( provided that 0 ≦ y ≦ 1,0 <z < 1.) It has at least one layer.

  In the semiconductor light emitting device of this embodiment, light from red to green can be emitted with high luminance thanks to the composition of the light emitting layer.

  The semiconductor light emitting device of one embodiment is characterized in that the transparent substrate is made of GaP.

  In the semiconductor light emitting device of this embodiment, light from red to green can be emitted with high luminance thanks to the composition of the light emitting layer.

In another aspect, the present invention is a method for manufacturing a semiconductor light emitting device for manufacturing the semiconductor light emitting device according to claim 1,
The first semiconductor layer, the light emitting layer, and the second semiconductor layer are sequentially stacked on the sacrificial substrate,
Directly bonding the first surface of the transparent substrate to the second semiconductor layer;
Removing the sacrificial substrate,
The surface electrode is provided in a partial region of the second surface opposite to the first surface of the transparent substrate,
A groove that is recessed with respect to the outside is provided in a region other than the region occupied by the surface electrode in the second surface of the transparent substrate using a dicing blade.

  According to the method for manufacturing a semiconductor light emitting device of the present invention, since the groove is formed using a dicing blade, the groove can be formed easily. Moreover, since each semiconductor layer is supported by the sacrificial substrate or the transparent substrate in the manufacturing process, the wafer is not broken. Therefore, the semiconductor light emitting device is easily manufactured.

  The electronic device according to the present invention is an electronic device including the semiconductor light emitting element, wherein the first semiconductor layer side opposite to the transparent substrate of the semiconductor light emitting element is die bonded to a die bond surface having heat conductivity. It is characterized by being.

  In the electronic device according to the present invention, since the thickness of the first semiconductor layer can be set thinner than that of the substrate, the light emitting layer and the die bond surface are very close to each other. Therefore, the heat generated by the light emitting layer during operation is efficiently dissipated through the first semiconductor layer and the die bond surface. As a result, the injection current can be increased. Therefore, high luminance is obtained in combination with the high external emission efficiency of the semiconductor light emitting device.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

(First embodiment)
1A, 1B, and 1C are a side sectional view, a plan view, and a bottom view, respectively, showing an LED 20 as a semiconductor light emitting device according to a first embodiment of the present invention. 1A corresponds to a cross section taken along line AA in FIG. 1B. The LED 20 takes the form of a chip having a substantially rectangular parallelepiped shape.

As shown in FIG. 1A, the LED 20 includes an n-type Al _0.5 Ga _0.5 As current diffusion layer 3 as a first semiconductor layer, an n-type Al _0.5 In _0.5 P cladding layer 4, a quantum well active layer 5 as a light emitting layer, p-type Al _0.5 In _0.5 P cladding layer 6, p-type (Al _0.2 Ga _0.8 ) _0.77 In _0.23 P intermediate layer 7, p-type Ga _0.915 In _0.085 P-attached contact layer 8 as the second semiconductor layer, and transparent substrate A p-type GaP substrate 10 is sequentially provided. The quantum well active layer 5 is configured by alternately laminating a plurality of barrier layers made of (Al _0.5 Ga _0.5 ) _0.5 In _0.5 P and well layers made of GaInP. The GaP substrate 10 is directly bonded to the contact layer 8 (80 indicates a direct bonding interface). As shown in FIG. 1B, a circular bonding pad 11 made of AuBe / Au as a surface electrode is formed in the central region of the upper surface 10a of the p-type GaP substrate 10. On the other hand, as shown in FIG. 1C, nine circular n-type electrodes 12 made of AuSi are formed on the lower surface 3 b of the current diffusion layer 3. The LED 20 is configured such that the n-type electrode 12 side is die-bonded to a die-bonding surface (not shown) having heat conductivity of various electronic devices.

  The GaP substrate 10 has four grooves 30 which are recessed with respect to the outside of the chip in a region other than the region occupied by the bonding pads 11 on the upper surface 10a. These grooves 30 have a rectangular cross section and are formed to have a depth of 70 μm from the upper surface 10 a of the GaP substrate 10. As can be seen from FIG. 1B, in a plan view, these grooves 30 are provided so as to surround the bonding pad 11 and form an angle of about 45 ° with respect to each chip side surface 10b.

  The LED 20 is manufactured as follows. The LED 20 has a chip size (planar dimension) of 300 μm □.

First, as shown in FIG. 2, an n-type GaAs buffer layer 2 with a layer thickness of 1 μm, an n-type Al _0.5 Ga _0.5 As current diffusion layer 3 with a layer thickness of 3 μm, and a layer on an n-type GaAs substrate 1 as a sacrificial substrate. 1 μm thick n-type Al _0.5 In _0.5 P cladding layer 4, quantum well active layer 5, 1 μm thick p-type Al _0.5 In _0.5 P cladding layer 6, 0.15 μm thick p-type (Al _0.2 Ga _0.8 ) _0.77 In _0.23 P intermediate layer 7, p-type Ga _0.915 In _0.085 P pasted contact layer 8 having a layer thickness of 5 μm, and non-doped GaAs cap layer 9 having a layer thickness of 0.01 μm are formed by MOCVD (metal organic chemical vapor deposition). Laminate in order. As described above, the quantum well active layer 5 is formed by alternately stacking a plurality of barrier layers made of (Al _0.5 Ga _0.5 ) _0.5 In _0.5 P and well layers made of GaInP. As a method for growing each semiconductor layer, in addition to the MOCVD method, other methods such as an MBE method (molecular beam epitaxial method) and a MOMBE method (organometallic molecular beam epitaxial method) can be used.

  During the growth of each semiconductor layer, Zn is used for the p-type dopant, while Si is used for the n-type dopant. In addition, Mg, C, and Be can be used as the p-type dopant, and Se and Te can be used as the n-type dopant.

Further, the carrier concentration of the p-type Ga _0.915 In _0.085 P _adhered contact layer 8 is changed (inclined) with respect to the stacking direction. Specifically, 4 μm on the GaAs cap layer 9 side is 2.5 × 10 ¹⁸ cm ^−3, and 1 μm on the p-type (Al _0.2 Ga _0.8 ) _0.77 In _0.23 P intermediate layer 7 side is 1.0 × 10 ¹⁸ cm 3. ^-3 . The reason why the carrier concentration of the contact layer 8 is inclined as described above is that the carrier concentration at the direct bonding interface is set high to avoid an increase in operating voltage at the direct bonding interface, while suppressing Zn diffusion from the contact layer 8 to the active layer 5. It is to do.

Thereafter, as shown in FIG. 3, the non-doped GaAs cap layer 9 is removed, and the p-type Ga _0.915 In _0.085 P- _bonded contact layer 8 is polished, and the surface of the contact layer 8 (upper surface in FIG. 3) is processed into a mirror surface. After that, the oxide film is removed by surface treatment with an etchant. Also, a p-type GaP substrate 10 having a mirror surface is prepared, and the oxide film is removed by surface treatment with an etchant. Then, after sufficiently washing and drying them, the surface (the lower surface in FIG. 3) to be directly bonded to the GaP substrate 10 is brought into close contact with the surface of the adhesive contact layer 8 in a pressurized state, and is 750 ° C. in vacuum. Heat treatment at temperature for 0.5 hour. As a result, the GaP substrate 10 is directly bonded to the stuck contact layer 8. The heat treatment may be performed in a hydrogen atmosphere.

Thereafter, as shown in FIG. 4, the n-type GaAs substrate 1 and the n-type GaAs buffer layer 2 are removed by etching with an ammonia: hydrogen peroxide-based etchant. Thereafter, the surface of the p-type GaP substrate 10 (upper surface in FIG. 4) is polished so that the p-type GaP substrate 10 has a thickness of 280 μm. Bonding pads 11 made of AuBe / Au having a diameter of 100 μm are formed on the polished surface of the p-type GaP substrate 10 at a pitch of 300 μm according to the chip plane dimensions. Further, a circular n-type electrode 12 made of AuSi and having a diameter of 40 μm is formed on the surface (the lower surface in FIG. 4) of the n-type Al _0.5 Ga _0.5 As current diffusion layer 3. The n-type electrodes 12 are formed so that nine pieces are distributed per chip.

  Thereafter, a plurality of grooves 30 having a depth of 70 μm are formed on the upper surface of the p-type GaP substrate 10 by a blade having a width of 20 μm. As shown in FIG. 5A, the groove 30 passes through a midpoint between the bonding pads 11 and 11 and is 45 ° with respect to a line (shown by a broken line in FIG. 5A) that is expected to become the chip side surface 10b. Form to form an angle. In this example, the pitch of the grooves 30 is 212.1 μm based on the chip planar dimension of 300 μm. In this way, the groove 30 can be formed in the same manner for all the chips.

  Further, the wafer in this state is diced into individual chips using a blade having a width of 20 μm. Thereafter, the damage layer caused by dicing is removed by etching, and the chip is divided into chips. In this way, the LED 20 shown in FIGS. 1A to 1C is obtained.

  In the LED 20 thus manufactured, the external quantum efficiency was 17%. The external quantum efficiency of the LED of the comparative example shown in FIG. 6 (which differs from the LED 20 only in that the groove 30 is not provided in the p-type GaP substrate 10) was 14%. Therefore, by providing the groove 30 in the p-type GaP substrate 10, the external quantum efficiency is improved by about 1.2 times.

  As a result, since the groove 30 provided in the p-type GaP substrate 10 forms an angle of 45 ° with respect to the chip side surface 10b, the light that is multiply reflected inside the chip is reduced, and the electrodes 11, 12 and It shows that the loss due to absorption in the active layer 5 is reduced.

  The effect becomes clear when the depth of the groove 30 is 50 μm or more. In the LED in which the depth of the groove 30 was 50 μm, the external quantum efficiency was 1.1 times that of the LED in FIG.

  In the above example, the number of grooves 30 is four per chip. However, as shown in FIG. 5B, each groove 30 is divided into a pair of parallel grooves 50 and 50 so that the number of grooves 30 is eight per chip. It is also possible to do. In this way, the inner area of the groove having an angle of 45 ° with respect to the chip side surface 10b can be increased, and the external quantum efficiency can be further improved. Actually, in the LED in which the number of grooves (depth: 70 μm) is eight in this way, the external quantum efficiency can be improved 1.3 times as compared with the LED of FIG.

  Regarding current-light output characteristics, in a conventional LED die-bonded on the transparent substrate side, when pulse driving with a period of 1 second and a duty ratio of 3% was performed, thermal saturation occurred at an injection current of about 200 mA. On the other hand, when the LED 20 of this embodiment was pulse-driven under the same conditions, thermal saturation did not occur until the injection current reached 800 mA or more. This is probably because the quantum well active layer 5 which is the light emitting layer in the present embodiment is closer to the die bond surface, and thus the heat dissipation is greatly improved. As a result, the injection current can be increased. Therefore, coupled with the high external emission efficiency of the LED 20, high brightness can be obtained.

(Second Embodiment)
7A, 7B, and 7C are a side cross-sectional view, a plan view, and a bottom view, respectively, showing an LED 40 as a semiconductor light-emitting device according to a second embodiment of the present invention. 7A corresponds to a cross section taken along line AA in FIG. 7B. The LED 40 takes the form of a chip having a substantially rectangular parallelepiped shape.

As shown in FIG. 7A, the LED 40 includes an n-type Al _0.5 Ga _0.5 As current diffusion layer 3 as a first semiconductor layer, an n-type Al _0.5 In _0.5 P cladding layer 4, a quantum well active layer 5 as a light emitting layer, p-type Al _0.5 In _0.5 P cladding layer 6, p-type (Al _0.2 Ga _0.8 ) _0.77 In _0.23 P intermediate layer 7, p-type Ga _0.915 In _0.085 P-attached contact layer 8 as the second semiconductor layer, and transparent substrate A p-type GaP substrate 10 is sequentially provided. The quantum well active layer 5 is configured by alternately laminating a plurality of barrier layers made of (Al _0.5 Ga _0.5 ) _0.5 In _0.5 P and well layers made of GaInP. The GaP substrate 10 is directly bonded to the contact layer 8 (80 indicates a direct bonding interface). As shown in FIG. 7B, a circular bonding pad 11 made of AuBe / Au as a surface electrode is formed in the central region of the upper surface 10a of the p-type GaP substrate 10. On the other hand, as shown in FIG. 7C, a circular Al electrode 23 is provided in the central region of the lower surface 3b of the current diffusion layer 3, and n-type electrodes 12A made of four AuSis extend radially therefrom. The LED 40 is configured such that the Al electrode 23 and the n-type electrode 12A side are die-bonded to a die-bonding surface (not shown) having heat conductivity of various electronic devices.

  The GaP substrate 10 has four pairs (eight) grooves 50A and 50B that are recessed with respect to the outside of the chip in a region other than the region occupied by the bonding pads 11 on the upper surface 10a. These grooves 50 </ b> A and 50 </ b> B have a rectangular cross section and are formed to have a depth of 70 μm from the upper surface 10 a of the GaP substrate 10. 7B, in a plan view, these four pairs of grooves 50A, 50B are provided so as to surround the bonding pad 11, and form an angle of about 45 ° with respect to each chip side surface 10b. Yes.

  As shown in FIG. 7A, a Zn diffusion portion 25 is formed in a part of the p-type GaP substrate 10 on the direct bonding interface 80 side. As shown in FIG. 7B, the Zn diffusion portion 25 is provided in a region surrounded by two adjacent chip side surfaces 10 b and the groove 50 in a plan view. The Zn diffusion portion 25 concentrates the injection current at the corner portion of the quantum well active layer facing the Zn diffusion portion 25, and a substantial light emitting region is shown at the corner portion 26 of the quantum well active layer 5 (indicated by a broken line in FIG. 7A). Limited to.

  The LED 40 is manufactured as follows. The LED 40 has a chip size (planar dimension) of 300 μm □.

First, as in the first embodiment, the following layers are stacked by MOCVD or the like. That is, as shown in FIG. 2, an n-type GaAs buffer layer 2 having a layer thickness of 1 μm and an n-type Al _0.5 Ga _0.5 As current diffusion layer 3 having a layer thickness of 3 μm are formed on an n-type GaAs substrate 1 as a sacrificial substrate. 1 μm thick n-type Al _0.5 In _0.5 P clad layer 4, quantum well active layer 5, 1 μm thick p-type Al _0.5 In _0.5 P clad layer 6, 0.15 μm thick p-type (Al _0.2 Ga _0.8 A _0.77 In _0.23 P intermediate layer 7, a p-type Ga _0.915 In _0.085 P sticking contact layer 8 having a layer thickness of 5 μm, and a non-doped GaAs cap layer 9 having a layer thickness of 0.01 μm are laminated. As described above, the quantum well active layer 5 is formed by alternately laminating a plurality of barrier layers made of (Al _0.5 Ga _0.5 ) _0.5 In _0.5 P and well layers made of GaInP. As a method for growing each semiconductor layer, various methods such as the MBE method and the MOMBE method can be used in addition to the MOCVD method.

  During the growth of each semiconductor layer, Zn is used for the p-type dopant, while Si is used for the n-type dopant. In addition, Mg, C, and Be can be used as the p-type dopant, and Se and Te can be used as the n-type dopant.

Further, the carrier concentration of the p-type Ga _0.915 In _0.085 P _adhered contact layer 8 is fixed at 5 × 10 ¹⁷ cm ⁻³ .

Thereafter, in the same manner as shown in FIG. 3, the non-doped GaAs cap layer 9 is removed and the p-type Ga _0.915 In _0.085 P pasted contact layer 8 is polished, and the surface of the contact layer 8 (upper surface in FIG. 3) is polished. Process into a mirror surface.

On the other hand, on the surface (the lower surface in FIG. 3) to be directly bonded of the p-type GaP substrate 10, Zn is diffused into four circular shapes with a diameter of 50 μm per chip, and the carrier concentration is 1 × 10 ¹⁹ cm ^−3. The Zn diffusion portion 25 is formed. The Zn diffusion portions 25 are formed on the surface to be directly bonded to the p-type GaP substrate 10 at a pitch of 300 μm according to the planar dimensions of the chip, four pieces per chip.

  Thereafter, the surface of the p-type GaP substrate 10 and the surface of the adhesive contact layer 8 are surface-treated with an etchant to remove the oxide film. Then, after sufficiently washing and drying them, the surface of the p-type GaP substrate 10 to be directly bonded and the surface of the pasted contact layer 8 are brought into close contact with each other in a pressurized state for 0.5 hours in a vacuum. And heat treatment at 750 ° C. As a result, the p-type GaP substrate 10 is directly bonded to the stuck contact layer 8.

  At this time, the portion where the Zn diffusion portion 25 of the p-type GaP substrate 10 is joined to the pasted contact layer 8 is an ohmic junction, but the other portions of the pasted contact layer 8 and the p-type GaP substrate 10 have any carrier concentration. Therefore, ohmic junction is not achieved. Therefore, a circular channel having a diameter of 50 μm is formed by the Zn diffusion portion 25. As a result, an injection current flows only in this portion during operation, and a current confinement structure is obtained in which a substantial light emitting region is limited to the corner portion 26 of the quantum well active layer 5.

Thereafter, as shown in FIG. 4, the n-type GaAs substrate 1 and the n-type GaAs buffer layer 2 are removed by etching with an ammonia: hydrogen peroxide-based etchant. Thereafter, the surface of the p-type GaP substrate 10 (upper surface in FIG. 4) is polished so that the p-type GaP substrate 10 has a thickness of 280 μm. Bonding pads 11 made of AuBe / Au having a diameter of 100 μm are formed on the polished surface of the p-type GaP substrate 10 at a pitch of 300 μm according to the chip plane dimensions. Further, an n-type electrode 12A made of AuSi is formed on the surface (the lower surface in FIG. 4) of the n-type Al _0.5 Ga _0.5 As current diffusion layer 3, and is further circularly connected to the n-type electrode 12. The Al electrode 23 is formed.

  Thereafter, a plurality of pairs of grooves 50 and 50 having a depth of 70 μm are formed on the upper surface of the p-type GaP substrate 10 by a blade having a width of 20 μm in the manner shown in FIG. 5B. The pitch of each pair of grooves 50, 50 is 212.1 μm based on the chip planar dimension of 300 μm. In this way, the grooves 50A and 50B (FIG. 7B) can be formed in the same manner for all the chips.

  Further, the wafer in this state is diced into individual chips using a blade having a width of 20 μm. Thereafter, the damage layer caused by dicing is removed by etching, and the chip is divided into chips. In this way, the LED 40 shown in FIGS. 7A to 7C is obtained.

  In the LED 40 thus manufactured, the external quantum efficiency was 20%. On the other hand, the external quantum efficiency of the comparative example LED that does not have the current confinement structure (which differs from the LED 40 only in that the Zn diffusion portion 25 is not provided) was 18%. Therefore, by performing current confinement by the Zn diffusion portion 25, the external quantum efficiency is improved by about 1.1 times.

  The reason for this is explained as follows. That is, in this LED 40, as shown in FIG. 7B, in a plan view, the corner portion 26 of the quantum well active layer 5 that is a substantial light emitting region is in a region opposite to the surface electrode 11 with respect to the groove 50B. Therefore, as shown in FIG. 7A, most of the light L generated at the corner portion 26 is emitted outside through the inner surface of the groove 50B before reaching the surface electrode 11. Therefore, it is possible to further reduce the multiple reflection inside the element and increase the external emission efficiency.

(Third embodiment)
In the second embodiment, the internal confinement structure is adopted as a method for limiting the light emitting region. However, as in the LED 60 shown in FIGS. 8A, 8B, and 8C, the n-type Al _0.5 Ga _0.5 As current diffusion layer 3 is used. A similar effect can be obtained by providing the n-type electrode 12B in ohmic contact only at the four corners of the chip.

  8A, FIG. 8B, and FIG. 8C correspond to FIG. 7A, FIG. 7B, and FIG. 7C, respectively. The LED 60 includes triangular frame-shaped n-type electrodes 12B each made of AuSi at the four corners of the lower surface 3b of the current diffusion layer 3, instead of the Zn diffusion portion 25 of the p-type GaP substrate 10 described above. These n-type electrodes 12B are electrically connected to the Al electrodes 23 via four Al electrodes 24 extending radially from the circular Al electrode 23 in the central region of the lower surface 3b.

  Also in this LED 60, the substantial light emitting region is limited to the corner portion 26 of the quantum well active layer 5 during operation. Therefore, as shown in FIG. 8A, most of the light L generated at the corner portion 26 is emitted outside through the inner surface of the groove 50B before reaching the surface electrode 11. Therefore, it is possible to further reduce the multiple reflection inside the element and increase the external emission efficiency.

(Fourth embodiment)
Moreover, you may provide the four groove | channels 31 substantially parallel with respect to the chip | tip side surface 10b to respectively correspond like LED61 shown to FIG. 9A, FIG. 9B, and FIG. 9C.

  9A, FIG. 9B, and FIG. 9C correspond to FIG. 7A, FIG. 7B, and FIG. 7C, respectively. As can be clearly seen from FIG. 1B, in a plan view, the four grooves 31 of the LED 61 are provided so as to surround the bonding pad 11 and extend substantially parallel to the corresponding chip side surface 10b. Yes. The Zn diffusion portion 25A of the p-type GaP substrate 10 shown in FIG. 9A has a frame over the entire periphery in a region sandwiched between the chip side surface 10b and the groove 31 corresponding to the chip side surface in a plan view. It is provided in the shape.

  The Zn diffusion portion 25A concentrates the injection current at the corner portion of the quantum well active layer facing the Zn diffusion portion 25A, and a substantial light emitting region is shown in the peripheral portion 26A of the quantum well active layer 5 (indicated by a broken line in FIG. 9A). Limited to. Therefore, as shown in FIG. 9A, most of the light L generated at the peripheral portion 26 </ b> A is emitted outside through the inner surface of the groove 31 before reaching the surface electrode 11. Therefore, it is possible to further reduce the multiple reflection inside the element and increase the external emission efficiency.

(Fifth embodiment)
In the fourth embodiment, the internal confinement structure is adopted as a method for limiting the light emitting region. However, like the LED 62 shown in FIGS. 10A, 10B, and 10C, the n-type Al _0.5 Ga _0.5 As current diffusion layer 3 is used. The same effect can be obtained even if the n-type electrode 12C in ohmic contact is provided in a frame shape in the peripheral region of the chip.

  10A, FIG. 10B, and FIG. 10C correspond to FIG. 9A, FIG. 9B, and FIG. 9C, respectively, and the same components are denoted by the same reference numerals and the description thereof is omitted. The LED 62 includes a frame-shaped n-type electrode 12C made of AuSi over the entire circumference of the peripheral region of the lower surface 3b of the current diffusion layer 3 instead of the Zn diffusion portion 25A of the p-type GaP substrate 10 described above. The n-type electrode 12C is electrically connected to the Al electrode 23 via four Al electrodes 24 extending radially from the circular Al electrode 23 in the central region of the lower surface 3b.

  Also in this LED 62, a substantial light emitting region during operation is limited to the corner portion 26A (indicated by a broken line in FIG. 10A) of the quantum well active layer 5. Therefore, as shown in FIG. 10A, most of the light L generated at the peripheral portion 26 </ b> A is emitted to the outside through the inner surface of the groove 31 before reaching the surface electrode 11. Therefore, it is possible to further reduce the multiple reflection inside the element and increase the external emission efficiency.

  In each of the above-described embodiments, the quantum well active layer 5 is formed of an AlGaInP-based material. However, the material and type of the light-emitting layer are not limited to this, and other material systems such as an AlGaAs-based material may be used. A single layer may be used.

  Further, although the GaP substrate 10 is used as the transparent substrate, the present invention is not limited to this, and other semiconductor substrates such as GaN and SiC may be used as long as they are transparent to the emitted light. Furthermore, an insulating substrate such as sapphire or glass may be used. In this case, both p-type and n-type electrodes may be formed on the die-bonded semiconductor layer, and the electrodes may be die-bonded with bumps. The layer to which the transparent substrate is directly bonded may be a cladding layer other than the contact layer.

In addition, although an n-type Al _0.5 Ga _0.5 As layer is used as the current diffusion layer, the present invention is not limited to this, and lattice matching is performed with a growth substrate such as (Al _0.3 Ga _0.7 ) _0.5 In _0.5 P, so that the emission wavelength can be adjusted. A transparent layer may be used.

It is a sectional side view which shows LED of 1st Embodiment of this invention. It is a top view which shows LED of 1st Embodiment. It is a bottom view which shows LED of 1st Embodiment. It is a figure which shows 1 process among the manufacturing processes of LED of 1st Embodiment. It is a figure which shows a mode that a p-type GaP board | substrate is directly joined to a sticking contact layer. It is a figure which shows a mode that the n-type GaAs substrate and the n-type GaAs buffer layer were removed. It is a figure which shows the example which forms a groove | channel by dicing. It is a figure which shows another example which forms a groove | channel by dicing. It is a figure which shows LED of a comparative example. It is a sectional side view which shows LED of an example of 2nd Embodiment. It is a top view which shows LED of an example of 2nd Embodiment. It is a bottom view which shows LED of 2nd Embodiment. It is a sectional side view which shows LED of 3rd Embodiment. It is a top view which shows LED of 3rd Embodiment. It is a bottom view which shows LED of 3rd Embodiment. It is a sectional side view which shows LED of 4th Embodiment. It is a top view which shows LED of 4th Embodiment. It is a bottom view which shows LED of 4th Embodiment. It is side sectional drawing which shows LED of 5th Embodiment. It is a top view which shows LED of 5th Embodiment. It is a bottom view which shows LED of 5th Embodiment. It is a figure which shows the manufacturing method of the conventional AlGaInP type LED. It is a figure which shows the manufacturing method of the conventional AlGaInP type LED. It is a figure which shows the conventional AlGaInP type LED. It is a schematic diagram which shows the mode of the multiple reflection in the conventional LED.

Explanation of symbols

1 n-type GaAs substrate 2 n-type GaAs buffer layer 3 n-type Al _0.5 Ga _0.5 As current diffusion layer 4 n-type Al _0.5 In _0.5 P clad layer 5 quantum well active layer 6 p-type Al _0.5 In _0.5 P clad layer 7 p-type (Al _0.2 Ga _0.8 ) _0.77 In _0.23 P intermediate layer 8 p-type Ga _0.915 In _0.085 P stuck contact layer 9 Non-doped GaAs cap layer 9
10 p-type GaP substrate 11 bonding pad 12, 12A, 12B, 12C n-type electrode 20, 40, 60, 61, 62 LED
25, 25A Zn diffused portion 30, 31, 50, 50A, 50B groove

Claims (10)

A first conductive type first semiconductor layer, a light emitting layer for generating light, a second conductive type second semiconductor layer, and transparent to light from the light emitting layer, and in the second semiconductor layer A transparent substrate with the surfaces of 1 directly joined, in order,
The transparent substrate is provided with a surface electrode in a partial region of the second surface opposite to the first surface, and outside the region of the second surface other than the region occupied by the surface electrode. A semiconductor light emitting device, wherein a recessed groove is provided. The semiconductor light emitting device according to claim 1,
Take the form of a chip that is substantially rectangular parallelepiped,
The semiconductor light emitting element, wherein the groove extends along the second surface at an angle of substantially 45 ° with respect to the side surface of the chip. The semiconductor light emitting device according to claim 2,
4. A semiconductor light emitting device, wherein the number of grooves is 4 or more per chip. The semiconductor light emitting device according to claim 1,
A depth of the groove is 50 μm or more. The semiconductor light emitting device according to claim 2,
A structure for concentrating the injection current in the light emitting layer portion facing the region surrounded by the two adjacent side surfaces of the chip and the groove other than the region occupied by the surface electrode in the second surface is provided. A semiconductor light emitting device characterized by the above. The semiconductor light emitting device according to claim 1,
Take the form of a chip that is substantially rectangular parallelepiped,
Each of the grooves extends along the second surface substantially parallel to the corresponding chip side surface;
A structure in which the injection current is concentrated on a light emitting layer portion facing the region sandwiched between the chip side surface and the groove corresponding to the chip side surface other than the region occupied by the surface electrode in the second surface. A semiconductor light emitting device comprising the semiconductor light emitting device. The semiconductor light emitting device according to claim 1,
The light emitting layer may characterized by having at least one layer formed of _{(Al y Ga 1-y)} z In 1-z P ( provided that 0 ≦ y ≦ 1,0 <z < 1.) A semiconductor light emitting device. The semiconductor light emitting device according to claim 1,
A semiconductor light emitting element, wherein the transparent substrate is made of GaP. A method of manufacturing a semiconductor light emitting device for producing the semiconductor light emitting device according to claim 1,
The first semiconductor layer, the light emitting layer, and the second semiconductor layer are sequentially stacked on the sacrificial substrate,
Directly bonding the first surface of the transparent substrate to the second semiconductor layer;
Removing the sacrificial substrate,
The surface electrode is provided in a partial region of the second surface opposite to the first surface of the transparent substrate,
A method of manufacturing a semiconductor light emitting element, comprising: forming a groove recessed with respect to the outside using a dicing blade in a region other than the region occupied by the surface electrode in the second surface of the transparent substrate. An electronic device comprising the semiconductor light emitting device according to claim 1,
An electronic apparatus, wherein the first semiconductor layer side opposite to the transparent substrate of the semiconductor light emitting element is die-bonded to a die bond surface having heat conductivity.

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