JP5936415B2 - 半導体集積回路、情報処理装置および制御方法 - Google Patents

半導体集積回路、情報処理装置および制御方法 Download PDF

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Publication number
JP5936415B2
JP5936415B2 JP2012076774A JP2012076774A JP5936415B2 JP 5936415 B2 JP5936415 B2 JP 5936415B2 JP 2012076774 A JP2012076774 A JP 2012076774A JP 2012076774 A JP2012076774 A JP 2012076774A JP 5936415 B2 JP5936415 B2 JP 5936415B2
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Japan
Prior art keywords
power
control unit
clock
integrated circuit
semiconductor integrated
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JP2012076774A
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English (en)
Japanese (ja)
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JP2013206309A (ja
JP2013206309A5 (enExample
Inventor
和也 加山
和也 加山
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Canon Inc
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Canon Inc
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Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2012076774A priority Critical patent/JP5936415B2/ja
Priority to US13/841,464 priority patent/US9360921B2/en
Priority to CN201310109180.2A priority patent/CN103365263B/zh
Publication of JP2013206309A publication Critical patent/JP2013206309A/ja
Publication of JP2013206309A5 publication Critical patent/JP2013206309A5/ja
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Publication of JP5936415B2 publication Critical patent/JP5936415B2/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/329—Power saving characterised by the action undertaken by task scheduling
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Power Sources (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2012076774A 2012-03-29 2012-03-29 半導体集積回路、情報処理装置および制御方法 Active JP5936415B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2012076774A JP5936415B2 (ja) 2012-03-29 2012-03-29 半導体集積回路、情報処理装置および制御方法
US13/841,464 US9360921B2 (en) 2012-03-29 2013-03-15 Semiconductor integrated circuit, information processing apparatus, and control method
CN201310109180.2A CN103365263B (zh) 2012-03-29 2013-03-29 半导体集成电路、信息处理装置和控制方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012076774A JP5936415B2 (ja) 2012-03-29 2012-03-29 半導体集積回路、情報処理装置および制御方法

Publications (3)

Publication Number Publication Date
JP2013206309A JP2013206309A (ja) 2013-10-07
JP2013206309A5 JP2013206309A5 (enExample) 2016-02-04
JP5936415B2 true JP5936415B2 (ja) 2016-06-22

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JP2012076774A Active JP5936415B2 (ja) 2012-03-29 2012-03-29 半導体集積回路、情報処理装置および制御方法

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US (1) US9360921B2 (enExample)
JP (1) JP5936415B2 (enExample)
CN (1) CN103365263B (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6224994B2 (ja) * 2013-11-01 2017-11-01 キヤノン株式会社 情報処理装置およびその制御方法
JP6513463B2 (ja) * 2015-04-17 2019-05-15 ルネサスエレクトロニクス株式会社 半導体集積回路
US10152112B2 (en) * 2015-06-10 2018-12-11 Sonics, Inc. Power manager with a power switch arbitrator
TWI604326B (zh) * 2016-10-27 2017-11-01 財團法人工業技術研究院 基於fpga之系統功率評估裝置與方法
GB2569537B (en) * 2017-12-18 2020-02-26 Advanced Risc Mach Ltd A technique for managing power domains in an integrated circuit
KR102663815B1 (ko) * 2018-06-01 2024-05-07 삼성전자주식회사 컴퓨팅 장치 및 이의 동작 방법
US12019494B2 (en) * 2022-06-29 2024-06-25 Microsoft Technology Licensing, Llc Domain clock and power activation control circuit to reduce voltage droop and related methods

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4245150A (en) 1979-02-26 1981-01-13 International Business Machines Corporation Power line disturbance detector circuit
US5664089A (en) 1994-04-26 1997-09-02 Unisys Corporation Multiple power domain power loss detection and interface disable
JP3437174B2 (ja) 2001-04-12 2003-08-18 沖電気工業株式会社 省電力化集積回路および省電力化集積回路の制御方法
JP3595799B2 (ja) 2002-02-28 2004-12-02 松下電器産業株式会社 半導体集積回路及びそのリセット方法
US6586969B1 (en) * 2002-03-25 2003-07-01 Lsi Logic Corporation Method and system for synchronously initializing digital logic circuits
US7659746B2 (en) * 2005-02-14 2010-02-09 Qualcomm, Incorporated Distributed supply current switch circuits for enabling individual power domains
JP2006331107A (ja) * 2005-05-26 2006-12-07 Matsushita Electric Ind Co Ltd 電力管理回路、及び電子回路
JP2009054031A (ja) * 2007-08-28 2009-03-12 Toshiba Corp リセット制御装置
US8493109B2 (en) * 2010-03-31 2013-07-23 Qualcomm Incorporated System and method to control a power on reset signal
JPWO2012132020A1 (ja) * 2011-03-31 2014-07-24 富士通株式会社 情報処理システム、システム管理装置、集積回路

Also Published As

Publication number Publication date
US9360921B2 (en) 2016-06-07
JP2013206309A (ja) 2013-10-07
CN103365263A (zh) 2013-10-23
US20130262895A1 (en) 2013-10-03
CN103365263B (zh) 2016-09-07

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