JP5935643B2 - Semiconductor light emitting device - Google Patents

Description

  The present invention relates to a semiconductor light emitting device in which a semiconductor light emitting element and a driving device for the semiconductor light emitting element are disposed on the same semiconductor substrate.

  In a semiconductor light emitting device having a semiconductor light emitting element such as a light emitting diode (LED) or a semiconductor laser, the semiconductor light emitting device can be miniaturized by integrating the semiconductor light emitting element and a driving device for driving the light emitting element on the same semiconductor substrate. It has been. For example, a method has been proposed in which a semiconductor light emitting element is formed on a silicon substrate via an intervening layer, and a driving device for the semiconductor light emitting element is formed monolithically on the silicon substrate (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 2-150081

  However, in a field effect transistor (FET) mounted on a silicon substrate as a driving device for a semiconductor light emitting element, a PNP parasitic transistor may be generated, and a current that cannot be controlled by the gate voltage may flow. Further, when a current is passed through the substrate, an NPN parasitic transistor is formed, and the FET may not operate normally. As described above, when the semiconductor light emitting element and the driving device are integrated on the same semiconductor substrate, the semiconductor light emitting device may not operate normally due to a malfunction of the driving device.

  In view of the above problems, an object of the present invention is to provide a semiconductor light emitting device in which the semiconductor light emitting element and the driving device thereof are arranged on the same semiconductor substrate and the occurrence of malfunction in the driving device is suppressed.

  According to one aspect of the present invention, (a) a semiconductor substrate in which a light emitting region and a driving device region are defined on the main surface, and (b) continuous from the light emitting region to the driving device region on the main surface of the semiconductor substrate. A stacked body having a structure in which an n-type semiconductor layer, an active layer, and a p-type semiconductor layer made of an epitaxially grown nitride semiconductor are stacked in this order, and (c) disposed on the stacked body An interlayer insulating film, (d) a control transistor disposed above the driving device region via at least a part of the stacked body and the interlayer insulating film, and (e) in the interlayer insulating film There is provided a semiconductor light emitting device including a light shielding film disposed between a control transistor and a stacked body.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor light-emitting device and its drive device are arrange | positioned on the same semiconductor substrate, and the semiconductor light-emitting device with which generation | occurrence | production of the malfunction in the drive device was suppressed can be provided.

It is typical sectional drawing which shows the structure of the semiconductor light-emitting device concerning embodiment of this invention. 1 is a schematic plan view showing a configuration of a semiconductor light emitting device according to an embodiment of the present invention. 1 is an equivalent circuit diagram of a semiconductor light emitting device according to an embodiment of the present invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor light-emitting device which concerns on embodiment of this invention (the 1). It is process sectional drawing for demonstrating the manufacturing method of the semiconductor light-emitting device which concerns on embodiment of this invention (the 2). It is process sectional drawing for demonstrating the manufacturing method of the semiconductor light-emitting device which concerns on embodiment of this invention (the 3). It is process sectional drawing for demonstrating the manufacturing method of the semiconductor light-emitting device which concerns on embodiment of this invention (the 4). It is process sectional drawing for demonstrating the manufacturing method of the semiconductor light-emitting device which concerns on embodiment of this invention (the 5). It is process sectional drawing for demonstrating the manufacturing method of the semiconductor light-emitting device which concerns on embodiment of this invention (the 6). It is process sectional drawing for demonstrating the manufacturing method of the semiconductor light-emitting device which concerns on embodiment of this invention (the 7). It is process sectional drawing for demonstrating the manufacturing method of the semiconductor light-emitting device which concerns on embodiment of this invention (the 8). It is typical sectional drawing which shows the structure of the semiconductor light-emitting device which concerns on the modification of embodiment of this invention.

  Embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the embodiments of the present invention include the material, shape, structure, arrangement, etc. of components. Is not specified as follows. The embodiment of the present invention can be variously modified within the scope of the claims.

  As shown in FIG. 1, a semiconductor light emitting device 1 according to an embodiment of the present invention is arranged on a main surface of a semiconductor substrate 10 having a light emitting region 101 and a driving device region 102 defined on the main surface, and the semiconductor substrate 10. The stacked body 20 having a structure in which the n-type semiconductor layer 21, the active layer 22, and the p-type semiconductor layer 23 are stacked in this order, the interlayer insulating film 40 disposed on the stacked body 20, and the stacked body 20 And a light-shielding film 50 disposed between the control transistor 60 and the stacked body 20 in the interlayer insulating film 40. With. The stacked body 20 is continuously disposed on the main surface of the semiconductor substrate 10 from the light emitting region 101 to the driving device region 102. The n-type semiconductor layer 21, the active layer 22, and the p-type semiconductor layer 23 are made of a nitride semiconductor formed by epitaxial growth.

  The interlayer insulating film 40 is continuously arranged from above the light emitting region 101 to above the driving device region 102, and the periphery of the control transistor 60 is covered with the interlayer insulating film 40. The light shielding film 50 is embedded in the interlayer insulating film 40. In the example shown in FIG. 1, the light shielding film 50 includes a first light shielding layer 51 and a second light shielding layer 52. As will be described later, the first light shielding layer 51 and the second light shielding layer 52 are formed in different steps.

  The semiconductor light emitting device 1 further includes a transparent electrode 30 disposed between the stacked body 20 and the interlayer insulating film 40 above the light emitting region 101 and in contact with the p-type semiconductor layer 23. The anode electrode 111 disposed on the interlayer insulating film 40 is electrically connected to the transparent electrode 30 in the opening formed in the interlayer insulating film 40. Holes are supplied from the anode electrode 111 to the transparent electrode 30. Further, the cathode electrode 112 is disposed on the back surface facing the main surface on which the stacked body 20 of the semiconductor substrate 10 is disposed.

  Electrons supplied from the cathode electrode 112 via the semiconductor substrate 10 and the n-type semiconductor layer 21 and holes supplied from the anode electrode 111 via the transparent electrode 30 and the p-type semiconductor layer 23 are the active layer 22. Recombines to generate light. That is, the semiconductor light emitting element 100 that generates the output light L is formed on the light emitting region 101. The output light L generated in the stacked body 20 passes through the transparent electrode 30 and the interlayer insulating film 40 and is output to the outside of the semiconductor light emitting device 1.

  The control transistor 60 functions as a drive device that controls light flowing in the semiconductor light emitting element 100 by controlling a current flowing through the stacked body 20 in the film thickness direction. Specifically, the control transistor 60 controls the injection of electrons into the active layer 22 through the n-type semiconductor layer 21 and the injection of holes into the active layer 22 through the p-type semiconductor layer 23. The light emission in the stacked body 20 is controlled. That is, the semiconductor light emitting device 100 is driven by applying a predetermined voltage between the anode electrode 111 and the cathode electrode 112.

  As the control transistor 60, a transistor having a structure in which a p-type region and an n-type region are adjacent to each other in a lateral direction that is parallel to the main surface and an insulating film is disposed on the lower surface facing the stacked body 20 is used. The In the control transistor 60, the main current flows in the lateral direction.

  For example, a junction field effect transistor such as a thin film transistor (TFT) structure can be used as the control transistor 60. The control transistor 60 shown in FIG. 1 has an npn structure 61 in which a first n-type region 611, a p-type region 612, and a second n-type region 613 are arranged in this order in the horizontal direction. A gate insulating film 62 is disposed on the npn structure 61 so as to cover at least the entire p-type region 612, and a gate region 63 is disposed so as to face the p-type region 612 with the gate insulating film 62 interposed therebetween. . In the control transistor 60 shown in FIG. 1, it is assumed that the first n-type region 611 is a drain region and the second n-type region 613 is a source region. Below the npn structure 61, a part of the interlayer insulating film 40 in the film thickness direction and a part of the stacked body 20 in the film thickness direction are arranged.

  A drain electrode 601, a source electrode 602, and a gate electrode 603 are disposed on the interlayer insulating film 40. The first n-type region 611 is connected to the drain electrode 601, the second n-type region 613 is connected to the source electrode 602, and the gate region 63 is connected to the gate electrode 603. Each region and each electrode of the control transistor 60 are connected to each other at an opening provided in the interlayer insulating film 40 and an opening provided in the second light shielding layer 52. Further, as shown in FIG. 1, the source electrode 602 of the control transistor 60 and the anode electrode 111 of the semiconductor light emitting device 100 are connected by the wiring layer 71 disposed on the interlayer insulating film 40.

  The semiconductor substrate 10 shown in FIG. 1 has a structure in which a buffer layer 12 is disposed on a silicon substrate 11 and a stacked body 20 is disposed on the buffer layer 12. However, the buffer layer 12 may be omitted.

The buffer layer 12, for _{example, Al x M y Ga 1-} xy N (M is indium (In) or boron (B), 0 <x ≦ 1,0 ≦ y ≦ 1, x + y = 1) first consisting of And sub-layers of AlaMbGa1-a-bN (M is In or B, 0 ≦ a <1, 0 ≦ b ≦ 1, a + b = 1, a <x) are alternately stacked. A multilayer structure can be adopted. For example, the first sublayer is an aluminum nitride (AlN) film having a thickness of about 0.5 to 5 nm, and the second sublayer is a gallium nitride (GaN) film having a thickness of about 0.5 to 200 nm.

  The n-type semiconductor layer 21 is, for example, a GaN film having a thickness of about 5 μm doped with silicon (Si) as an n-type dopant, and supplies electrons to the active layer 22. The p-type semiconductor layer 23 is, for example, a GaN film having a thickness of about 0.2 μm doped with a p-type dopant, and supplies holes to the active layer 22. The p-type dopant is magnesium (Mg), zinc (Zn), cadmium (Cd), calcium (Ca), beryllium (Be), carbon (C), or the like.

  The active layer 22 has, for example, a multiple quantum well (MQW) structure in which InGaN films and GaN films are alternately stacked. The film thicknesses of the InGaN film and the GaN film are about several μm to several tens of μm, respectively.

The transparent electrode 30 and the interlayer insulating film 40 are made of a material that transmits light generated in the active layer 22. For the transparent electrode 30, for example, an indium tin oxide (ITO) film can be employed. The thickness of the ITO film is about 50 nm to 500 nm. As the interlayer insulating film 40, for example, a silicon oxide (SiO ₂ ) film having a film thickness of about 150 nm to 1500 nm can be employed.

  For the light shielding film 50, for example, titanium (Ti), tungsten (W), or the like is preferably used. The light emitted from the semiconductor light emitting element 100 in the direction of the control transistor 60 is shielded by the light shielding film 50 so that the light does not strike the control transistor 60. As shown in FIG. 1, the light shielding film 50 is disposed on the side surface and the bottom surface facing the stacked body 20 of the control transistor 60. Since the light shielding film 50 is embedded in the interlayer insulating film 40, the light shielding film 50 is hardly exposed to the atmosphere or pure water for a long time. For this reason, deterioration of the light shielding film 50 due to water vapor or the like can be suppressed.

  For the anode electrode 111 and the cathode electrode 112, for example, gold (Au) or the like can be employed.

  FIG. 2 is a plan view of the semiconductor light emitting device 1 as viewed from the anode electrode 111 side. FIG. 1 is a cross-sectional view taken along the II direction of FIG. In FIG. 2, regions indicated by broken lines inside the anode electrode 111, the drain electrode 601, the source electrode 602, and the gate electrode 603 are openings of the interlayer insulating film 40 through which the respective electrodes are transmitted.

  As shown in FIG. 2, the transparent electrode 30 is disposed over the entire light emitting region 101. Further, the anode electrode 111 is arranged along the outer periphery of the transparent electrode 30 so that a current flows through the entire area of the transparent electrode 30. Thereby, the current flowing through the active layer 22 is made uniform, and light can be generated in a wide range of the active layer 22.

FIG. 3 shows an equivalent circuit diagram of the semiconductor light emitting device 1. As already described, the source electrode 602 of the control transistor 60 and the anode electrode 111 of the semiconductor light emitting device 100 are connected by the wiring layer 71. The cathode electrode 112 of the semiconductor light emitting device 100 is grounded. Then, by applying a gate voltage V _GS equal to or higher than the threshold voltage between the gate electrode 603 and the source electrode 602 in a state where a predetermined drain voltage V _DD is applied to the drain electrode 601 of the control transistor 60, the control transistor 60 becomes Turn on. As a result, a current flows between the anode electrode 111 and the cathode electrode 112 of the semiconductor light emitting device 100, and the semiconductor light emitting device 100 emits light. For example, the drain voltage V _DD is about 10V, and the gate voltage V _GS is about 4V. By turning off the control transistor 60, the light emission of the semiconductor light emitting device 100 is stopped.

As described above, in the semiconductor light emitting device 1 according to the embodiment, the control transistor 60 that is the driving device for the semiconductor light emitting element 100 is disposed on the stacked body 20 that is the epitaxially grown film constituting the semiconductor light emitting element 100. . For example, a junction field effect transistor such as a TFT having a structure in which a main current (drain current) flows in the lateral direction and an insulating film is disposed on the lower surface facing the stacked body 20 is controlled in the control transistor 60. It is preferably used for the transistor 60. For this reason, the semiconductor light emitting device 1 does not generate a parasitic transistor. Therefore, there is no problem that a current that cannot be controlled by the gate voltage V _GS flows or that an FET operation is not performed when a current flows through the semiconductor substrate 10.

  In addition, since the control transistor 60 is disposed on the stacked body 20 which is a part of the semiconductor light emitting element 100, the area of the semiconductor light emitting device 1 is reduced as compared with the case where the control transistor 60 is disposed in another region of the silicon substrate 11. Can be small.

  Further, the light shielding film 50 is formed inside the interlayer insulating film 40, and the control transistor 60 is covered with the light shielding film 50 so that the light emitted from the semiconductor light emitting element 100 does not strike. By embedding the light shielding film 50 in the interlayer insulating film 40, insulation between the control transistor 60 and the semiconductor light emitting element 100 is realized simultaneously with light shielding. Since an extra region for the light shielding film 50 is unnecessary, an increase in the area of the semiconductor light emitting device 1 is suppressed.

  A method for manufacturing the semiconductor light emitting device 1 shown in FIG. 1 will be described with reference to FIGS. In addition, the manufacturing method of the semiconductor light-emitting device 1 described below is an example, and it is needless to say that it can be realized by various other manufacturing methods including this modification.

  First, the buffer layer 12 is formed on the silicon substrate 11 to configure the semiconductor substrate 10. On the buffer layer 12, an n-type semiconductor layer 21, an active layer 22, and a p-type semiconductor layer 23 are sequentially stacked by an epitaxial growth method to form a stacked body 20 as shown in FIG. 4. Next, as illustrated in FIG. 5, the stacked body 20 and the buffer layer 12 are etched to a chip size by using a dry etching method or the like, and element isolation is performed.

  As shown in FIG. 6, a part of the upper portion of the stacked body 20 is removed by etching in a region where the control transistor 60 is formed. In the example shown in FIG. 6, the p-type semiconductor layer 23 and the active layer 22 are all removed, and the upper portion of the n-type semiconductor layer 21 is removed. Note that an interlayer insulating film 40, a wiring layer 71, a first light shielding layer 51, and a second light shielding layer 52 are formed on the side surfaces of the removed epitaxial film from the stacked body 20. For this reason, it is preferable to taper about 45 degrees between the side surface and the upper surface exposed by etching of the stacked body 20. That is, the thickness of the stacked body 20 gradually increases from the driving device region 102 toward the light emitting region 101.

  As shown in FIG. 7, after forming the transparent electrode 30 on the p-type semiconductor layer 23 in the light emitting region 101, the first insulating layer 41 is formed on the entire surface of the stacked body 20. Next, a first light shielding layer 51 is formed on the first insulating layer 41 in the driving device region 102. The first light shielding layer 51 is disposed in a region other than the light emitting region 101 and is also formed on the side surface of the stacked body 20 that is a boundary between the light emitting region 101 and the driving device region 102. Thereby, the light incident on the control transistor 60 from the side surface direction is blocked.

  After the second insulating layer 42 is formed on the entire surface, a control transistor 60 is formed on the second insulating layer 42 in the driving device region 102 as shown in FIG. For example, in order to form the npn structure 61, a plasma chemical vapor deposition (PE-CVD) method in which heat treatment is performed at 350 ° C. or a low pressure chemical vapor deposition (LP-CVD) method in which heat treatment is performed at 650 ° C. is used. A silicon layer is formed. Since the heat treatment at 650 ° C. performed by the LP-CVD method is also effective for activating the p-type impurity magnesium (Mg), a method for forming a polysilicon layer by the LP-CVD method will be described. That is, after the growth of the polysilicon layer, silicon (Si) implantation and laser annealing at, for example, 600 ° C. are performed to form amorphous Si having large crystal grains. Impurity ion implantation is performed here to form a first n-type region 611, a p-type region 612, and a second n-type region 613. Thereafter, a gate insulating film 62 and a gate region 63 are formed. For the gate region 63, for example, a polysilicon film into which impurity ions are implanted can be employed.

  Next, as shown in FIG. 9, after the third insulating layer 43 is formed on the entire surface, the second light shielding layer 52 is formed on the third insulating layer 43 in the driving device region 102. Further, in order to connect the first n-type region 611 that is the drain region, the second n-type region 613 that is the source region, and the gate region 63 to the drain electrode 601, the source electrode 602, and the gate electrode 603, respectively. Are formed in the second light shielding layer 52.

  Thereafter, as shown in FIG. 10, a fourth insulating layer 44 is formed on the entire surface. The first insulating layer 41 to the fourth insulating layer 44 constitute the interlayer insulating film 40 shown in FIG. An opening for connecting the first n-type region 611, the second n-type region 613, and the gate region 63 to the drain electrode 601, the source electrode 602, and the gate electrode 603 is provided as an interlayer insulating film 40. To form. At this time, an opening for connecting the anode electrode 111 and the transparent electrode 30 is also formed in the interlayer insulating film 40.

  Next, as shown in FIG. 11, the drain electrode 601, the source electrode 602, the gate electrode 603, and the anode electrode 111 are formed so as to fill the opening formed in the interlayer insulating film 40 and the second light shielding layer 52. To do. A wiring layer 71 is also formed at the same time. Thereafter, the cathode electrode 112 is formed on the back surface of the semiconductor substrate 10 to complete the semiconductor light emitting device 1 shown in FIG.

  In the manufacturing method of the semiconductor light emitting device 1 described above, the stacked body 20 which is an epitaxially grown film is etched to a chip size by dry etching, and element isolation is performed. Although the control transistor 60 is formed after the epitaxial growth process, the formation process of the control transistor 60 is performed at 650 ° C. or lower and is a process at a temperature lower than the growth temperature of each layer of the semiconductor light emitting device 100. For this reason, the formation process of the control transistor 60 hardly affects the epitaxial film.

  Note that in the case where the gate electrode film is formed before the epitaxial growth step, the gate electrode film may be damaged due to damage or stress caused by subsequent heat treatment or etching treatment. Further, the threshold voltage Vth may vary.

  However, in the method for manufacturing the semiconductor light emitting device 1 according to the embodiment of the present invention, the film for the gate electrode is formed after the epitaxial growth step. For this reason, it is possible to suppress damage to the gate electrode film and fluctuation of the threshold voltage Vth due to stress during epitaxial growth.

<Modification>
In FIG. 1, an example in which the film thickness on the light emitting region 101 of the stacked body 20 is thicker than the film thickness on the driving device region 102 is shown. According to the structure shown in FIG. 1, the height of the semiconductor light emitting device 1 in the light emitting region 101 and the driving device region 102 can be made equal.

  However, as shown in FIG. 12, for example, the control transistor 60 is arranged on the p-type semiconductor layer 23 without removing a part of the upper part of the stacked body 20 in the driving device region 102 where the control transistor 60 is arranged. Also good. Thereby, the manufacturing process of the semiconductor light-emitting device 1 can be shortened.

  As mentioned above, although this invention was described by embodiment, it should not be understood that the description and drawing which form a part of this indication limit this invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art. Needless to say, the present invention includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor light-emitting device 10 ... Semiconductor substrate 11 ... Silicon substrate 12 ... Buffer layer 20 ... Laminate 21 ... N-type semiconductor layer 22 ... Active layer 23 ... P-type semiconductor layer 30 ... Transparent electrode 40 ... Interlayer insulating film 50 ... Light shielding film DESCRIPTION OF SYMBOLS 60 ... Control transistor 61 ... npn structure 62 ... Gate insulating film 63 ... Gate region 71 ... Wiring layer 100 ... Semiconductor light emitting element 101 ... Light emission region 102 ... Drive device region 111 ... Anode electrode 112 ... Cathode electrode 601 ... Drain electrode 602 ... Source Electrode 603 ... Gate electrode

Claims (8)

A semiconductor substrate having a light emitting region and a driving device region defined on the main surface;
An n-type semiconductor layer made of an epitaxially grown nitride semiconductor, an active layer, and a p-type semiconductor layer are sequentially arranged on the main surface of the semiconductor substrate from the light emitting region to the driving device region. A laminate having a structure laminated with;
An interlayer insulating film disposed on the laminate;
A control transistor disposed above the driving device region via at least a part of the stacked body and the interlayer insulating film, and controlling light emission in the stacked body;
A semiconductor light emitting device comprising: a light shielding film disposed between the control transistor and the stacked body in the interlayer insulating film.   2. The semiconductor light emitting device according to claim 1, wherein the light shielding film is disposed on a side surface and a bottom surface of the control transistor facing the stacked body.   3. The semiconductor light emitting device according to claim 1, wherein a film thickness of the stacked body on the light emitting region is larger than a film thickness on the driving device region.   4. The semiconductor light emitting device according to claim 3, wherein a film thickness of the stacked body is gradually increased from the driving device region toward the light emitting region. 5.   5. The semiconductor light-emitting device according to claim 1, wherein the control transistor has a structure in which a p-type region and an n-type region are adjacent to each other in a direction parallel to the main surface.   6. The semiconductor light emitting device according to claim 5, wherein the control transistor is a junction field effect transistor.   7. The wiring layer according to claim 6, further comprising a wiring layer disposed on the interlayer insulating film and connected to a source electrode of the control transistor and the p-type semiconductor layer through an opening provided in the interlayer insulating film. The semiconductor light-emitting device as described.   8. The semiconductor light emitting device according to claim 1, further comprising a transparent electrode disposed between the stacked body and the interlayer insulating film above the light emitting region and in contact with the p-type semiconductor layer. 9. apparatus.

Images