JP5849388B2 - Semiconductor light emitting device - Google Patents

Semiconductor light emitting device Download PDF

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JP5849388B2
JP5849388B2 JP2010247227A JP2010247227A JP5849388B2 JP 5849388 B2 JP5849388 B2 JP 5849388B2 JP 2010247227 A JP2010247227 A JP 2010247227A JP 2010247227 A JP2010247227 A JP 2010247227A JP 5849388 B2 JP5849388 B2 JP 5849388B2
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electrode
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JP2012099700A (en
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暢尚 杉森
暢尚 杉森
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Sanken Electric Co Ltd
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本発明は、n型半導体層、活性層及びp型半導体層が積層された構造の半導体発光装置に関する。   The present invention relates to a semiconductor light emitting device having a structure in which an n-type semiconductor layer, an active layer, and a p-type semiconductor layer are stacked.

発光ダイオード(LED)や半導体レーザなどの、n型半導体層、活性層及びp型半導体層が積層された構造の半導体発光装置において、発光効率の向上が図られている。例えば、p型半導体層上のほぼ全面に透光性のp側電極を形成し、更にp側電極上に絶縁膜を介して反射膜を形成した半導体発光装置が提案されている(例えば特許文献1参照。)。これにより、p側における反射率が向上し、基板側からの光取り出し効率が向上する。   In a semiconductor light-emitting device having a structure in which an n-type semiconductor layer, an active layer, and a p-type semiconductor layer are stacked, such as a light-emitting diode (LED) or a semiconductor laser, light emission efficiency is improved. For example, a semiconductor light emitting device has been proposed in which a light-transmitting p-side electrode is formed on almost the entire surface of a p-type semiconductor layer, and a reflective film is further formed on the p-side electrode via an insulating film (for example, Patent Documents). 1). Thereby, the reflectance on the p side is improved, and the light extraction efficiency from the substrate side is improved.

特許第4122785号公報Japanese Patent No. 4122785

上記の半導体発光装置では、n側電極が露出されたn型半導体層上全体に形成されるため、発光に寄与しない領域の面積が大きい。このため、基板面積に対する発光面積の比率が小さい。また、絶縁膜の上に反射層が形成される構造のために、反射層の耐湿性の点で問題がある。   In the above semiconductor light emitting device, since the n-side electrode is formed over the entire exposed n-type semiconductor layer, the area of the region that does not contribute to light emission is large. For this reason, the ratio of the light emission area to the substrate area is small. Further, since the reflective layer is formed on the insulating film, there is a problem in terms of moisture resistance of the reflective layer.

上記問題点に鑑み、本発明は、基板面積に対する発光面積の比率が高く、且つ反射層の耐湿性を向上した半導体発光装置を提供することを目的とする。   In view of the above problems, an object of the present invention is to provide a semiconductor light emitting device in which the ratio of the light emitting area to the substrate area is high and the moisture resistance of the reflective layer is improved.

本発明の一態様によれば、(イ)n型半導体層、活性層及びp型半導体層がこの順で積層された積層体と、(ロ)p型半導体層上に配置された透明電極と、(ハ)透明電極上に配置された電極絶縁膜と、(ニ)電極絶縁膜上に配置され、電極絶縁膜、透明電極、p型半導体層及び活性層を貫通して設けられたn側開口部でn型半導体層に接するn側電極と、(ホ)電極絶縁膜上にn側電極と離間して配置され、電極絶縁膜に設けられたストライプ状のp側開口部で透明電極に接するp側電極と、(ヘ)電極絶縁膜内部に、又は透明電極と電極絶縁膜との間に、積層体の上面に対向して配置され、活性層から出射された光を反射する反射層とを備え、n側開口部が、間口よりも底面が狭いテーパー形状を有し、n側電極の外縁部下方において、n側開口部の周囲を囲んで活性層、透明電極及び反射層が配置され 反射層が、n側開口部のテーパー形状の斜面に沿ってn側開口部の内側に配置された領域を有し、n側電極が、n側開口部のテーパー形状の斜面から底面に沿ってn側開口部の内側に配置された領域を有して、n側開口部の底面においてn型半導体層に接し、反射層とn側電極が異なる材料からなる半導体発光装置が提供される。 According to one aspect of the present invention, (a) a stacked body in which an n-type semiconductor layer, an active layer, and a p-type semiconductor layer are stacked in this order; and (b) a transparent electrode disposed on the p-type semiconductor layer; (C) an electrode insulating film disposed on the transparent electrode; and (d) an n-side disposed on the electrode insulating film and penetrating the electrode insulating film, the transparent electrode, the p-type semiconductor layer, and the active layer. An n-side electrode in contact with the n-type semiconductor layer at the opening, and (e) a transparent electrode with a striped p-side opening provided on the electrode insulating film, spaced apart from the n-side electrode. A p-side electrode that is in contact, and (f) a reflective layer that is disposed inside the electrode insulating film or between the transparent electrode and the electrode insulating film so as to face the upper surface of the multilayer body and reflects light emitted from the active layer The n-side opening has a tapered shape whose bottom is narrower than the frontage, and below the outer edge of the n-side electrode, Active layer surrounds the side opening is disposed the transparent electrode and the reflective layer, the reflective layer has a region disposed inside the n-side opening along the slope of the tapered shape of the n-side opening The n-side electrode has a region disposed inside the n-side opening along the bottom surface from the tapered slope of the n-side opening, and is in contact with the n-type semiconductor layer at the bottom of the n-side opening, A semiconductor light emitting device is provided in which the reflective layer and the n-side electrode are made of different materials .

本発明によれば、基板面積に対する発光面積の比率が高く、且つ反射層の耐湿性を向上した半導体発光装置を提供できる。   ADVANTAGE OF THE INVENTION According to this invention, the ratio of the light emission area with respect to a substrate area can be high, and the semiconductor light-emitting device which improved the moisture resistance of the reflection layer can be provided.

本発明の第1の実施形態に係る半導体発光装置の構成を示す模式的な断面図である。1 is a schematic cross-sectional view showing a configuration of a semiconductor light emitting device according to a first embodiment of the present invention. 本発明の第1の実施形態に係る半導体発光装置の構成を示す模式的な平面図である。1 is a schematic plan view showing a configuration of a semiconductor light emitting device according to a first embodiment of the present invention. 本発明の第1の実施形態に係る半導体発光装置の実装方法を示す模式的な断面図である。It is typical sectional drawing which shows the mounting method of the semiconductor light-emitting device concerning the 1st Embodiment of this invention. 本発明の第1の実施形態に係る半導体発光装置の製造方法を説明するための工程断面図である(その1)。It is process sectional drawing for demonstrating the manufacturing method of the semiconductor light-emitting device which concerns on the 1st Embodiment of this invention (the 1). 本発明の第1の実施形態に係る半導体発光装置の製造方法を説明するための工程断面図である(その2)。It is process sectional drawing for demonstrating the manufacturing method of the semiconductor light-emitting device which concerns on the 1st Embodiment of this invention (the 2). 本発明の第1の実施形態に係る半導体発光装置の製造方法を説明するための工程断面図である(その3)。It is process sectional drawing for demonstrating the manufacturing method of the semiconductor light-emitting device which concerns on the 1st Embodiment of this invention (the 3). 本発明の第1の実施形態に係る半導体発光装置の製造方法を説明するための工程断面図である(その4)。It is process sectional drawing for demonstrating the manufacturing method of the semiconductor light-emitting device which concerns on the 1st Embodiment of this invention (the 4). 本発明の第1の実施形態に係る半導体発光装置の製造方法を説明するための工程断面図である(その5)。It is process sectional drawing for demonstrating the manufacturing method of the semiconductor light-emitting device which concerns on the 1st Embodiment of this invention (the 5). 本発明の第1の実施形態に係る半導体発光装置の製造方法を説明するための工程断面図である(その6)。It is process sectional drawing for demonstrating the manufacturing method of the semiconductor light-emitting device which concerns on the 1st Embodiment of this invention (the 6). 本発明の第1の実施形態に係る半導体発光装置の他の実装方法を示す模式的な断面図である。It is typical sectional drawing which shows the other mounting method of the semiconductor light-emitting device concerning the 1st Embodiment of this invention. 本発明の第1の実施形態に係る半導体発光装置の他の構成を示す模式的な平面図である。FIG. 6 is a schematic plan view showing another configuration of the semiconductor light emitting device according to the first embodiment of the present invention. 本発明の第2の実施形態に係る半導体発光装置の構成を示す模式的な断面図である。It is typical sectional drawing which shows the structure of the semiconductor light-emitting device concerning the 2nd Embodiment of this invention. 本発明の第2の実施形態に係る半導体発光装置の製造方法を説明するための工程断面図である(その1)。It is process sectional drawing for demonstrating the manufacturing method of the semiconductor light-emitting device which concerns on the 2nd Embodiment of this invention (the 1). 本発明の第2の実施形態に係る半導体発光装置の製造方法を説明するための工程断面図である(その2)。It is process sectional drawing for demonstrating the manufacturing method of the semiconductor light-emitting device which concerns on the 2nd Embodiment of this invention (the 2). 本発明の第2の実施形態に係る半導体発光装置の製造方法を説明するための工程断面図である(その3)。It is process sectional drawing for demonstrating the manufacturing method of the semiconductor light-emitting device which concerns on the 2nd Embodiment of this invention (the 3). 本発明の第2の実施形態に係る半導体発光装置の製造方法を説明するための工程断面図である(その4)。It is process sectional drawing for demonstrating the manufacturing method of the semiconductor light-emitting device concerning the 2nd Embodiment of this invention (the 4). 本発明の第2の実施形態に係る半導体発光装置の製造方法を説明するための工程断面図である(その5)。It is process sectional drawing for demonstrating the manufacturing method of the semiconductor light-emitting device concerning the 2nd Embodiment of this invention (the 5).

図面を参照して、本発明の第1及び第2の実施形態を説明する。以下の図面の記載において、同一又は類似の部分には同一又は類似の符号を付している。ただし、図面は模式的なものであり、厚みと平面寸法との関係、各層の厚みの比率などは現実のものとは異なることに留意すべきである。したがって、具体的な厚みや寸法は以下の説明を参酌して判断すべきものである。又、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれていることはもちろんである。   First and second embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

又、以下に示す第1及び第2の実施形態は、この発明の技術的思想を具体化するための装置や方法を例示するものであって、この発明の実施形態は、構成部品の材質、形状、構造、配置などを下記のものに特定するものでない。この発明の実施形態は、特許請求の範囲において、種々の変更を加えることができる。   Further, the following first and second embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the embodiments of the present invention include the materials of components, The shape, structure, arrangement, etc. are not specified below. The embodiment of the present invention can be variously modified within the scope of the claims.

(第1の実施形態)
本発明の第1の実施形態に係る半導体発光装置1は、図1に示すように、n型半導体層21、活性層22及びp型半導体層23がこの順で積層された積層体20と、p型半導体層23上に配置された透明電極30と、透明電極30上に配置された電極絶縁膜40と、電極絶縁膜40上に配置され、電極絶縁膜40、透明電極30、p型半導体層23及び活性層22を貫通して設けられたn側開口部41でn型半導体層21に接するn側電極51と、電極絶縁膜40上に配置され、電極絶縁膜40に設けられたストライプ状のp側開口部43で透明電極30に接するp側電極53と、電極絶縁膜40内部に積層体20の上面に対向して配置された反射層70とを備える。反射層70は、活性層22から出射された光を積層体20側に反射する。n側電極51とp側電極53は、互いに離間して電極絶縁膜40上に配置されている。
(First embodiment)
As shown in FIG. 1, the semiconductor light emitting device 1 according to the first embodiment of the present invention includes a stacked body 20 in which an n-type semiconductor layer 21, an active layer 22, and a p-type semiconductor layer 23 are stacked in this order, The transparent electrode 30 disposed on the p-type semiconductor layer 23, the electrode insulating film 40 disposed on the transparent electrode 30, and the electrode insulating film 40, the transparent electrode 30, and the p-type semiconductor disposed on the electrode insulating film 40 An n-side electrode 51 in contact with the n-type semiconductor layer 21 through an n-side opening 41 provided through the layer 23 and the active layer 22 and a stripe provided on the electrode insulating film 40 and provided on the electrode insulating film 40 The p-side electrode 53 is in contact with the transparent electrode 30 through the p-shaped opening 43 and the reflective layer 70 is disposed inside the electrode insulating film 40 so as to face the upper surface of the stacked body 20. The reflective layer 70 reflects the light emitted from the active layer 22 to the stacked body 20 side. The n-side electrode 51 and the p-side electrode 53 are disposed on the electrode insulating film 40 so as to be separated from each other.

更に、図1に示した半導体発光装置1は、基板10上に配置されたバッファ層11上に、積層体20が配置された構造である。基板10のバッファ層11と接する面に対向する面である発光領域110から、出力光Lが半導体発光装置1の外部に放射される。   Furthermore, the semiconductor light emitting device 1 shown in FIG. 1 has a structure in which a stacked body 20 is disposed on a buffer layer 11 disposed on a substrate 10. The output light L is radiated to the outside of the semiconductor light emitting device 1 from the light emitting region 110 that is a surface facing the surface in contact with the buffer layer 11 of the substrate 10.

基板10は活性層22で発生する光を透過する材料からなり、例えばサファイア基板などを基板10に採用可能である。   The substrate 10 is made of a material that transmits light generated in the active layer 22. For example, a sapphire substrate can be used as the substrate 10.

バッファ層11は活性層22で発生する光を透過する材料からなり、例えば、AlxyGa1-x-yN(Mはインジウム(In)又はボロン(B)、0<x≦1、0≦y≦1、x+y=1)からなる第1のサブレイヤーと、AlaMbGa1-a-bN(MはIn又はB、0≦a<1、0≦b≦1、a+b=1、a<x)からなる第2のサブレイヤーとを交互に積層した多層構造を採用可能である。例えば、第1のサブレイヤーは膜厚0.5〜5nm程度の窒化アルミニウム(AlN)膜、第2のサブレイヤーは膜厚0.5〜200nm程度の窒化ガリウム(GaN)膜である。 Buffer layer 11 is made of a material that transmits the light generated in the active layer 22, for example, Al x M y Ga 1- xy N (M is indium (In) or boron (B), 0 <x ≦ 1,0 ≦ a first sublayer consisting of y.ltoreq.1, x + y = 1) and AlaMbGa1-a-bN (M is In or B, 0.ltoreq.a <1, 0.ltoreq.b.ltoreq.1, a + b = 1, a <x). It is possible to adopt a multilayer structure in which the second sublayers are alternately stacked. For example, the first sublayer is an aluminum nitride (AlN) film having a thickness of about 0.5 to 5 nm, and the second sublayer is a gallium nitride (GaN) film having a thickness of about 0.5 to 200 nm.

n型半導体層21は、例えばn型ドーパントとしてシリコン(Si)がドープされた膜厚5μm程度のGaN膜であり、活性層22に電子を供給する。p型半導体層23は、例えばp型ドーパントがドープされた膜厚0.2μm程度のGaN膜であり、活性層22に正孔(ホール)を供給する。p型ドーパントは、マグネシウム(Mg)、亜鉛(Zn)、カドミウム(Cd)、カルシウム(Ca)、ベリリウム(Be)、炭素(C)等である。   The n-type semiconductor layer 21 is, for example, a GaN film having a thickness of about 5 μm doped with silicon (Si) as an n-type dopant, and supplies electrons to the active layer 22. The p-type semiconductor layer 23 is, for example, a GaN film having a thickness of about 0.2 μm doped with a p-type dopant, and supplies holes to the active layer 22. The p-type dopant is magnesium (Mg), zinc (Zn), cadmium (Cd), calcium (Ca), beryllium (Be), carbon (C), or the like.

活性層22は、例えばInGaN膜とGaN膜を交互に積層した多重量子井戸(MQW)構造を有する。InGaN膜とGaN膜の膜厚は、それぞれ数μm〜数十μm程度である。n型半導体層21から供給された電子とp型半導体層23から供給された正孔とが活性層22で再結合して光を発生する。   The active layer 22 has, for example, a multiple quantum well (MQW) structure in which InGaN films and GaN films are alternately stacked. The film thicknesses of the InGaN film and the GaN film are about several μm to several tens of μm, respectively. Electrons supplied from the n-type semiconductor layer 21 and holes supplied from the p-type semiconductor layer 23 are recombined in the active layer 22 to generate light.

透明電極30及び電極絶縁膜40は、活性層22で発生する光が透過する材料からなる。透明電極30には、例えば酸化インジウム・スズ(ITO)膜などが採用可能である。ITO膜の膜厚は、50nm〜500nm程度である。電極絶縁膜40には、例えば膜厚150nm〜1500nm程度の酸化シリコン(SiO2)膜などが採用可能である。 The transparent electrode 30 and the electrode insulating film 40 are made of a material that transmits light generated in the active layer 22. For the transparent electrode 30, for example, an indium tin oxide (ITO) film can be employed. The thickness of the ITO film is about 50 nm to 500 nm. As the electrode insulating film 40, for example, a silicon oxide (SiO 2 ) film having a film thickness of about 150 nm to 1500 nm can be employed.

また、n側電極51及びp側電極53には、例えば金(Au)などが採用可能である。半導体発光装置1の外部の負電源から電子がn側電極51に供給され、正電源から正孔がp側電極53に供給される。   For the n-side electrode 51 and the p-side electrode 53, for example, gold (Au) can be used. Electrons are supplied to the n-side electrode 51 from a negative power source outside the semiconductor light emitting device 1, and holes are supplied to the p-side electrode 53 from the positive power source.

反射層70には、例えば銀パラジウム銅(APC)膜、Al膜などを採用可能である。活性層22から透明電極30方向に出射された光は、反射層70で反射され、出力光Lの一部として半導体発光装置1の外部に放射される。   For the reflective layer 70, for example, a silver palladium copper (APC) film, an Al film, or the like can be employed. The light emitted from the active layer 22 in the direction of the transparent electrode 30 is reflected by the reflective layer 70 and is emitted to the outside of the semiconductor light emitting device 1 as part of the output light L.

図1に示すように、反射層70は電極絶縁膜40の内部に埋め込まれている。例えば、電極絶縁膜40を途中まで形成した後に反射層70が形成され、反射層70上に残りの電極絶縁膜40が形成される。このため、反射層70の金属が長時間大気や純水等にさらされることがほとんどなく、水蒸気などによる反射層70の劣化を抑制できる。   As shown in FIG. 1, the reflective layer 70 is embedded in the electrode insulating film 40. For example, the reflective layer 70 is formed after the electrode insulating film 40 is formed halfway, and the remaining electrode insulating film 40 is formed on the reflective layer 70. For this reason, the metal of the reflective layer 70 is hardly exposed to the atmosphere, pure water, or the like for a long time, and deterioration of the reflective layer 70 due to water vapor or the like can be suppressed.

図2に、n側電極51及びp側電極53の側からみた半導体発光装置1の平面図を示す。図1は、図2のI−I方向に沿った断面図である。図2に示すように、n側電極51が配置された領域を除いて、半導体発光装置1の上面ほぼ全体にp側電極53が配置されている。p側電極53から、電極絶縁膜40に開口されたp側開口部43を介して、透明電極30に正孔が供給される。   FIG. 2 is a plan view of the semiconductor light emitting device 1 as viewed from the n-side electrode 51 and the p-side electrode 53 side. FIG. 1 is a cross-sectional view taken along the II direction of FIG. As shown in FIG. 2, the p-side electrode 53 is disposed on almost the entire top surface of the semiconductor light emitting device 1 except for the region where the n-side electrode 51 is disposed. Holes are supplied from the p-side electrode 53 to the transparent electrode 30 through the p-side opening 43 opened in the electrode insulating film 40.

図2において、n側電極51の内側に破線で示した領域が、n側電極51を透過してみたn側開口部41である。また、n側電極51の内側に示した一点鎖線は透明電極30の外縁を示し、一点鎖線の内側の領域には透明電極30が配置されていない。n側電極51の内側に示した二点鎖線は反射層70の外縁を示し、二点鎖線の内側の領域には反射層70が配置されていない。   In FIG. 2, a region indicated by a broken line inside the n-side electrode 51 is an n-side opening 41 through the n-side electrode 51. Further, the alternate long and short dash line shown inside the n-side electrode 51 indicates the outer edge of the transparent electrode 30, and the transparent electrode 30 is not disposed in the region inside the alternate long and short dash line. The two-dot chain line shown inside the n-side electrode 51 represents the outer edge of the reflective layer 70, and the reflective layer 70 is not disposed in the region inside the two-dot chain line.

図1及び図2に示すように、n側電極51は、n側開口部41の上方に配置されている。半導体発光装置1の上面に露出したn側電極51の領域は、例えばボンディング用パッドなどの、外部の負電源と電気的にコンタクトを取るための電極用パッドとして使用される。このため、n側電極51の面積は外部とのコンタクトに必要な大きさであればよい。n側電極51を電極用パッドとして使用するため、n型半導体層21に電子を供給するn側電極51とは別の電極用パッドを用意する必要がない。   As shown in FIGS. 1 and 2, the n-side electrode 51 is disposed above the n-side opening 41. The region of the n-side electrode 51 exposed on the upper surface of the semiconductor light emitting device 1 is used as an electrode pad for making electrical contact with an external negative power source such as a bonding pad. For this reason, the area of the n-side electrode 51 may be a size required for contact with the outside. Since the n-side electrode 51 is used as an electrode pad, it is not necessary to prepare an electrode pad different from the n-side electrode 51 that supplies electrons to the n-type semiconductor layer 21.

上記のように、半導体発光装置1では、n側電極51直下にのみ形成されたn側開口部41においてn側電極51とn型半導体層21とが接している。このため、半導体発光装置1の面積は増大せず、且つ活性層22から出射されて反射層70方向に進む光が透過する領域の減少が抑制される。   As described above, in the semiconductor light emitting device 1, the n-side electrode 51 and the n-type semiconductor layer 21 are in contact with each other in the n-side opening 41 formed only immediately below the n-side electrode 51. For this reason, the area of the semiconductor light emitting device 1 does not increase, and a decrease in the region through which light emitted from the active layer 22 and traveling in the direction of the reflective layer 70 is transmitted is suppressed.

なお、図1に示したように、n側開口部41における積層体20の開口領域は、側面が底面に対して傾斜しており、間口よりも底面が狭いテーパー形状である。このため、n側開口部41に露出した積層体20の側面部において電極絶縁膜40が薄くなることがなく、外部からの力による半導体発光装置1の破壊を防止できる。例えば、n側電極51にワイヤボンディングしても、ボンディング圧力によってn側開口部41が破壊されることがない。n側開口部41はn側電極51の下方に位置するため、もともと非発光領域であり、積層体20の開口領域をテーパー形状にしても発光領域が実質的に減少することはない。   As shown in FIG. 1, the opening area of the stacked body 20 in the n-side opening 41 has a tapered shape in which the side surface is inclined with respect to the bottom surface and the bottom surface is narrower than the frontage. For this reason, the electrode insulating film 40 does not become thin at the side surface portion of the stacked body 20 exposed at the n-side opening 41, and the semiconductor light emitting device 1 can be prevented from being broken by an external force. For example, even if the n-side electrode 51 is wire-bonded, the n-side opening 41 is not broken by the bonding pressure. Since the n-side opening 41 is located below the n-side electrode 51, it is originally a non-light emitting region, and even if the opening region of the stacked body 20 is tapered, the light emitting region is not substantially reduced.

図2では、ストライプ状の2本のp側開口部43が互いに並行に配置された例を示した。p側開口部43の本数は、透明電極30の面積などに応じて任意に設定可能である。例えば面積の広い透明電極30に正孔を供給する必要がある場合には、3本以上のp側開口部43を形成してもよい。一方、透明電極30の面積が狭い場合には、形成するp側開口部43が1本でもよい。   FIG. 2 shows an example in which two striped p-side openings 43 are arranged in parallel to each other. The number of p-side openings 43 can be arbitrarily set according to the area of the transparent electrode 30 and the like. For example, when it is necessary to supply holes to the transparent electrode 30 having a large area, three or more p-side openings 43 may be formed. On the other hand, when the area of the transparent electrode 30 is small, one p-side opening 43 may be formed.

p側開口部43は、p側電極53から供給される正孔が透明電極30の全域に供給されるように配置される。これにより、活性層22を流れる電流が均一化され、活性層22の広い範囲で光を発生させることができる。   The p-side opening 43 is arranged so that holes supplied from the p-side electrode 53 are supplied to the entire area of the transparent electrode 30. Thereby, the current flowing through the active layer 22 is made uniform, and light can be generated in a wide range of the active layer 22.

例えば図2に示したように、2本配置されたp側開口部43それぞれの端部からp側電極53のコーナー部までの距離d11は、同一の長さであることが好ましい。また、各p側開口部43の端部からn側開口部41近傍の透明電極30の外縁までの距離d12は、同一の長さであることが好ましい。このようにp側開口部43を配置することにより、透明電極30の全域にムラなく正孔が供給され、活性層22を流れる電流が均一化される。   For example, as shown in FIG. 2, the distance d11 from the end of each of the two p-side openings 43 arranged to the corner of the p-side electrode 53 is preferably the same length. The distance d12 from the end of each p-side opening 43 to the outer edge of the transparent electrode 30 in the vicinity of the n-side opening 41 is preferably the same length. By arranging the p-side opening 43 in this way, holes are supplied uniformly throughout the transparent electrode 30, and the current flowing through the active layer 22 is made uniform.

上記に説明した半導体発光装置1とは異なり、活性層22を流れる電流を均一化するためにn型半導体層21の全域に電子を供給する場合には、半導体発光装置1の上面の広い範囲に、n側電極51を配置する必要がある。例えば櫛の歯形状にn側電極51を配置する。この場合、深い掘り込み溝であるn側開口部41を半導体発光装置1の上面の広い範囲に形成する必要がある。また、n側開口部41の内壁に電極絶縁膜40を形成するため、n側開口部41の幅を広くする必要がある。   Unlike the semiconductor light emitting device 1 described above, when electrons are supplied to the entire area of the n-type semiconductor layer 21 in order to make the current flowing through the active layer 22 uniform, the semiconductor light emitting device 1 has a wide area on the upper surface. The n-side electrode 51 needs to be disposed. For example, the n-side electrode 51 is arranged in a comb tooth shape. In this case, it is necessary to form the n-side opening 41 which is a deep digging groove in a wide range on the upper surface of the semiconductor light emitting device 1. In addition, since the electrode insulating film 40 is formed on the inner wall of the n-side opening 41, the width of the n-side opening 41 needs to be increased.

一方、図1及び図2に示した半導体発光装置1によれば、パターニングされたp側開口部43を介して、p側電極53から透明電極30の全域に正孔が供給され、活性層22に電流が均一に流れる。このため、n側開口部41の面積を小さくできる。なお、p側開口部43の深さは電極絶縁膜40の膜厚分でよい。更にp側開口部43の幅は、p側電極53と透明電極30とが接触できる程度でよく、p側開口部43の内側に絶縁膜を形成するために広くする必要もない。   On the other hand, according to the semiconductor light emitting device 1 shown in FIGS. 1 and 2, holes are supplied from the p-side electrode 53 to the entire area of the transparent electrode 30 through the patterned p-side opening 43, and the active layer 22. Current flows uniformly. For this reason, the area of the n-side opening 41 can be reduced. Note that the depth of the p-side opening 43 may be the thickness of the electrode insulating film 40. Further, the width of the p-side opening 43 may be such that the p-side electrode 53 and the transparent electrode 30 can be in contact with each other, and does not need to be widened in order to form an insulating film inside the p-side opening 43.

活性層22で発生した光が基板10方向に反射されないn側開口部41の面積が、半導体発光装置1の非発光領域の面積に影響する。つまり、n側開口部41の面積が大きいほど、発光領域110のうちで光度の高い出力光Lが放射される有効面積が減少する。したがって、第1の実施形態に係る半導体発光装置1によれば、n側開口部41の面積を小さくできるため、半導体発光装置1上面に広くn側電極51を配置する場合に比べて発光に寄与する領域の面積減少を抑制しつつ、活性層22を流れる電流を均一化できる。つまり、第1の実施形態に係る半導体発光装置1によれば、有効に出力光Lが放射される発光領域110の面積の減少が抑制される。   The area of the n-side opening 41 where the light generated in the active layer 22 is not reflected in the direction of the substrate 10 affects the area of the non-light emitting region of the semiconductor light emitting device 1. That is, as the area of the n-side opening 41 is larger, the effective area of the light emitting region 110 where the output light L having a high luminous intensity is radiated decreases. Therefore, according to the semiconductor light emitting device 1 according to the first embodiment, since the area of the n-side opening 41 can be reduced, it contributes to light emission as compared with the case where the n-side electrode 51 is widely disposed on the upper surface of the semiconductor light emitting device 1. The current flowing through the active layer 22 can be made uniform while suppressing the area reduction of the region to be performed. That is, according to the semiconductor light emitting device 1 according to the first embodiment, a reduction in the area of the light emitting region 110 where the output light L is effectively emitted is suppressed.

更に、図1、図2に示すように、第1の実施形態に係る半導体発光装置1では、n側開口部41が設けられた領域の残余の領域において、活性層22、p型半導体層23、透明電極30及び反射層70がn側電極51の下方に配置されている。このようにn側電極51の外縁部下方にも透明電極30及び反射層70を配置することによって、活性層22から出射された光がn側電極51の下方でも反射される。したがって、n側電極51の外縁部ぎりぎりまでを半導体発光装置1の発光に寄与する領域にできる。つまり、n側開口部41が配置された領域以外のほぼ全域が発光に寄与する領域である。その結果、半導体発光装置1について基板面積に対する発光面積の比率を更に高くできる。このため、活性層22で発生した光をより効率的に外部に放射することができ、より大きな光度を得られる。   Further, as shown in FIGS. 1 and 2, in the semiconductor light emitting device 1 according to the first embodiment, the active layer 22 and the p-type semiconductor layer 23 in the remaining region of the region where the n-side opening 41 is provided. The transparent electrode 30 and the reflective layer 70 are disposed below the n-side electrode 51. As described above, by arranging the transparent electrode 30 and the reflective layer 70 also below the outer edge of the n-side electrode 51, the light emitted from the active layer 22 is reflected also below the n-side electrode 51. Therefore, the region that contributes to the light emission of the semiconductor light emitting device 1 can be made up to the very edge of the n-side electrode 51. That is, almost the entire region other than the region where the n-side opening 41 is disposed is a region contributing to light emission. As a result, the ratio of the light emitting area to the substrate area of the semiconductor light emitting device 1 can be further increased. For this reason, the light generated in the active layer 22 can be radiated to the outside more efficiently, and a greater luminous intensity can be obtained.

また、図1に示した半導体発光装置1とは異なり、半導体発光装置1上面に広くn側電極51を配置する場合には、深い掘り込み溝であるn側開口部41に沿って配置されるn側電極51を電流の引き回しに使用することになる。このために、n側開口部41の角部に電流が集中する。その結果、n側開口部41の角部でプラスの静電気による静電気放電(ESD)破壊が生じる可能性が高いという問題がある。   In addition, unlike the semiconductor light emitting device 1 shown in FIG. 1, when the n-side electrode 51 is widely disposed on the upper surface of the semiconductor light emitting device 1, it is disposed along the n-side opening 41 that is a deep digging groove. The n-side electrode 51 is used for current routing. For this reason, current concentrates on the corners of the n-side opening 41. As a result, there is a problem that electrostatic discharge (ESD) breakdown due to positive static electricity is likely to occur at the corner of the n-side opening 41.

しかし、第1の実施形態に係る半導体発光装置1では、p側開口部43によって電流が引き回される。このため、n側電極51と距離をとって透明電極30に電流が分散され、電極の一部に電流が集中することがない。したがって、ESDに対して破壊に至りやすい場所がなく、結果として半導体発光装置1のESD耐性が向上する。   However, in the semiconductor light emitting device 1 according to the first embodiment, a current is drawn by the p-side opening 43. For this reason, the current is distributed to the transparent electrode 30 at a distance from the n-side electrode 51, and the current does not concentrate on a part of the electrode. Therefore, there is no place that is easily damaged by ESD, and as a result, the ESD resistance of the semiconductor light emitting device 1 is improved.

図1に示した半導体発光装置1は、例えば図3に示すように実装基板80に搭載されるフリップチップ型である。即ち、n側電極51及びp側電極53が実装基板80上の電源配線パターンに接して、半導体発光装置1が実装基板80上に搭載されている。   The semiconductor light emitting device 1 shown in FIG. 1 is a flip chip type mounted on a mounting substrate 80 as shown in FIG. 3, for example. That is, the n-side electrode 51 and the p-side electrode 53 are in contact with the power supply wiring pattern on the mounting substrate 80, and the semiconductor light emitting device 1 is mounted on the mounting substrate 80.

負電極領域81と正電極領域83からなる電源配線パターンが、実装基板80上に形成されている。半導体発光装置1のn側電極51及びp側電極53が配置される領域は、半導体発光装置1が搭載される実装基板80の電源配線パターンに対応して設定される。例えば金スズ(Au−Sn)などの共晶半田を用いて半導体発光装置1と実装基板80とを接続する場合に、任意の実装基板80の電源配線パターンに合わせて、n側電極51及びp側電極53のパターン配置が決定される。そして、負電極領域81にn側電極51が接し、正電極領域83にp側電極53が接するように、半導体発光装置1が実装基板80に搭載される。   A power supply wiring pattern including a negative electrode region 81 and a positive electrode region 83 is formed on the mounting substrate 80. The region where the n-side electrode 51 and the p-side electrode 53 of the semiconductor light emitting device 1 are disposed is set corresponding to the power supply wiring pattern of the mounting substrate 80 on which the semiconductor light emitting device 1 is mounted. For example, when the semiconductor light emitting device 1 and the mounting substrate 80 are connected using eutectic solder such as gold tin (Au—Sn), the n-side electrode 51 and the p-side electrode 51 and the p-type electrode are connected to the power wiring pattern of the arbitrary mounting substrate 80. The pattern arrangement of the side electrode 53 is determined. Then, the semiconductor light emitting device 1 is mounted on the mounting substrate 80 so that the n-side electrode 51 is in contact with the negative electrode region 81 and the p-side electrode 53 is in contact with the positive electrode region 83.

実装基板80の負電極領域81から供給される電子が、n側電極51を介して、n型半導体層21に供給される。実装基板80の正電極領域83から供給される正孔が、p側電極53を介して、p型半導体層23に供給される。これらの電子と正孔が活性層22で再結合して光が発生する。   Electrons supplied from the negative electrode region 81 of the mounting substrate 80 are supplied to the n-type semiconductor layer 21 through the n-side electrode 51. Holes supplied from the positive electrode region 83 of the mounting substrate 80 are supplied to the p-type semiconductor layer 23 through the p-side electrode 53. These electrons and holes are recombined in the active layer 22 to generate light.

既に述べたように、活性層22で発生して基板10方向に進行する光は、バッファ層11及び基板10を透過して、基板10の発光領域110から出力光Lの一部として半導体発光装置1の外部に放射される。そして、活性層22で発生して透明電極30方向に出射された光は、反射層70で基板10方向に反射される。反射層70で反射した光は、基板10の発光領域110から出力光Lの一部として外部に放射される。   As already described, the light generated in the active layer 22 and traveling in the direction of the substrate 10 is transmitted through the buffer layer 11 and the substrate 10, and as a part of the output light L from the light emitting region 110 of the substrate 10, the semiconductor light emitting device. 1 is radiated to the outside. The light generated in the active layer 22 and emitted in the direction of the transparent electrode 30 is reflected in the direction of the substrate 10 by the reflective layer 70. The light reflected by the reflective layer 70 is radiated to the outside as a part of the output light L from the light emitting region 110 of the substrate 10.

図1、図3に示したように、n側電極51の表面とp側電極53の表面とは、同一平面レベルにある。つまり、半導体発光装置1の実装基板80と接する面にはほとんど段差がない。このため、半導体発光装置1を実装基板80に実装する場合に、バンプや導電性物質によってn側電極51の高さとp側電極53の高さを調整する必要がない。したがって、実装基板80に半導体発光装置1を容易に実装することができる。   As shown in FIGS. 1 and 3, the surface of the n-side electrode 51 and the surface of the p-side electrode 53 are on the same plane level. That is, there is almost no step on the surface of the semiconductor light emitting device 1 that is in contact with the mounting substrate 80. For this reason, when the semiconductor light emitting device 1 is mounted on the mounting substrate 80, it is not necessary to adjust the height of the n-side electrode 51 and the height of the p-side electrode 53 with bumps or conductive materials. Therefore, the semiconductor light emitting device 1 can be easily mounted on the mounting substrate 80.

なお、半導体発光装置1と実装基板80との接触面積が広いために、半導体発光装置1の放熱性も良好である。   Since the contact area between the semiconductor light emitting device 1 and the mounting substrate 80 is wide, the heat dissipation of the semiconductor light emitting device 1 is also good.

以上に説明したように、第1の実施形態に係る半導体発光装置1によれば、p側電極53から、電極絶縁膜40に開口されたp側開口部43を介して、透明電極30の全域に正孔が供給される。このため、活性層22を流れる電流が均一化される。一方、n側電極51が配置された領域の面積は小さく、且つ、n側電極51直下のn側開口部41が形成された領域以外は積層体20が除去されず、n側電極51下方に透明電極30及び反射層70が配置されている。このため、半導体発光装置1における基板面積に対する発光面積の比率は高い。   As described above, according to the semiconductor light emitting device 1 according to the first embodiment, the entire region of the transparent electrode 30 is passed from the p-side electrode 53 through the p-side opening 43 opened in the electrode insulating film 40. Are supplied with holes. For this reason, the current flowing through the active layer 22 is made uniform. On the other hand, the area of the region where the n-side electrode 51 is arranged is small, and the stacked body 20 is not removed except in the region where the n-side opening 41 just below the n-side electrode 51 is formed. The transparent electrode 30 and the reflective layer 70 are disposed. For this reason, the ratio of the light emitting area to the substrate area in the semiconductor light emitting device 1 is high.

更に、半導体発光装置1の反射層70を電極絶縁膜40の内部に埋め込むことにより、反射層70の耐湿性を向上することができる。   Furthermore, by embedding the reflective layer 70 of the semiconductor light emitting device 1 inside the electrode insulating film 40, the moisture resistance of the reflective layer 70 can be improved.

図4〜図9を参照して、図1に示した半導体発光装置1の製造方法を説明する。なお、以下に述べる半導体発光装置1の製造方法は一例であり、この変形例を含めて、これ以外の種々の製造方法により実現可能であることは勿論である。   A method for manufacturing the semiconductor light emitting device 1 shown in FIG. 1 will be described with reference to FIGS. In addition, the manufacturing method of the semiconductor light-emitting device 1 described below is an example, and it is needless to say that it can be realized by various other manufacturing methods including this modification.

(イ)先ず、基板10上にバッファ層11を形成する。バッファ層11上に、n型半導体層21、活性層22及びp型半導体層23を順次に積層して、図4に示すように積層体20を形成する。   (A) First, the buffer layer 11 is formed on the substrate 10. On the buffer layer 11, an n-type semiconductor layer 21, an active layer 22, and a p-type semiconductor layer 23 are sequentially stacked to form a stacked body 20 as shown in FIG.

(ロ)p型半導体層23上に透明電極30を形成する。なお、n側開口部41が形成される領域の透明電極30を削除するために、フォトリソグラフィ技術などを用いて透明電極30を図5に示すようにパターニングする。   (B) The transparent electrode 30 is formed on the p-type semiconductor layer 23. In order to delete the transparent electrode 30 in the region where the n-side opening 41 is formed, the transparent electrode 30 is patterned as shown in FIG. 5 using a photolithography technique or the like.

(ハ)図6に示すように、n側開口部41が形成される領域のp型半導体層23、活性層22、及びn型半導体層21の上部の一部を除去し、積層体20の開口領域410を形成する。このとき、図6に示すように開口領域410がテーパー形状をなすように、積層体20の上部の一部を除去する。   (C) As shown in FIG. 6, the p-type semiconductor layer 23, the active layer 22, and the upper part of the n-type semiconductor layer 21 in the region where the n-side opening 41 is formed are removed, and the stacked body 20 An opening region 410 is formed. At this time, as shown in FIG. 6, a part of the upper portion of the stacked body 20 is removed so that the opening region 410 has a tapered shape.

(ニ)図7に示すように、透明電極30上に電極絶縁膜40の下層部分401を形成する。次いで、下層部分401上に反射層70を形成する。   (D) As shown in FIG. 7, a lower layer portion 401 of the electrode insulating film 40 is formed on the transparent electrode 30. Next, the reflective layer 70 is formed on the lower layer portion 401.

(ホ)n側開口部41及びp側開口部43を配置する領域の反射層70及び下層部分401を、フォトリソグラフィ技術などを用いて除去する。次いで、反射層70及び下層部分401上に電極絶縁膜40の上層部分402を形成する。そして、図8に示すように、n側開口部41及びp側開口部43を配置する領域の上層部分402を除去する。なお、先ず反射層70のみ除去し、上層部分402を形成後に上層部分402と下層部分401を同時に除去してもよい。   (E) The reflective layer 70 and the lower layer portion 401 in the region where the n-side opening 41 and the p-side opening 43 are disposed are removed using a photolithography technique or the like. Next, the upper layer portion 402 of the electrode insulating film 40 is formed on the reflective layer 70 and the lower layer portion 401. And as shown in FIG. 8, the upper layer part 402 of the area | region which arrange | positions the n side opening part 41 and the p side opening part 43 is removed. Note that only the reflective layer 70 may be removed first, and the upper layer portion 402 and the lower layer portion 401 may be simultaneously removed after the upper layer portion 402 is formed.

(ヘ)電極絶縁膜40に形成したn側開口部41及びp側開口部43を埋め込むようにして、電極絶縁膜40上に金属膜を形成する。その後、図9に示すように金属膜をパターニングして、n側電極51及びp側電極53を形成する。これにより、図1に示す半導体発光装置1が完成する。   (F) A metal film is formed on the electrode insulating film 40 so as to bury the n-side opening 41 and the p-side opening 43 formed in the electrode insulating film 40. Thereafter, as shown in FIG. 9, the metal film is patterned to form the n-side electrode 51 and the p-side electrode 53. Thereby, the semiconductor light emitting device 1 shown in FIG. 1 is completed.

なお、n側電極51とp側電極53のパターン配置を変更するだけで、基板10から出力光Lを出射する図1に示したフリップチップ型の半導体発光装置1と、透明電極30及び電極絶縁膜40を透過した出力光を出射する上面発光型の半導体発光装置とを作り分けることができる。つまり、n側電極51及びp側電極53を形成するための金属膜のマスクを変更し、反射層70の形成工程の有無を選択するだけで、フリップチップ型の半導体発光装置1と上面発光型の半導体発光装置とを選択的に製造することができる。このため、工程共有化の効果を得ることが容易である。   Note that the flip-chip type semiconductor light emitting device 1 shown in FIG. 1 that emits the output light L from the substrate 10, the transparent electrode 30, and the electrode insulation can be obtained simply by changing the pattern arrangement of the n-side electrode 51 and the p-side electrode 53. A top-emitting semiconductor light-emitting device that emits output light that has passed through the film 40 can be made separately. That is, the flip chip type semiconductor light emitting device 1 and the top emission type light emitting device can be selected simply by changing the mask of the metal film for forming the n side electrode 51 and the p side electrode 53 and selecting whether or not the reflective layer 70 is formed. The semiconductor light emitting device can be selectively manufactured. For this reason, it is easy to obtain the process sharing effect.

<変形例>
図10に示すように、バンプ91、93によって半導体発光装置1と実装基板80とを接続してもよい。電源配線パターンの負電極領域81上に配置されたバンプ91とn側電極51が接し、正電極領域83上に配置されたバンプ93とp側電極53が接する。
<Modification>
As shown in FIG. 10, the semiconductor light emitting device 1 and the mounting substrate 80 may be connected by bumps 91 and 93. The bump 91 disposed on the negative electrode region 81 of the power supply wiring pattern and the n-side electrode 51 are in contact with each other, and the bump 93 disposed on the positive electrode region 83 is in contact with the p-side electrode 53.

また、第1の実施形態に係る半導体発光装置1では掘り込み溝を形成する必要がないため、半導体発光装置1のn側開口部41の面積は小さい。このため、特にn側電極51を配置する位置の自由度が高い。したがって、実装基板80の電源配線パターンに応じて、任意の位置にn側電極51を配置できる。   Further, in the semiconductor light emitting device 1 according to the first embodiment, it is not necessary to form a digging groove, so that the area of the n-side opening 41 of the semiconductor light emitting device 1 is small. For this reason, the freedom degree of the position which arrange | positions the n side electrode 51 especially is high. Therefore, the n-side electrode 51 can be arranged at an arbitrary position according to the power supply wiring pattern of the mounting substrate 80.

図11に、図2と異なるn側電極51及びp側電極53の配置例を示す。図2ではn側開口部41が1つ配置される例を示したが、図11は3つのn側開口部41が配置される例を示した。図11では、3つのn側開口部41を覆って帯状にn側電極51が配置されている。そして、n側電極51の両側にp側電極53が配置されている。   FIG. 11 shows an arrangement example of the n-side electrode 51 and the p-side electrode 53 which is different from that in FIG. Although FIG. 2 shows an example in which one n-side opening 41 is arranged, FIG. 11 shows an example in which three n-side openings 41 are arranged. In FIG. 11, the n-side electrode 51 is arranged in a band shape covering the three n-side openings 41. A p-side electrode 53 is disposed on both sides of the n-side electrode 51.

(第2の実施形態)
本発明の第2の実施形態に係る半導体発光装置1は、図12に示すように、透明電極30と電極絶縁膜40の間に反射層70が配置されていることが、電極絶縁膜40内部に反射層70が配置された図1に示す半導体発光装置1と異なる点である。その他の構成については、図1に示す第1の実施形態と同様である。
(Second Embodiment)
In the semiconductor light emitting device 1 according to the second embodiment of the present invention, the reflection layer 70 is disposed between the transparent electrode 30 and the electrode insulating film 40 as shown in FIG. 1 is different from the semiconductor light emitting device 1 shown in FIG. Other configurations are the same as those of the first embodiment shown in FIG.

即ち、n側電極51直下のn側開口部41が形成された領域以外は積層体20が除去されず、n側電極51下方に透明電極30及び反射層70が配置されている。このため、図12に示した半導体発光装置1における基板面積に対する発光面積の比率は高い。   That is, the stacked body 20 is not removed except in the region where the n-side opening 41 directly under the n-side electrode 51 is formed, and the transparent electrode 30 and the reflective layer 70 are disposed below the n-side electrode 51. For this reason, the ratio of the light emitting area to the substrate area in the semiconductor light emitting device 1 shown in FIG. 12 is high.

また、図12に示すように、反射層70を覆うように電極絶縁膜40を形成することによって、水蒸気などによる反射層70の劣化を抑制できる。このため、反射層70の耐湿性が向上する。   Also, as shown in FIG. 12, by forming the electrode insulating film 40 so as to cover the reflective layer 70, deterioration of the reflective layer 70 due to water vapor or the like can be suppressed. For this reason, the moisture resistance of the reflective layer 70 is improved.

図13〜図17を参照して、本発明の第2の実施形態に係る半導体発光装置1の製造方法を説明する。なお、以下に述べる半導体発光装置1の製造方法は一例であり、この変形例を含めて、これ以外の種々の製造方法により実現可能であることは勿論である。   A method for manufacturing the semiconductor light emitting device 1 according to the second embodiment of the present invention will be described with reference to FIGS. In addition, the manufacturing method of the semiconductor light-emitting device 1 described below is an example, and it is needless to say that it can be realized by various other manufacturing methods including this modification.

(イ)図4〜図5を参照して説明した方法と同様にして、基板10、バッファ層11及び積層体20を積層した後、p型半導体層23上に透明電極30を形成する。その後、図13に示すように、n側開口部41が形成される領域には配置されないようにパターニングされた透明電極30上に、反射層70を積層する。このとき、例えばチタン(Ti)膜と酸化シリコン膜からなる保護層75を反射層70上に形成することにより、反射層70が保護される。   (A) In the same manner as described with reference to FIGS. 4 to 5, the substrate 10, the buffer layer 11, and the stacked body 20 are stacked, and then the transparent electrode 30 is formed on the p-type semiconductor layer 23. Then, as shown in FIG. 13, the reflective layer 70 is laminated | stacked on the transparent electrode 30 patterned so that it may not be arrange | positioned in the area | region in which the n side opening part 41 is formed. At this time, the reflective layer 70 is protected by forming the protective layer 75 made of, for example, a titanium (Ti) film and a silicon oxide film on the reflective layer 70.

(ロ)n側開口部41が形成される領域のp型半導体層23、活性層22、及びn型半導体層21の上部の一部を除去し、積層体20の開口領域410を形成する。このとき、図14に示すように開口領域410がテーパー形状をなすように、積層体20の上部の一部を除去する。   (B) The p-type semiconductor layer 23, the active layer 22, and a part of the upper portion of the n-type semiconductor layer 21 in the region where the n-side opening 41 is formed are removed to form the opening region 410 of the stacked body 20. At this time, as shown in FIG. 14, a part of the upper part of the stacked body 20 is removed so that the opening region 410 has a tapered shape.

(ハ)図15に示すように、積層体20及び保護層75の上面に電極絶縁膜40を形成する。   (C) As shown in FIG. 15, the electrode insulating film 40 is formed on the upper surfaces of the stacked body 20 and the protective layer 75.

(ニ)図16に示すように、n側開口部41及びp側開口部43を配置する領域の電極絶縁膜40を、フォトリソグラフィ技術などを用いて除去する。このとき、p側開口部43の底面に露出する保護層75も除去する。p側開口部43の底面に露出する反射層70は、除去しても残してもよい。   (D) As shown in FIG. 16, the electrode insulating film 40 in the region where the n-side opening 41 and the p-side opening 43 are disposed is removed using a photolithography technique or the like. At this time, the protective layer 75 exposed on the bottom surface of the p-side opening 43 is also removed. The reflective layer 70 exposed on the bottom surface of the p-side opening 43 may be removed or left.

(ホ)電極絶縁膜40に形成したn側開口部41及びp側開口部43を埋め込むようにして、電極絶縁膜40上に金属膜を形成する。その後、図17に示すように金属膜をパターニングして、n側電極51及びp側電極53を形成する。以上により、図12に示した半導体発光装置1が完成する。   (E) A metal film is formed on the electrode insulating film 40 so as to bury the n-side opening 41 and the p-side opening 43 formed in the electrode insulating film 40. Thereafter, as shown in FIG. 17, the metal film is patterned to form the n-side electrode 51 and the p-side electrode 53. Thus, the semiconductor light emitting device 1 shown in FIG. 12 is completed.

本発明の第2の実施形態に係る半導体発光装置1によれば、基板面積に対する発光面積の比率が高く、且つ反射層70の耐湿性を向上した半導体発光装置を提供することができる。他は、実施形態と実質的に同様であり、重複した記載を省略する。   According to the semiconductor light emitting device 1 according to the second embodiment of the present invention, it is possible to provide a semiconductor light emitting device in which the ratio of the light emitting area to the substrate area is high and the moisture resistance of the reflective layer 70 is improved. Others are substantially the same as those in the embodiment, and redundant description is omitted.

上記のように、本発明は実施形態によって記載したが、この開示の一部をなす論述及び図面はこの発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施形態、実施例及び運用技術が明らかとなろう。本発明はここでは記載していない様々な実施形態などを含むことは勿論である。したがって、本発明の技術的範囲は上記の説明から妥当な特許請求の範囲に係る発明特定事項によってのみ定められるものである。   As mentioned above, although this invention was described by embodiment, it should not be understood that the description and drawing which form a part of this indication limit this invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art. Needless to say, the present invention includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

1…半導体発光装置
10…基板
11…バッファ層
20…積層体
21…n型半導体層
22…活性層
23…p型半導体層
30…透明電極
40…電極絶縁膜
41…n側開口部
43…p側開口部
51…n側電極
53…p側電極
70…反射層
80…実装基板
81…負電極領域
83…正電極領域
91、93…バンプ
110…発光領域
DESCRIPTION OF SYMBOLS 1 ... Semiconductor light-emitting device 10 ... Board | substrate 11 ... Buffer layer 20 ... Laminated body 21 ... N-type semiconductor layer 22 ... Active layer 23 ... P-type semiconductor layer 30 ... Transparent electrode 40 ... Electrode insulating film 41 ... N side opening part 43 ... p Side opening 51 ... n-side electrode 53 ... p-side electrode 70 ... reflection layer 80 ... mounting substrate 81 ... negative electrode region 83 ... positive electrode region 91, 93 ... bump 110 ... light emitting region

Claims (3)

n型半導体層、活性層及びp型半導体層がこの順で積層された積層体と、
前記p型半導体層上に配置された透明電極と、
前記透明電極上に配置された電極絶縁膜と、
前記電極絶縁膜上に配置され、前記電極絶縁膜、前記透明電極、前記p型半導体層及び前記活性層を貫通して設けられたn側開口部で前記n型半導体層に接するn側電極と、
前記電極絶縁膜上に前記n側電極と離間して配置され、前記電極絶縁膜に設けられたストライプ状のp側開口部で前記透明電極に接するp側電極と、
前記電極絶縁膜内部に、又は前記透明電極と前記電極絶縁膜との間に、前記積層体の上面に対向して配置され、前記活性層から出射された光を反射する反射層と
を備え、
前記n側開口部が、間口よりも底面が狭いテーパー形状を有し、
前記n側電極の外縁部下方において、前記n側開口部の周囲を囲んで前記活性層、前記透明電極及び前記反射層が配置され
前記反射層が、前記n側開口部の前記テーパー形状の斜面に沿って前記n側開口部の内側に配置された領域を有し、
前記n側電極が、前記n側開口部の前記テーパー形状の前記斜面から底面に沿って前記n側開口部の内側に配置された領域を有して、前記n側開口部の前記底面において前記n型半導体層に接し、
前記反射層と前記n側電極が異なる材料からなる
ことを特徴とする半導体発光装置。
a stacked body in which an n-type semiconductor layer, an active layer, and a p-type semiconductor layer are stacked in this order;
A transparent electrode disposed on the p-type semiconductor layer;
An electrode insulating film disposed on the transparent electrode;
An n-side electrode disposed on the electrode insulating film and in contact with the n-type semiconductor layer at an n-side opening provided through the electrode insulating film, the transparent electrode, the p-type semiconductor layer, and the active layer; ,
A p-side electrode disposed on the electrode insulating film and spaced apart from the n-side electrode, and in contact with the transparent electrode at a striped p-side opening provided in the electrode insulating film;
A reflective layer that is disposed inside the electrode insulating film or between the transparent electrode and the electrode insulating film so as to face the upper surface of the multilayer body and reflects light emitted from the active layer;
The n-side opening has a tapered shape whose bottom is narrower than the frontage,
Below the outer edge portion of the n-side electrode, the active layer, the transparent electrode, and the reflective layer are disposed around the periphery of the n-side opening ,
The reflective layer has a region disposed inside the n-side opening along the tapered slope of the n-side opening,
The n-side electrode has a region disposed on the inner side of the n-side opening along the bottom surface from the tapered slope of the n-side opening, and at the bottom surface of the n-side opening, in contact with the n-type semiconductor layer,
The semiconductor light emitting device, wherein the reflective layer and the n-side electrode are made of different materials .
前記p側電極が、互いに並行して配置された複数のストライプ状の前記p側開口部で前記透明電極に接することを特徴とする請求項1に記載の半導体発光装置。   The semiconductor light emitting device according to claim 1, wherein the p-side electrode is in contact with the transparent electrode at the plurality of stripe-shaped p-side openings arranged in parallel to each other. 前記n側電極の表面と前記p側電極の表面とが同一平面レベルにあることを特徴とする請求項1又は2に記載の半導体発光装置。   3. The semiconductor light emitting device according to claim 1, wherein the surface of the n-side electrode and the surface of the p-side electrode are at the same plane level.
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CN102456796B (en) 2014-09-03

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