JP7398794B2 - Semiconductor light emitting device array - Google Patents

Description

The present invention relates to a semiconductor light emitting element array, and more particularly to the integration of a monolithic micro LED array in which a light emitting section and a driving circuit are integrated. A monolithic micro LED array is an arrangement in which minute (10 to 100 μm square) LED cells are integrated and arranged in a two-dimensional matrix.

LED is a type of solid-state device that converts electrical energy into light, and includes an active layer interposed between an n-type semiconductor layer and a p-type semiconductor layer, and when a voltage is applied between the two doped layers, When carriers such as electrons and holes concentrate in the active layer and recombine within the active layer, the energy becomes smaller than the energy they each had, and the excess energy generated at that time is converted into light energy. It uses the principle of emitting light. LEDs are characterized by being able to be driven with relatively low voltage and generating low heat due to high energy efficiency. LEDs are manufactured in various types, and among these various types, a monolithic micro LED array is one in which a plurality of micro LED pixels are formed on one wafer (see Patent Document 1).

Monolithic micro LED arrays are characterized by high brightness and low power consumption, and are attracting a lot of attention as next-generation display elements to replace LCD (liquid crystal display) and OLED (organic electroluminescent) displays, and the market will rapidly expand in the future. It is predicted that it will rise. Monolithic micro LED arrays are expected to be used not only in display applications, but also in a wide range of fields such as projection type projectors, automobile lighting, and display devices.Furthermore, LED lighting has features such as no mercury content and a long lifespan. It is believed that in the future, it will replace traditional street lighting such as incandescent, fluorescent, and high-pressure sodium lamps. Under these circumstances, there is a growing movement to commercialize projection equipment that uses monolithic micro LEDs as light sources. Monolithic micro LEDs are self-luminous devices like OLEDs, so they share the same features of superior light utilization efficiency and the ability to maintain a high contrast ratio, but they are also superior in terms of high luminous efficiency and long life. . Coupled with the advantages of high brightness, low power consumption, and high definition, there is a growing movement to expand the applications of projection devices that use monolithic micro LEDs as light sources (see Patent Document 2).

When manufacturing a monolithic micro LED array by forming multiple micro LED pixels on one wafer, conventionally, two terminals, a p-pole and an n-pole, are formed on each pixel through the chip manufacturing process, and then the signal line is They were arranged and driven along the vertical and horizontal axes. In this case, a problem arises in that a large number of drive current application wirings coexist for each micro LED pixel, resulting in an increase in the size of the monolithic micro LED array. In order to miniaturize the device, it is necessary to make the driving current application wiring thinner, but there is a concern that the wiring may break due to electromigration.

JP2013-211443 Publication JP2016-110131 Publication JP2017-80963 Publication

In an LED display, individually manufactured LED chips are arranged in a two-dimensional matrix during mounting, and drive current application wiring is required to supply current to each LED chip. When integrating LED chips to form an LED array, there is a problem in that a large number of driving current application wirings are mixed together, and as the number of LED cells increases, the wiring length becomes long, making it difficult to miniaturize. Up to now, it has been proposed to miniaturize the LED array chip and each wiring material by using separate substrates and connecting them through electrode pads that face each other (see Patent Document 3).

However, in monolithic micro LEDs, as further integration progresses and the number of LED cells increases, a large number of wiring lines for applying driving current are mixed together, the wiring length becomes long, and the wiring becomes thinner for integration. It becomes necessary. The need for high-intensity light emission requires a large amount of current to be supplied to the LED, and if an attempt is made to improve the resolution by increasing the degree of integration of the LED, the current density flowing through the wiring will increase significantly. Simple metal fine interconnects are concerned about the effects of electromigration caused by high-density current. Electromigration is a phenomenon in which metal atoms in the wiring move when current (electrons) flows through the metal wiring inside an IC. Vacancies are created when electrons collide with metal atoms, and if the metal atoms are crowded together under certain conditions, the wiring will break. There is a concern that the reliability of such interconnects will deteriorate, which poses a major problem in realizing devices.

The present invention has been made in view of the above points, and its purpose is to provide a semiconductor light emitting element array that solves wiring problems caused by high current density.

Therefore, as a result of extensive research, the present inventors propose supplying current to the LED with a drive circuit using a vertical structure in order to maintain wiring reliability even at high current density. By making the current path to the LED perpendicular to the substrate, there is no need to use fine wiring on the substrate. A monolithic micro LED array can be integrated by integrally forming the board on which the light emitting part of the monolithic micro LED array is mounted and the board on which the drive circuit part, which has a control signal circuit and a drive circuit configured separately, are integrated without wiring. It is possible to solve wiring problems such as deterioration of wiring reliability due to high current density, which is a problem when using high current density.

That is, the semiconductor light emitting element array of the present invention is a semiconductor light emitting element array that includes a light emitting section in which a plurality of semiconductor light emitting elements are two-dimensionally arranged, and a switching section in which a plurality of semiconductor switching elements are two-dimensionally arranged. The light emitting section has a plurality of semiconductor light emitting elements formed on a first semiconductor substrate, first and second drive electrodes for driving the semiconductor light emitting elements on the surface of the first semiconductor substrate, and a first semiconductor light emitting element. A light emitting surface is provided on the back surface of the first semiconductor substrate. In the switching section, a plurality of semiconductor switching elements are formed on a second semiconductor substrate, and each of the plurality of semiconductor switching elements allows a current to flow between first and second electrodes and between the first and second electrodes. It has a third electrode that turns ON/OFF, the first and third electrodes of the semiconductor switching element are formed on the surface of the second semiconductor substrate, and the second electrode of the semiconductor switching element is formed on the surface of the second semiconductor substrate. Formed on the back side.

A first drive electrode of the semiconductor light emitting element formed on the surface of the first semiconductor substrate and a first electrode of the semiconductor switching element formed on the surface of the second semiconductor substrate are arranged to face each other, The predetermined first drive electrode of the semiconductor light emitting element formed on the surface of the first semiconductor substrate and the predetermined first electrode of the semiconductor switching element formed on the surface of the second semiconductor substrate are electrically connected to each other. It is connected.

In the present invention, it is configured as a monolithic micro LED array with an integrated drive circuit, and includes a first semiconductor substrate on which a plurality of semiconductor light emitting elements are formed, and a second semiconductor substrate on which a plurality of semiconductor switching elements are formed. By directly electrically connecting opposing electrodes using flip-chip bonding or the like, the wiring length for driving current within a monolithic micro LED array chip can be significantly shortened due to LED integration. This makes it possible to create a structure in which a reduction in drive current due to an increase in wiring resistance caused by a change in wiring resistance can be suppressed.

FIG. 2 is a schematic diagram of a micro LED array and an LED drive current control circuit board according to an embodiment. It is a circuit diagram for driving a micro LED array (8×8). FIG. 3 is a driving circuit diagram for one pixel. FIG. 3 is a schematic diagram of the LED array substrate (first substrate) after mesa etching. FIG. 2 is a schematic diagram of an LED array substrate (first substrate) after B (boron) ion implantation. It is a schematic diagram of an LED drive board (second board). These are the measurement results of external quantum efficiency. This is the ID-VDS characteristic of nMOSFET. This is the ID-VGS characteristic of nMOSFET. This is the ID-VDS characteristic of VMOSFET. This is the ID-VGS characteristic of VMOSFET.

Embodiments of the present invention will be described below based on the drawings. FIG. 1 schematically shows the main part configuration of an LED array integrated board. The first semiconductor substrate 1 has a plurality of semiconductor light emitting elements formed in a light emitting section on the substrate. A first drive electrode 3 and a second drive electrode 4 for driving a semiconductor light emitting element are provided on the front surface of the first semiconductor substrate, and a light emitting surface 5 is provided on the back surface of the first semiconductor substrate. A switching section is formed in the second semiconductor substrate 2, and this switching section includes a plurality of semiconductor switching elements 20 (vertical structure VMOSFET or UMOSFET) and semiconductor control elements 21 (nMOSFET). It is formed of semiconductor switching cells.

A first semiconductor substrate 1 and a second semiconductor substrate 2 on which a plurality of semiconductor switching elements are formed are arranged with their surfaces facing each other, and there is a gap between the facing first drive electrode 3 and second electrode 7. are directly electrically connected using flip-chip bonding or the like, and an LED drive current 22 is supplied from the second semiconductor substrate to the LED array of the first semiconductor substrate.

FIG. 2 shows an example of a circuit of the semiconductor light emitting element array of the present invention, and FIG. 3 shows an example of a driving circuit for one pixel. In the semiconductor light emitting element array, the plurality of semiconductor switching cells are two-dimensionally arranged in m rows and n columns (where m and n are natural numbers of 2 or more), and the second semiconductor control element of the plurality of semiconductor switching cells is A first control voltage is applied to m electrodes 10 (see FIG. 1) in each row. A second control voltage is applied to n third electrodes 11 (see FIG. 1) in each row of the semiconductor control elements of the plurality of semiconductor switching cells.

Next, the configuration of each substrate will be described in detail as an example.
A GaN substrate is used as the first semiconductor substrate 1, and a plurality of semiconductor light emitting elements are formed in the light emitting section 5 on the substrate. A first drive electrode (hereinafter sometimes referred to as "LED array drive electrode") 3 and a second drive electrode 4 for driving a semiconductor light emitting element is provided on the surface of a first semiconductor substrate, A light emitting surface 5 is provided on the back surface of the first semiconductor substrate. 4 and 5 show the substrate of the LED array. FIG. 4 is a schematic diagram after mesa etching, and FIG. 5 is a schematic diagram after B (boron) ion implantation. This will be explained with reference to FIG. Because of the need to increase the size of the electrode for integration with MOSFET, a GaN-micro LED array with a B (boron) ion implantation structure was used. In manufacturing the GaN-micro LED array with the B ion implantation structure, in this example, a general LED process was used for etching and electrode formation. A 2-inch GaN-LED wafer with a wavelength of 460 nm grown on a sapphire substrate (PSS) was used as the substrate. In the substrate, the p-type GaN layer 102 has a thickness of 300 nm, the InGaN layer 103 has a thickness of 100 nm, the n-type GaN layer 104 has a thickness of 5 μm, and the sapphire layer 105 has a thickness of 400 μm. The manufacturing process using this substrate is shown below.

A GaN-LED wafer on a sapphire substrate was diced into 10 mm square chips by blade dicing. Thereafter, as a process pretreatment, organic cleaning using acetone and cleaning using SPM (sulfuric acid peroxide) were performed. To form the mesa structure, photolithography is performed using a positive resist THMR-iP3100 (manufactured by Tokyo Ohka Kogyo Co., Ltd.), and n-type resist is formed using ICP-RIE (Inductive Coupled Plasma-Reactive Ion Etching) for element isolation. GaN layer 104 is exposed. Since the total thickness of the p-type GaN layer 102 and the InGaN layer 103 was 400 nm, etching was performed for 3 minutes so that the etching depth exceeded 500 nm. After etching, the actual value using the step system was 650 nm, and the etching rate was 3.61 nm/min.

The protective film for B ion implantation was formed using LP-CVD (Low-Pressure Chemical Vapor Deposition) in order to protect the ice surface due to ion collision during ion implantation and to prevent nitrogen loss during annealing to restore crystallinity after ion implantation. 50 nm of SiO ₂ was deposited using the following method. For B ion implantation, photolithography was performed using a positive resist OFPR8600 52cp (manufactured by Tokyo Ohka Co., Ltd.), and ions were implanted into the exposed p-type GaN region. During ion implantation, an 8-inch Si wafer is used as a handling wafer, and the GaN-LED substrate is pressed and fixed with a Si chip. After ion implantation, the resist is removed by SPM. The resist could be easily peeled off by soaking it in SPM for 30 minutes.

Regarding crystallinity recovery annealing, crystallinity recovery annealing was performed in an _N2 atmosphere after ion implantation. In order to compare the activation of B ions, annealing was performed at temperatures of 700° C. and 1000° C. for 5 minutes each. Regarding the formation of the n-electrode 101 and the p-electrode 100, a material that can make contact with the p-type and n-type GaN layers was selected as the metal. In addition, in order to extract light from the sapphire substrate side, the film thickness was designed to prevent transmission. After photolithography was performed using a negative resist AZ5214E (manufactured by Clariant) to remove resist residue and natural oxide film, Ti (30 nm) was deposited as an electrode of the n-type GaN layer 104 using an electron beam vacuum evaporation system. )/Al (30 nm)/Ti (30 nm)/Au (50 nm) were deposited. Thereafter, an electrode pattern was formed through a lift-off process using acetone. Using the same procedure, Ni (5 nm)/Ag (150 nm)/Ni (20 nm)/Au (30 nm) were deposited as electrodes of the p-type GaN layer 102.

This will be explained with reference to FIG. FIG. 5 is a schematic diagram after B ion implantation. Although a mesa structure was formed by etching the p-type layer, if there is a step on the LED surface due to mesa etching, cream solder required for bonding may flow to the n-electrode 101 side, causing leakage current, or Since the ground area of the junction with the p-electrode 100 is small, there are concerns such as poor heat dissipation. Furthermore, it becomes difficult to deposit a metal reflective film on the interface between the p-electrode 100 and the MOSFET. Therefore, a micro LED array with a flat structure was fabricated using B (boron) ion implantation 106. Conventionally, it was not possible to make the size of the p-electrode 100 larger than the mesa region, but with the B ion-implanted structure, this restriction is no longer present, so the size of the p-electrode 100 can be increased and the p-electrode 100 itself used as a reflective film. Using. Furthermore, as the size of the p-electrode increased, the ground area increased and heat dissipation improved. External quantum efficiency measurements were performed on the B ion-implanted GaN-micro LED array using a prober system and a photodiode. Note that FIG. 7 shows the external quantum efficiency measurement results. Light emission from the chip was confirmed when current was injected. External quantum efficiency is the ratio of the number of photons coming out of the LED chip or package to the number of electrons (current) flowing through the LED.

FIG. 6 shows a schematic diagram of the LED driving board. To explain with reference to FIG. 1, the second semiconductor substrate 2 is a Si substrate, and the switching section on the substrate consists of a pair of semiconductor switching element 20 (vertical structure VMOSFET) and semiconductor control element 21 (nMOSFET). A plurality of semiconductor switching cells (see FIGS. 2 and 3) are formed. As the driving method, we adopted an active matrix method, which is used for driving organic LEDs (OLEDs) and has low power consumption and is suitable for high definition. A driving circuit for one pixel is composed of two transistors: a switching transistor 207 and a driving transistor 206. For the drive transistor, we used a power MOSFET that can flow a larger current than a planar MOSFET, and among these, we adopted a V-groove trench gate MOSFET (VMOSFET), which is suitable for miniaturization. When a voltage is applied to the gate of the VMOSFET, a channel is formed directly under the gate, and an LED drive current 22 flows vertically from the drain to the source. Therefore, the channel area can be made larger than that of the planar type, and a large current can flow. The feature of this drive circuit is that, as mentioned above, the second electrode 7 and the drive electrode 3 of the LED array are directly connected, so that current is supplied directly from the VMOSFET to the LED array without using wiring. .

For forming the V-groove trench gate type MOSFET, a p-/n+-Si substrate was used because a power MOSFET in which the current path is perpendicular to the substrate cannot be realized on a bulk Si substrate. An epitaxial substrate was used in which a boron-doped Si-p- layer 204 was epitaxially grown on an antimony-doped Si-n+ substrate 203. This is a substrate with a two-layer structure in which p--Si is formed by epitaxial growth on an n+-Si wafer.

Before performing a MOSFET manufacturing process on the Si layer, it is necessary to remove organic substances, metal ions, etc. adhering to the substrate surface. Therefore, in the present invention, after forming alignment marks, organic substances and metal ions were removed by SPM, contamination was removed by HPM (hydrochloric acid peroxide), and natural oxide film treatment was performed using dilute hydrofluoric acid. A similar cleaning process was also performed before each oxide film deposition process and before the impurity diffusion process in order to reduce impurities at the Si interface. Furthermore, since KOH (potassium hydroxide) was used to form the gate portion (V groove) in the gate oxidation pretreatment, there was a concern about K contamination, so cleaning with HPM was performed. Integrating MOSFETs on the same substrate requires electrical insulation between each element. Therefore, thermal oxidation was performed on the Si layer for 180 min. A field oxide film (SiO ₂ ) 202 was grown to a thickness of about 600 nm.

After the field oxide film is grown, an active region (n+ region) 15 is required to drive the MOSFET. Therefore, we used photolithography to open a window to form an active region. After resist coating, the resist was removed from areas other than the exposed areas by exposure, development, and rinsing. Thereafter, a plasma dry cleaner was used to make the oxide film surface hydrophilic, and BHF (buffered hydrofluoric acid) was used to remove the oxide film that would become the active region. Thereafter, phosphorus (P) as an impurity was diffused in a phosphorus diffusion furnace to form an active region.

In order to form a V-type trench in the gate portion of the VMOSFET, an oxide film (SiO ₂ ) 201 of about 300 nm is deposited by LP-CVD as a mask during etching. Thereafter, photolithography is performed to pattern the opening of the V-groove. Thereafter, a plasma dry cleaner was used to make the oxide film surface hydrophilic, and BHF was used to remove the oxide film that would become the gate region. Thereafter, the resist used in patterning was removed by SPM treatment, and the resist was removed at 55°C with a 20wt. % KOH aqueous solution for 25 minutes to form a V-groove at the gate portion.

After the mask LP-CVD oxide film used for forming the V-groove in the gate portion was completely removed using BHF, pre-oxidation cleaning was performed. In the present invention, K contamination on the gate surface was removed by performing cleaning with boiled ultrapure water and HPM twice. Thereafter, the gate oxide film 16 is heated at 900°C/60min. by a wet oxidation method. By doing so, an oxide film of about 100 nm was deposited.

In order to make contact between the active region and the Al--Si electrode, patterning was performed by photolithography, and the oxide film was removed using BHF. Thereafter, the resist used in patterning was removed by SPM processing, and Al--Si was evaporated to a thickness of about 1 μm over the entire surface of the chip using a multi-target sputterer.

Al--Si deposited by multi-target sputtering was patterned by photolithography, and etched using a mixed solution of H ₃ PO ₄ , CH ₃ COOH, and HNO ₃ . As a result, unnecessary metal other than the Al--Si electrode and the wiring portion was removed. Thereafter, organic cleaning was performed to remove the resist used in patterning.

Since the VMOSFET manufactured according to the present invention requires the drain electrode 8 to be formed on the back surface of the chip, a resist was applied as a front protective film on the chip surface, and then Al was evaporated to a thickness of about 300 nm by resistance heating. Thereafter, the protective resist was removed by organic cleaning.

FIG. 8 shows the output characteristics of the fabricated nMOSFET, and FIG. 9 shows the transfer characteristics. The output characteristics of an ideal n-type MOSFET can be seen, and the drain current can be controlled by the gate voltage. FIG. 10 shows the ID-VDS characteristics of the manufactured VMOSFET, and FIG. 11 shows the ID-VGS characteristics. Since it can be seen from FIG. 10 that the drain current is controlled by the gate voltage, the realization of VMOSFET operation has been achieved. Next, it can be seen from the graph that the targeted current value of 20 mA was achieved at VGS=5V and VDS=4V, and the targeted allowable current was achieved.

As explained above, the required characteristics of the first semiconductor substrate 1 and the second semiconductor substrate 2 are satisfied, and the opposing electrodes are directly electrically connected using flip chip bonding or the like. By doing so, it becomes possible to create a structure that supplies drive current to the LED array without using fine wiring. Further, in the above embodiment, a VMOSFET is used as the semiconductor switching element, but a UMOSFET having a vertical structure may also be used.

Note that the above-described embodiments and examples show examples of the present invention, and the present invention is not limited to these configurations. Therefore, the first substrate 1 and the second substrate 2 It is possible to make appropriate changes to the manufacturing process.

1 First semiconductor substrate (GaN substrate)
2 Second semiconductor substrate (Si substrate)
3 First drive electrode (anode)
4 Second drive electrode (cathode)
5 LED light emitting surface 6 First electrode (semiconductor switching element)
7 Second electrode (semiconductor switching element)
8 Third electrode (semiconductor switching element)
9 First electrode (semiconductor control element)
10 Second electrode (semiconductor control element)
11 Third electrode (semiconductor control element)
12 p layer 13 n layer 15 n+ region 16 gate oxide film 20 semiconductor switching element 21 semiconductor control element 22 LED drive current 100 p electrode 101 n electrode 102 p-GaN layer 103 In-GaN layer 104 n-GaN layer 105 Sapphire layer 106 B ion implantation 201 SiO ₂ layer 202 SiO ₂ layer 203 n+ layer 204 p- layer 206 VMOS section 207 nMOS section

Claims (4)

A semiconductor light emitting element array consisting of a light emitting part in which a plurality of semiconductor light emitting elements are arranged two-dimensionally, and a switching part in which a plurality of semiconductor switching elements are arranged two-dimensionally,
The light emitting section has a plurality of semiconductor light emitting elements formed on a first semiconductor substrate, first and second drive electrodes for driving the semiconductor light emitting elements on the surface of the first semiconductor substrate, and a first semiconductor light emitting element. 1 has a light emitting surface on the back surface of the semiconductor substrate;
In the switching section, a plurality of semiconductor switching elements are formed on a second semiconductor substrate, and each of the plurality of semiconductor switching elements allows a current to flow between first and second electrodes and between the first and second electrodes. It has a third electrode that turns ON/OFF, the first and third electrodes of the semiconductor switching element are formed on the surface of the second semiconductor substrate, and the second electrode of the semiconductor switching element is formed on the surface of the second semiconductor substrate. formed on the back side,
A first drive electrode of a semiconductor light emitting element formed on the surface of the first semiconductor substrate and a first electrode of the semiconductor switching element formed on the surface of the second semiconductor substrate are arranged to face each other,
The predetermined first drive electrode of the semiconductor light emitting element formed on the surface of the first semiconductor substrate and the predetermined first electrode of the semiconductor switching element formed on the surface of the second semiconductor substrate are electrically connected to each other. A semiconductor light emitting element array characterized in that the semiconductor light emitting elements are connected. A semiconductor light emitting element array comprising a light emitting part in which a plurality of semiconductor light emitting elements are arranged two-dimensionally, and a switching part in which a plurality of semiconductor switching cells are arranged two-dimensionally,
The light emitting section has a plurality of semiconductor light emitting elements formed on a first semiconductor substrate, first and second drive electrodes for driving the semiconductor light emitting elements on the surface of the first semiconductor substrate, and a first semiconductor light emitting element. 1 has a light emitting surface on the back surface of the semiconductor substrate;
In the switching section, a plurality of semiconductor switching cells each including a pair of vertically structured semiconductor switching elements and semiconductor control elements (nMOS) are formed on a second semiconductor substrate, and each semiconductor switching element is connected to a first and a second semiconductor switching element. It has an electrode and a third electrode that turns on/off a current flowing between the first and second electrodes, the first and third electrodes of the semiconductor switching element are formed on the surface of the second semiconductor substrate, The second electrode of the semiconductor switching element is formed on the back surface of the second semiconductor substrate,
The semiconductor control element has first and second electrodes and a third electrode that controls the potential difference between the first and second electrodes, and the first, second and third electrodes are connected to the second semiconductor substrate. The first electrode of the semiconductor control element and the third electrode of the semiconductor switching element are electrically connected, and the third electrode and second electrode of the semiconductor control element are connected to the first and second electrodes, respectively. Connected to the control line of 2,
A first drive electrode of a semiconductor light emitting element formed on a surface of a first semiconductor substrate and a first electrode of a semiconductor switching element formed on a surface of a second semiconductor substrate are arranged to face each other, and A predetermined first drive electrode of a semiconductor light emitting element formed on a surface of a semiconductor substrate and a predetermined first electrode of a semiconductor switching element formed on a surface of a second semiconductor substrate are electrically connected. A semiconductor light emitting element array characterized by: In the semiconductor light emitting element array, the plurality of semiconductor switching cells are two-dimensionally arranged in m rows and n columns (where m and n are natural numbers of 2 or more), and the second semiconductor control element of the plurality of semiconductor switching cells is A first control voltage is applied to m electrodes in each column, and a second control voltage is applied to n third electrodes in each row of the semiconductor control elements of the plurality of semiconductor switching cells. The semiconductor light emitting device array according to claim 1 or 2, characterized in that: 4. The semiconductor light emitting device according to claim 1, wherein the potential applied to the second electrode of the semiconductor switching element is a positive power supply voltage, and the second drive electrode of the semiconductor light emitting element is at a ground potential. element array.

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