KR20200087881A - Method of forming a p-type layer for a light emitting device - Google Patents

Abstract

In a method according to embodiments of the present invention, a semiconductor structure is grown that includes a III-nitride light emitting layer disposed between a p-type region and an n-type region. The p-type region is embedded in the semiconductor structure. The trench is formed in a semiconductor structure. The trench exposes the p-type region. After forming the trench, the semiconductor structure is annealed.

Description

METHOD OF FORMING A P-TYPE LAYER FOR A LIGHT EMITTING DEVICE

Cross reference to related applications

This application claims priority to U.S. Provisional Patent Application No. 62/339,448 filed on May 20, 2016 and European Patent Application No. 16179661.0 filed on July 15, 2016. U.S. Provisional Patent Application Nos. 62/339,448 and European Patent Applications No. 16179661.0 are incorporated herein.

Including light emitting diodes (LEDs), resonant cavity light emitting diodes (RCLEDs), vertical cavity laser diodes (VCSELs), and edge emitting lasers Semiconductor light emitting devices are currently available among the most efficient light sources. Material systems currently of interest in the manufacture of high-brightness light emitting devices capable of operating across the visible spectrum are also referred to as III-nitride materials, Group III-V semiconductors, especially binary, 3, gallium, aluminum, indium, and nitrogen. Circle, and quaternary alloys. Typically, III-nitride light emitting devices are sapphire, silicon by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or other epitaxial techniques. It is prepared by epitaxially growing a stack of semiconductor layers of different compositions and dopant concentrations on carbide, III-nitride, or other suitable substrate. The stack is, for example, one or more n-type layers doped with Si, often formed on a substrate, one or more light emitting layers in an active region formed over an n-type layer or layers, and for example Mg formed over an active region And one or more p-type layers doped with. Electrical contacts are formed on the n- and p-type regions.

In commercial III-nitride LEDs, semiconductor structures are typically grown by MOCVD. The nitrogen source used during MOCVD is typically ammonia. When ammonia dissociates, hydrogen is produced. Hydrogen forms a complex with magnesium, and magnesium is used as a p-type dopant during the growth of p-type materials. The hydrogen complex inactivates the p-type properties of magnesium, effectively reducing the dopant concentration of the p-type material and reducing the efficiency of the device. After the growth of the p-type material, the structure is annealed to break the hydrogen-magnesium complex by blocking hydrogen.

1 illustrates a portion of a semiconductor structure that includes buried p-type regions and trenches for activating the p-type regions.
FIG. 2 illustrates a portion of the top surface of the structure illustrated in FIG. 1.
3 is a method of forming a device having a buried p-type region, according to some embodiments of the invention.
4 illustrates an LED with a p-type region grown before the n-type region, according to some embodiments of the invention.
5 illustrates an LED comprising a tunnel junction, according to some embodiments of the invention.
6 illustrates a device comprising two LEDs separated by a tunnel junction, according to some embodiments of the invention.
7 illustrates a portion of a partially grown semiconductor device that includes segments of a mask material.
8 illustrates a portion of a semiconductor device with embedded trenches.
9 illustrates a portion of a semiconductor device including a trench in which metal contacts are disposed.

The requirement of annealing in an anhydrous atmosphere to activate the p-type layers in the III-nitride device limits the device design. It has been experimentally demonstrated that hydrogen cannot diffuse through n-type III-nitride materials and hydrogen does not readily diffuse laterally through the semiconductor material over distances corresponding to half the diameter of a typical device wafer. As a result, in order for the activation annealing to be effective, the p-type layers cannot be covered by any other layer. Without effective annealing, the device remains without a p-type layer, or with a p-type layer with an extremely low dopant concentration, rendering it useless. Thus, devices with embedded p-type layers, such as devices with tunnel junctions or devices where p-type layers are grown before n-type layers, will be formed by annealing after conventional processes involving growth by MOCVD. Can't.

In embodiments of the invention, the device structure is grown with a buried p-type layer. Trenches are formed in the device structure exposing portions of the buried p-type layer. The structure is then annealed so that hydrogen can diffuse laterally from the buried p-type layer into trenches and hydrogen can escape around.

1 illustrates a portion of a semiconductor device structure. The structure of FIG. 1 is grown on growth substrate 30, which may be, for example, sapphire, SiC, Si, non-III-nitride material, GaN, composite substrate, or any other suitable substrate. Optional III-nitride film 102 may be grown before p-type region 100, but III-nitride film 102 is not required. III-nitride film 102 may be, for example, nucleation or buffer layers, smoothing layers, n-type layers, luminescent or active layers, undoped layers, devices that may be GaN or any other III-nitride material. The active region, and/or any other suitable layers or materials.

The p-type region 100 includes at least one binary, ternary, quaternary, or 5-membered III-nitride layer doped with a p-type dopant, eg, Mg or any other suitable material. .

III-nitride film 104 is grown after p-type layer 100 such that p-type layer 100 is embedded by III-nitride film 104. III-nitride film 104 may include n-type layers, p-type layers, an active region of the device, light emitting layers, undoped layers, and/or any other suitable layers or materials.

After or during growth, trenches 106 are formed in the semiconductor structure. The trenches 106 can extend through the entire thickness of the III-nitride film 104 such that the bottom ends of the trenches 106 are in the p-type region 100, as illustrated in FIG. 1. Alternatively, the trenches 106 may have a III-nitride film such that the bottom ends of the trenches 106 are in the III-nitride film 102, the surface of the growth substrate 30, or extend into the growth substrate 30. 104) and p-type regions 100 may extend through the entire thickness.

The width 108 of the trenches 106 is, for example, at least 0.05 μm in some embodiments, 50 μm or less in some embodiments, at least 0.5 μm in some embodiments, and 15 μm in some embodiments It may be: In some embodiments, trenches are kept as small as possible to avoid losing the luminous area.

The trenches 106 are spaced so that all of the p-type region 100 is spaced a distance from the trench that is less than or equal to the maximum diffusion length of hydrogen during later annealing. The maximum spacing 110 between trenches 106 may be twice the average or maximum diffusion length of hydrogen during annealing. The spacing 110 can be determined by the conditions of the annealing, which can determine the maximum lateral diffusion length of hydrogen during annealing-different anneals can have different maximum lateral diffusion lengths. The maximum spacing 110 between the nearest neighboring trenches may be at least 1 μm in some embodiments, 500 μm or less in some embodiments, at least 5 μm in some embodiments, and 250 μm or less in some embodiments have.

The semiconductor structure illustrated in FIG. 1 may be annealed after forming trenches 106. During annealing, hydrogen is pushed from the p-type region 100 into the trenches 106, which can escape from the semiconductor structure to the surroundings.

In some embodiments, after annealing, trenches 106 may be filled with insulating material 114. The insulating material 114 allows the metal contact to be formed on the surface with the trenches without accidentally causing a short. The insulating material 114 may be formed at any stage of processing after annealing-for example, the trenches 106 may be removed before or after removing the growth substrate, in embodiments in which the growth substrate is removed, or In embodiments where etching is performed, it may be filled with insulating material 114 before or after etching to expose the buried layer.

In some embodiments, trenches 106 are used as vias where metal contacts are formed to contact the p-type region in the device below the p-side, as illustrated in FIG. 9. In embodiments where metal contacts 134 are formed in trenches 106 in contact with p-type region 100, a series of metals and insulators are provided with a metal contact (a trench (as illustrated in FIG. 9). It is deposited and patterned to directly contact only the buried p-type region 100 (in the bottom of 132) or other desired layer, and not in direct contact with the layers (III-nitride film 104). For example, the insulating material 130 can be disposed on the sidewalls of the trench between the contact metal 134 and semiconductor layers that are not in direct contact with the metal contact.

In some embodiments, trenches 106 are left exposed to air or ambient gas, or coated with a thin passivation layer (eg, SiO ₂ ) rather than being filled. Thus, in some embodiments, trenches 106 may be partially or wholly filled with an insulating or passivating material.

2 is a top view of a portion of the top surface 112 of the structure of FIG. 1. As illustrated in FIG. 2, in some embodiments, trenches 106 are insulated from each other and may be surrounded by a portion of the semiconductor structure that is not interrupted by the trench. Thus, in some embodiments, the semiconductor material is all electrically connected, and no electrically isolated islands of semiconductor material are formed by the trenches 106. In some embodiments, some or all trenches may be connected to each other to form isolated islands of semiconductor material-for example, in some embodiments, trenches 106 are later separated from the wafer of semiconductor material. You can define the boundaries of a single device. A single device formed on a wafer of devices is defined as boundaries of the device or some trenches connected to each other to define an isolated island of semiconductor material within the device, and one or more other formed in an isolated island of semiconductor material isolated from each other. You can have a trench.

3 illustrates a method of forming a device. In block 120, a III-nitride structure with a buried p-type region is grown on a growth substrate.

At block 122, trenches 106 are formed in the grown III-nitride structure. Trenches 106 are illustrated in FIGS. 1 and 2. The trenches 106 can be formed by any suitable technique, including, for example, dry etching, wet etching, or a combination of dry and wet etching. In some embodiments, the method of forming the trench can affect diffusion of hydrogen from the exposed surface of the semiconductor material formed by etching the trench. For example, p-type GaN is known to be converted to n-type GaN during dry etching. If the thickness of the surface of the p-type converted to the n-type is too large, diffusion of hydrogen may be blocked so that hydrogen accumulates and escapes from the type-converted surface. Thus, in some embodiments, after dry etching forming trenches 106, the surface of the trenches removes the n-type converted layer or the thickness of the n-type converted layer to a thickness where hydrogen readily diffuses. It can be cleaned with wet etch to reduce.

In some embodiments, the semiconductor structure can be selectively grown to form trenches during growth, as illustrated in FIGS. 7 and 8. For example, as illustrated in FIG. 7, optional III-nitride film 102 and p-type region 100 are grown over substrate 30. A mask material 120 such as SiO ₂ can be placed on the p-type region 100 and then patterned so that the mask material remains in the areas where the trenches are formed. The mask material is not limited to the location illustrated in FIG. 7. For example, in various embodiments, the mask material is a fully grown III-nitride film 102 on a directly grown substrate, on the surface of a partially grown III-nitride film 102, as illustrated. Is formed on the surface of the, partially grown p-type region 100, or on the surface of the fully grown p-type region 100. As long as the mask material is in direct contact with at least a portion of the p-type region 100, the mask material is in any layer of the device, on any surface (including directly on the growth substrate 30), any thickness It can be formed with, and can be extended through multiple layers.

III-nitride film 104 is grown over mask material 120. The growth, as illustrated in FIG. 8, eventually covers the mask material through lateral overgrowth, so that the areas 122 between neighboring mask regions are filled with a III-nitride material. When the die is singulated after growth, wet etch or other suitable technique can be used to remove the mask material, creating an embedded trench 124 through which hydrogen can escape during activation annealing. During the activation annealing, hydrogen escapes from the embedded trenches through the sides of the wafer, and the embedded trenches are exposed to the surroundings.

Returning to FIG. 3, at block 124, a III-nitride structure with trenches activates the embedded p-type region, for example, by blocking hydrogen that has complexed with the p-type dopant in the p-type region. In order to do, it is annealed.

4, 5, and 6 illustrate devices comprising a buried p-type region that can be activated by forming trenches and by annealing, as illustrated in FIGS. 1, 2, and 3. . 4 illustrates a device in which the p-type region is grown before the n-type region. 5 and 6 illustrate devices comprising tunnel junctions. The trenches are omitted from FIGS. 4, 5, and 6 for clarity. In particular, the devices illustrated in FIGS. 4, 5, and 6 can be, for example, approximately 1 mm on the side, which means that tens or even hundreds of trenches can be formed in a single device. In any of the devices illustrated in FIGS. 4, 5, and 6, one or more of the trenches can be used as vias in which metal contacts to the buried layers of the device are placed, as described above.

In some embodiments, the p-type region of the III-nitride device is grown before the light emitting layer and n-type region.

In conventional III-nitride LEDs, the n-type region is first grown on the substrate, followed by light emitting layers and p-type semiconductor. The inner field of the III-nitride LED growing below the n-side increases with increasing forward bias. As a result, as the device bias (current) increases, the internal electric field increases, reducing electron-hole overlap and thereby reducing radiation efficiency. Growing the device in reverse order reverses the inner field, with the p-type region first grown on the substrate. In III-nitride LEDs grown under the p-side, the inner field is opposite to the built-in polarization field. As a result, as the forward bias (current) increases, the radiation efficiency of such devices can increase.

4 illustrates an example of a device in which the p-type region is grown before the emissive layer and the n-type region. Such a semiconductor structure can be included in any suitable device; Embodiments of the invention are not limited to the illustrated vertical device. In embodiments where the original growth substrate is removed, such as, for example, a flip chip device, the structure 102 can be entirely removed to form an electrical contact in the p-type region, or the hole/trench is a metal contact Can be etched through the structure 102 to expose a portion of the p-type region where it can be formed. In embodiments where the substrate remains, for example a lateral die device, one contact can be placed on the top surface of the semiconductor structure, and the other contact is exposed by etching to expose the p-type region It can be placed on a surface.

The device illustrated in FIG. 4 includes a semiconductor structure 10 grown on a growth substrate (not shown). After the p-type region 12 is first grown, the active or emitting region comprising at least one light emitting layer 14 continues, and then the n-type region 16 continues.

The P-type region 12 corresponds to the embedded p-type region 100 of FIG. 1; The active region 14 and n-type region 16 correspond to the III-nitride film 104 of FIG. 1; The III-nitride film 102 of FIG. 1 can be a nucleation or buffer structure (not shown) or can be omitted.

The metal p-contact 18 is disposed on the p-type region 12; The metal n-contact 20 is disposed on the n-type region 16.

The semiconductor structure 10 includes a light emitting or active region sandwiched between an n-type region and a p-type region. The n-type region 16 is composed of different compositions comprising n- or even p-type device layers designed for specific optical, material, or electrical properties desirable for a light emitting region, for example, to efficiently emit light. And multiple layers of dopant concentration. The light emitting layer 14 may be included in the light emitting or active region. Examples of suitable light emitting regions include a single thick or thin light emitting layer, or multiple quantum well light emitting regions comprising multiple thin or thick light emitting layers separated by barrier layers. The p-type region 12 is prepared layers such as buffer layers or nucleation layers, and/or p-type, n-type, or layers designed to facilitate removal of the growth substrate, which may not be intentionally doped, And multiple layers of different composition, thickness, and dopant concentration, including layers that are not intentionally doped, or n-type layers.

After growth, the semiconductor structure can be processed with any suitable device.

In some embodiments, the III-nitride device includes a tunnel junction. Tunnel junction (TJ) is a structure that allows electrons to be tunneled from the valence band of the p-type layer to the conduction band of the n-type layer in reverse bias. When the electron is tunneled, holes remain behind the p-type layer, so carriers are generated in both layers. Thus, in an electronic device such as a diode, when only a small leakage current flows in the reverse bias, a large current can be carried across the tunnel junction in the reverse bias. Tunnel junction is typically achieved in other material systems using very high doping (e.g. p++/n++ junction in (Al)GaAs material system), specific alignment of conduction and valence bands in p/n tunnel junction need. III-nitride materials have intrinsic polarization that creates an electric field in heterointerfaces between different alloy compositions. This polarization field can be used to achieve the required band alignment for tunneling.

5 and 6 illustrate two devices including tunnel junctions.

In the device of Figure 5, the tunnel junction is placed between the p-type region and the metal contact that injects current into the p-type region. The contact can be formed on the n-type layer, which can have much better sheet resistance and thus better current spread compared to p-type layers. In the device illustrated in FIG. 5, the n-type layers convert holes from the p-type region to electrons in the n-type contact layer through a tunnel junction, thereby making the contact layer for both positive and negative terminals of the LED. It is used as a field.

The device of FIG. 5 includes an n-type region 32 grown on a growth substrate, then a light emitting layer 34 that can be disposed in the light emitting region, and a p-type region 36. The n-type region 32, the light emitting layer 34, and the p-type region 36 are detailed in the text accompanying FIG. Tunnel junction 38 is formed over the p-type region 36.

In some embodiments, the tunnel junction 38 is also referred to as a p++ layer, a highly doped p-type layer in direct contact with the p-type region 36, and also referred to as an n++ layer, directly with the p++ layer And a highly doped n-type layer in contact. (In some embodiments, the p++ layer of the tunnel junction 38 can serve as a p-type region within the device, so no individual p-type region is required.) In some embodiments, the tunnel junction 38 ) Includes a p++ layer sandwiched between the p++ layer and the n++ layer and a layer of a composition different from the n++ layer. In some embodiments, tunnel junction 38 includes an InGaN layer sandwiched between a p++ layer and an n++ layer. In some embodiments, tunnel junction 38 includes an AlN layer sandwiched between a p++ layer and an n++ layer. The tunnel junction 38 is in direct contact with the n-type layer 40 described below.

The p++ layer can be, for example, InGaN or GaN doped with an acceptor such as Mg or Zn to a concentration of about 10 ¹⁸ cm ^-3 to about 5 x 10 ²⁰ cm ^-3 . In some embodiments, the p++ layer is doped to a concentration of about 2×10 ²⁰ cm ^-3 to about 4×10 ²⁰ cm ^-3 . The n++ layer can be, for example, InGaN or GaN doped with an acceptor such as Si or Ge to a concentration of about 10 ¹⁸ cm ^-3 to about 5 x 10 ²⁰ cm ^-3 . In some embodiments, the n++ layer is doped to a concentration of about 7×10 ¹⁹ cm ^-3 to about 9×10 ¹⁹ cm ^-3 . The tunnel junction 38 is usually very thin, for example, the tunnel junction 38 can have a total thickness ranging from about 2 nm to about 100 nm, and each of the p++ layer and n++ layer has a range of about 1 nm. It can have a thickness ranging from about 50 nm. In some embodiments, each of the p++ layer and the n++ layer can have a thickness ranging from about 25 nm to about 35 nm. The p++ layer and the n++ layer may not necessarily have the same thickness. In one embodiment, the p++ layer is 15 nm Mg-doped InGaN and the n++ layer is 30 nm Si-doped GaN. The p++ layer and the n++ layer can have an inclined dopant concentration. For example, a portion of the p++ layer adjacent to the base p-type region 36 may have a dopant concentration that slopes from the dopant concentration of the base p-type region to the desired dopant concentration in the p++ layer. Similarly, the n++ layer can have a dopant concentration that slopes from the maximum adjacent to the p++ layer to the minimum adjacent to the n-type layer 40 formed over the tunnel junction 38. The tunnel junction 38 is made thin enough and doped sufficiently so that the tunnel junction 38 displays a low series of voltage drops when the conduction current is in the reverse bias mode. In some embodiments, the voltage drop across the tunnel junction 38 is from about 0.1V to about 1V.

Embodiments comprising an InGaN or AlN or other suitable layer between the p++ layer and the n++ layer can enhance the polarization field in III-nitrides to help align the bands for tunneling. This polarization effect can reduce the doping requirements in n++ and p++ layers and reduce the required tunneling distance (potentially allowing higher current flow). The composition of the layer between the p++ layer and the n++ layer can be different from the composition of the p++ layer and the n++ layer, and/or selected to cause realignment due to polarization charges present between other materials in the III-nitride material system. Can be.

Examples of suitable tunnel junctions are described in US8039352 B2, which patent is incorporated herein by reference.

An n-type contact layer 40 is formed over the tunnel junction 38, in direct contact with the n++ layer.

In the device of FIG. 5, the p-type region 36 and the p++ layer of the tunnel junction 38 correspond to the p-type region 100 of FIG. 1; The n++ layer and n-type contact layer 40 of the tunnel junction 38 correspond to the III-nitride film 104 of FIG. 1; The n-type region 32 and the active region 34 correspond to the III-nitride film 102 of FIG. 1.

The first and second metal contacts 44 and 42 are formed on the n-type contact layer 40 and the n-type region 32, respectively. The mesa can be etched to form a flip chip device, as illustrated in FIG. 5, or any other suitable device structure can be used. The first and second metal contacts 44 and 42 may be of the same material, such as aluminum, but this is not required; Any suitable contact metal or metals can be used.

In the device of FIG. 6, multiple LEDs are grown overlaid and connected in series through a tunnel junction. In the device of FIG. 6, multiple LEDs are generated within the footprint of a single LED, which can dramatically increase the optical flux generated per unit area. In addition, by driving the LEDs connected by the tunnel junction with a lower drive current, each LED can operate at its peak efficiency. In a single LED, this will cause a drop in light output, but by having two or more LEDs connected in series at a given chip area, the light output can be maintained with dramatically improved efficiency. Accordingly, the tunnel junction device illustrated in FIG. 6 can be used in applications requiring high efficiency and/or applications requiring high flux per unit area.

The device of FIG. 6 includes an n-type region 32 grown on a growth substrate, and then a light emitting layer 34 that can be disposed in a light emitting region, and a p-type region 36 (as described above) Likewise, the p++ layer of the tunnel junction can function as a p-type region 36, so individual p-type regions are not required). The n-type region 32, the light emitting layer 34, and the p-type region 36 are detailed in the text accompanying FIG. Tunnel junction 38 is formed over p-type region 36, as described above. A second device structure comprising a second n-type region 46, a second emissive layer 48, and a second p-type region 50 is formed over the tunnel junction 38. The tunnel junction 38 is oriented such that the p++ layer directly contacts the p-type region 36 of the first LED, and the n++ layer directly contacts the n-type region 46 of the second LED.

In the device of FIG. 6, the p-type region 36 and the p++ layer of the tunnel junction 38 correspond to the p-type region 100 of FIG. 1; The n++ layer, the n-type layer 46, the active region 48, and the p-type region 50 of the tunnel junction 38 correspond to the III-nitride film 104 of FIG. 1 (the trenches are p- Upon direct contact with the mold region 50, the trenches will also activate the p-type region 50 through the p-type region 50, and if it is the last grown layer, it will also be activated by conventional annealing. Can); The n-type region 32 and the active region 34 correspond to the III-nitride film 102 of FIG. 1.

The first and second metal contacts 54 and 52 are formed on the n-type region 32 of the first LED and the p-type region 50 of the second LED, respectively. The mesa can be etched to form a flip chip device, as illustrated in FIG. 6, or any other suitable device structure can be used. In some embodiments, the additional tunnel junction and n-type layer are p-type of the second LED to form a second metal contact 52 on the n-type layer, as illustrated in the device of FIG. 5. It may be formed over the region 50.

Although two active regions are illustrated in FIG. 6, any number of active regions can be illustrated if the p-type region adjacent to each active region is separated from the n-type region adjacent to the next active region by tunnel junction. It can be included between metal contacts. Since the device of FIG. 6 has only two contacts, both emitting layers simultaneously emit light and cannot be activated individually and separately. In other embodiments, individual LEDs in the stack can be activated separately by forming additional contacts. In some embodiments, the device can have sufficient junctions to allow the device to operate at typical line voltages, such as 110 volts, 220 volts, and the like.

The two emitting layers can be made of the same composition, so they emit the same color light, or they can be made of different compositions, so they emit light of different colors (ie different peak wavelengths). For example, three active area devices with two contacts can be fabricated such that the first active area emits red light, the second active area emits blue light, and the third active area emits green light. have. When activated, the device can generate white light. Since active areas are stacked to appear to emit light from the same area, such devices avoid problems with color mixing present in devices that combine red, blue, and green light from adjacent active areas rather than stacked. can do. In devices with active regions that emit light of different wavelengths, the active region that generates the shortest wavelength of light can be located closest to the surface from which the light is extracted from the LED, typically a sapphire, SiC, or GaN growth substrate. The placement of the shortest wavelength active region close to the output surface is more sensitive by minimizing losses due to absorption in the quantum wells of other active regions and by placing longer wavelength active regions closer to the heat sink formed by the contacts. It is possible to reduce thermal shock on long wavelength quantum wells. The quantum well layers can also be made thin enough to have low absorption of light in the quantum well layers. The color of the mixed light emitted from the device can be controlled by selecting the number of active areas emitting light of each color. For example, the human eye is very sensitive to green photons and not sensitive to red and blue photons. To generate a balanced white light, a stacked active area device can have a single green active area and multiple blue and red active areas.

The devices of FIGS. 4, 5, and 6 are formed by growing a III-nitride semiconductor structure on growth substrate 30 as is known in the art. The growth substrate is often sapphire, but can be any suitable substrate, such as, for example, SiC, Si, GaN, or composite substrates (eg, like GaN on a sapphire template). The surface of the growth substrate on which the III-nitride semiconductor structure is grown can be patterned, roughened, or textured before growth, which can improve light extraction from the device. The surface of the growth substrate opposite the growth surface (ie, the surface where multiple lights are extracted in a flip chip configuration) can be patterned, roughened or textured before or after growth, which can improve light extraction from the device. have.

Metal contacts often include multiple conductive layers, such as a reflective metal and a guard metal that can prevent or reduce electron migration of the reflective metal. The reflective metal is often silver, but any suitable material or materials can be used. The metal contacts are electrically insulated from each other by a gap that can be filled with a dielectric material such as silicon or an oxide of any other suitable material. Multiple vias may be formed exposing portions of the n-type region 32; Metal contacts are not limited to the arrangements illustrated in FIGS. 4, 5, and 6. Metal contacts can be redistributed to form bond pads with a dielectric/metal stack, as is in the art.

To form the electrical connections to the LED, one or more interconnects are formed on the two illustrated metal contacts or are electrically connected to these metal contacts. The interconnects can be, for example, solder, stud bumps, gold layers, or any other suitable structure.

The substrate 30 can be thinned or removed entirely. In some embodiments, the surface of the substrate 30 exposed by thinning is patterned, textured, or roughened to improve light extraction.

Any of the devices described herein can be combined with a wavelength conversion structure. The wavelength converting structure can include one or more wavelength converting materials. The wavelength converting structure may be directly connected to the LED, or disposed in close proximity to the LED, but not directly connected to the LED, or may be spaced from the LED. The wavelength conversion structure can be any suitable structure. The wavelength converting structure may be formed individually from the LED, or may be formed in situ with the LED

Examples of wavelength converting structures formed individually from the LEDs are ceramic wavelength converting structures that can be formed by sintering or any other suitable process, rolled, cast, or otherwise formed into sheets, and then individual wavelength converting. Wavelength converting materials such as powder phosphors disposed on a transparent material such as silicon or glass singulated into structures, and transparent material such as silicon formed of a flexible sheet, which can be deposited over the LED or otherwise disposed. And wavelength converting materials such as powder phosphors placed therein.

Examples of wavelength conversion structures formed in situ include wavelength conversion materials such as powder phosphors that are mixed and distributed with a transparent material such as silicon, screen printed, stenciled, molded, or otherwise disposed on the LED; And wavelength conversion materials coated on the LED by electrophoresis, vapor phase, or any other suitable type of deposition.

Multiple types of wavelength conversion structures can be used in a single device. As just one example, a ceramic wavelength conversion member may be combined with a molded wavelength conversion member, with the same or different wavelength conversion materials being in the ceramic and molded members.

The wavelength converting structure is, for example, conventional phosphors, organic phosphors, quantum dots, organic semiconductors, II-VI or III-V semiconductors, II-VI or III-V semiconductor quantum dots or nano crystals, dyes Fields, polymers, or other materials that emit light.

The wavelength converting material absorbs the light emitted by the LED and emits light of one or more different wavelengths. The unconverted light emitted by the LED is often part of the final spectrum extracted from the structure, but it is not necessary. Examples of common combinations include a blue emitting LED in combination with a yellow emitting wavelength converting material, a blue emitting LED in combination with a green and red emitting wavelength converting material, a UV emitting LED in combination with a blue and yellow emitting wavelength converting material, and a blue, green And a UV emitting LED combined with red emitting wavelength converting materials. Wavelength converting materials that emit different colors of light can be added to adjust the spectrum of light extracted from the structure.

The embodiments described herein can be included with any suitable light emitting device. Embodiments of the invention are not limited to the specific structures illustrated.

Some features of some embodiments may be omitted or implemented in other embodiments. The device elements and method elements described herein are interchangeable and may be used or omitted from any of the examples or embodiments described herein.

In the examples and embodiments described above, the semiconductor light emitting device is a III-nitride LED that emits blue or UV light, but semiconductor light emitting devices other than LEDs, such as laser diodes, are within the scope of the invention. In addition, the principles described herein can be used for semiconductor luminescence or fabrication from other material systems such as other III-V materials, III-phosphide, III-arsenide, II-VI materials, ZnO, or Si-based materials. It may be applicable to other devices.

Having described the invention in detail, those skilled in the art will appreciate that upon considering this disclosure, modifications may be made to the invention without departing from the spirit of the creative concepts described herein. Accordingly, it is not intended that the scope of the invention be limited to the specific embodiments illustrated and described.

Claims (15)

As a method for selectively growing a semiconductor structure,
Forming a plurality of sections of mask material on the surface;
Patterning the semiconductor structure around a plurality of sections of the mask material to form at least one trench, the mask material remaining in the at least one trench; And
Annealing the semiconductor structure
How to include. The method of claim 1, wherein the semiconductor structure comprises at least one p-type region and at least one n-type region. 3. The method of claim 2, wherein the semiconductor structure further comprises at least one III-nitride light emitting layer. The method of claim 1, wherein the mask material comprises an insulating material. According to claim 1,
And prior to annealing the semiconductor structure, removing a plurality of sections of the mask material to expose the surface of the at least one trench. The method of claim 5,
And after annealing the semiconductor structure, filling the at least one trench with an insulating material. According to claim 1,
Further comprising disposing a metal in the at least one trench, the metal directly contacting a first portion of the semiconductor structure in the trench, and the mask material is a second portion of the semiconductor structure in the at least one trench. How to be placed between the part and the metal. The method of claim 1, wherein a plurality of trenches are present, and a closest neighboring trench is present for each of the plurality of trenches. 9. The method of claim 8, wherein each of the plurality of trenches is surrounded by a portion of the semiconductor structure uninterrupted by each of the plurality of trenches. The method of claim 8, wherein the nearest neighboring trenches are spaced less than twice the maximum length of diffusion of hydrogen during annealing the semiconductor structure. The method of claim 1, wherein the semiconductor structure comprises a tunnel junction. 3. The method of claim 2, wherein the at least one trench comprises at least one embedded trench, and the at least one embedded trench exposes at least a portion of the p-type region to the surrounding environment. 13. The method of claim 12, wherein the at least one trench is a lateral embedded trench. 13. The method of claim 12, wherein the at least one trench is surrounded by at least one portion of the p-type region or n-type region that is not interrupted by the at least one embedded trench. 13. The method of claim 12, further comprising growing tunnel junctions on the p-type region.

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