相關申請案之交叉參考
本申請案主張2016年5月20日申請之美國臨時專利申請案第62/339,448號及2016年7月15日申請之歐洲專利申請案第16179661.0號之優先權。美國臨時專利申請案第62/339,448號及歐洲專利申請案第16179661.0號被併入本文中。 在一無氫氛圍中需要一退火以活化一III族氮化物器件中之p型層限制器件設計。已實驗性地展示氫無法透過n型III族氮化物材料擴散，且氫不易於透過半導體材料在對應於一典型器件晶圓之直徑的一半之距離上橫向擴散。因此，為使活化退火有效，p型層不能被任何其他層覆蓋。無需一有效退火，器件保持不具有一p型層，或具有含一極低摻雜濃度之一p型層，從而顯現其無用。相應地，具有一埋入式p型層之一器件(諸如具有一隧道接面之一器件或其中p型層生長於n型層之前之一器件)無法由包含藉由MOCVD之生長接著退火之一習知程序形成。 在本發明之實施例中，一器件結構經生長具有一埋入式p型層。曝露埋入式p型層之部分之溝渠形成於器件結構中。接著，退火結構使得氫可橫向擴散出埋入式p型層至溝渠，其中氫可逸出至周圍環境。 圖1繪示一半導體器件結構之一部分。圖1之結構生長於一生長基板30上，其可為(例如)藍寶石、SiC、Si、一非III族氮化物材料、GaN、一複合基板或任何其他適合基板。一選用III族氮化物薄膜102可生長於p型區域100之前，儘管不需要III族氮化物薄膜102。III族氮化物薄膜102可包含(例如)核晶生長層或緩衝層、可為GaN或任何其他III族氮化物材料之平滑層、n型層、發光層或主動層、無摻雜層、一器件之主動區域及/或任何其他適合層或材料。 p型區域100包含摻雜有一p型摻雜物(諸如(例如) Mg或任何其他適合材料)之至少一二元、三元、四元或五元III族氮化物層。 一III族氮化物薄膜104生長於p型層100之後使得p型層100由III族氮化物薄膜104掩埋。III族氮化物薄膜104可包含n型層、p型層、器件之主動區域、發光層、無摻雜層及/或任何其他適合層或材料。 在生長之後或生長期間，溝渠106形成於半導體結構中。溝渠106可延伸穿過III族氮化物薄膜104之整個厚度使得溝渠106之底部係位於p型區域100中，如圖1中所繪示。替代地，溝渠106可延伸穿過III族氮化物薄膜104及p型區域100兩者之整個厚度使得溝渠106之底部係位於III族氮化物薄膜102中、係生長基板30之表面或延伸至生長基板30。 溝渠106之寬度108可為(例如)(在一些實施例中)至少0.05 μm、(在一些實施例中)不大於50 μm、(在一些實施例中)至少0.5 μm及(在一些實施例中)不大於15 μm。在一些實施例中，溝渠保持盡可能小以避免損失發光區域。 溝渠106經間隔使得在稍後退火期間所有p型區域100自一溝渠間隔不大於氫之最大擴散長度之一距離。在退火期間，溝渠106之間的最大間距110可為氫之平均或最大擴散長度之兩倍。間距110可由退火之條件判定，其可判定退火期間氫之最大橫向擴散長度-不同退火可具有不同最大橫向擴散長度。最近相鄰溝渠之間的最大間距110可為(在一些實施例中)至少1 μm、(在一些實施例中)不大於500 μm、(在一些實施例中)至少5 μm及(在一些實施例中)不大於250 μm。 圖1中所繪示之半導體結構可在形成溝渠106之後退火。在退火期間，氫被驅除出p型區域100至溝渠106中，其中氫可自半導體結構逸出至周圍環境中。 在一些實施例中，於退火之後，溝渠106可被填充有一絕緣材料114。絕緣材料114允許一金屬接點在不會無意地引起一短路之情況下之形成於具有溝渠之一表面上。絕緣材料114可在退火之後之處理的任何階段處形成-例如，在其中移除生長基板之實施例中，溝渠106可在移除生長基板之前或之後被填充有絕緣材料114，或在其中執行此蝕刻之實施例中，溝渠106可在蝕刻以曝露一埋入層之前或之後被填充有絕緣材料114。 在一些實施例中，溝渠106用作為其中形成金屬接點之通孔以接觸一p側下器件中之p型區域，如圖9中所繪示。在其中金屬接點134係形成於與p型區域100接觸之溝渠106中的實施例中，一序列金屬及絕緣體經沈積及圖案化，使得金屬接點僅與埋入式p型區域100或其他所要層(在如圖9中所繪示之溝渠132之底部中)而不是上之層(III族氮化物薄膜104)直接接觸。例如，一絕緣材料130可被安置於接觸金屬134與不與金屬接點直接接觸之半導體層之間之溝渠的側壁上。 在一些實施例中，溝渠106係曝露於空氣或周圍環境氣體，或塗有而非填充一薄鈍化層(例如SiO2
)。相應地，在一些實施例中，溝渠106可部分或完全填充有一絕緣或鈍化材料。 圖2係圖1之結構之一頂面112之一部分之一平面圖。如圖2中所繪示，在一些實施例中，溝渠106可係彼此隔離，且係由被一溝渠連續之半導體結構的一部分包圍。相應地，在一些實施例中，半導體材料全部經電連接，且無半導體材料之電隔離島係由溝渠106形成。在一些實施例中，一些或所有溝渠可彼此連接以形成半導體材料之隔離島-例如，在一些實施例中，溝渠106可界定稍後自半導體材料之一晶圓分離之一單一器件的邊界。經形成於器件之一晶圓上之一單一器件可具有彼此連接之一些溝渠以界定器件或器件內之半導體材料之一隔離島的邊界，及經彼此隔離且經形成於半導體材料之隔離島內的一或多個其他溝渠。 圖3繪示形成一器件之一方法。在區塊120中，具有一埋入式p型區域之一III族氮化物結構生長於一生長基板上。 在區塊122中，溝渠106係形成於生長之III族氮化物結構中。溝渠106經繪示於圖1及圖2中。溝渠106可係由任何適合技術形成，包含(例如)乾式蝕刻、濕式蝕刻或乾式蝕刻及濕式蝕刻之一組合。在一些實施例中，形成溝渠的方法可影響氫擴散出由蝕刻溝渠所形成之半導體材料的曝露表面。例如，p型GaN已知在乾式蝕刻期間被轉換為n型GaN。若轉換為n型之p型之表面的厚度太大，則氫之擴散可被阻擋，使得氫累積於型轉換表面處且無法逸出。相應地，在一些實施例中，於乾式蝕刻以形成溝渠106之後，可使用一濕式蝕刻清潔來溝渠之表面以移除n型轉換層，或將n型轉換層之厚度減小為氫易於透過其擴散之一厚度。 在一些實施例中，半導體結構可係選擇性地生長以在生長期間形成溝渠，如圖7及圖8中所繪示。例如，如圖7中所繪示，一選用III族氮化物薄膜102及一p型區域100係生長於一基板30上。一遮罩材料120 (諸如SiO2
)可被安置於p型區域100上，接著經圖案化，使得遮罩材料保留在其中形成溝渠之區域中。遮罩材料不受限於圖7中所繪示之位置。例如，在各種實施例中，遮罩材料係直接形成於生長基板上、部分生長之III族氮化物薄膜102之一表面上、一完全生長之III族氮化物薄膜102之表面上、部分生長之p型區域100之一表面上，或完全生長之p型區域100之表面上，如所繪示。遮罩材料可係形成於器件之任何層中、任何表面上(包含直接形成於生長基板30上)，其具有任何厚度，且可延伸穿過多個層，只要遮罩材料與p型區域100之至少一部分係直接接觸。 III族氮化物薄膜104生長於遮罩材料120上。生長將最終經由橫向過度生長來覆蓋遮罩材料，使得相鄰遮罩區域之間的區域122被填充有III族氮化物材料，如圖8中所繪示。當晶粒在生長之後被切割時，一濕式蝕刻或其他適合技術可被用以移除遮罩材料，從而產生氫在活化退火期間可透過其逸出之一嵌入式溝渠124。在活化退火期間，氫透過晶圓之側自嵌入式溝渠逸出，其中嵌入式溝渠係曝露於周圍環境。 返回圖3，在區塊124中，退火具有溝渠之III族氮化物結構藉由(例如)驅除與p型區域中之p型摻雜物已形成一複合物的氫來活化埋入式p型區域。 圖4、圖5及圖6繪示包含可藉由形成溝渠及退火來活化之一埋入式p型區域的器件，如圖1、圖2及圖3中所繪示。圖4繪示其中p型區域生長於n型區域之前之一器件。圖5及圖6繪示包含隧道接面之器件。為了清晰，溝渠係自圖4、圖5及圖6省略。特定言之，圖4、圖5及圖6中所繪示之器件在一側上可(例如)係約1 mm，意謂數十或甚至數百溝渠可被形成於一單一器件中。在圖4、圖5及圖6中所繪示之器件之任何者中，溝渠之一或多者可被用作為其中被安置至器件之埋入層之金屬接點的通孔，如上文所描述。 在一些實施例中，一III族氮化物器件之p型區域係生長於發光層及n型區域之前。 在習知III族氮化物LED中，n型區域首先生長於一基板上，接著發光層及p型半導體。生長於n側下之一III族氮化物LED之內場隨正向偏壓增加而增加。因此，當器件偏壓(電流)增加時，內部電場增加，從而減少電子電洞重疊，且藉此降低輻射效率。以反向順序生長器件(其中p型區域首先生長於基板上)來反轉內場。在生長於p側下之一III族氮化物LED中，內場係與內建極化場相反。因此，當正向偏壓(電流)增加時，此一器件之輻射效率可增加。 圖4繪示其中p型區域生長於發光層及n型區域之前之一器件之一實例。此一半導體結構可併入任何適合器件；本發明之實施例不受限於所繪示之垂直器件。在其中原始生長基板被移除之實施例(諸如(例如)一覆晶器件)中，結構102可被完全移除以電接觸p型區域，或一電洞/溝渠可經蝕刻穿過結構102以曝露一金屬接點可形成於其上之p型區域之一部分。在其中基板保留之實施例(諸如(例如)一橫向晶粒器件)中，一接點可安置於半導體結構之頂面上，且另一接點可安置於藉由蝕刻以曝露p型區域而曝露之一表面上。 圖4中所繪示之器件包含生長於一生長基板(圖中未展示)上之一半導體結構10。首先生長p型區域12，接著包含至少一發光層14之一主動或發光區域，接著一n型區域16。 p型區域12對應於圖1之埋入式p型區域100；主動區域14及n型區域16對應於圖1之III族氮化物薄膜104；圖1之III族氮化物薄膜102可為一核晶生長或緩衝結構(圖中未展示)或可省略。 一金屬p接點18安置於p型區域12上；一金屬n接點20安置於n型區域16上。 半導體結構10包含夾置於n型區域與p型區域之間的一發光或主動區域。n型區域16可包含多個不同成分及摻雜物濃度之層，包含(例如)針對用於有效地發射光之發光區域所要之特定光學性質、材料性質或電性質設計之n型或甚至p型器件層。發光層14可包含於發光或主動區域中。適合發光區域之實例包含一單一厚或薄發光層，或包含由阻障層分離之多個薄或厚發光層之一多量子井發光區域。p型區域12可包含多個不同成分、厚度及摻雜物濃度之層，包含製備層，諸如緩衝層或核晶生長層，及/或經設計以促進生長基板之移除之層，其可為p型、n型或非有意摻雜的 ，及非有意摻雜之層或n型層。 在生長之後，半導體結構可處理成任何適合器件。 在一些實施例中，一III族氮化物器件包含一隧道接面。一隧道接面(TJ)係允許電子以反向偏壓自一p型層之價帶穿隧至一n型層之傳導帶之一結構。當一電子穿隧時，一電洞保留在p型層後面，使得載子產生於兩個層中。相應地，在其中僅一小洩漏電流以反向偏壓流動之一電子器件(如一二極體)中，一大電流可以反向偏壓跨越一隧道接面攜載。一隧道接面需要p/n隧道接面處之傳導帶及價帶之一特定對準，其通常在使用非常高摻雜之其他材料系統(例如(Al)GaAs材料系統中之p++/n++接面)中達成。III族氮化物材料具有在不同合金成分之間的異質介面處產生一電場之一固有極化。此極化場可用以達成用於穿隧之所需帶對準。 圖5及圖6繪示包含隧道接面之兩個器件。 在圖5之器件中，一隧道接面安置於p型區域與將電流注入p型區域中之金屬接點之間。接點可形成於一n型層上，其可具有相較於p型層之較佳薄片電阻及因此較佳電流散佈。在圖5中所繪示之器件中，藉由經由一隧道接面將電洞自p型區域轉換為一n型接觸層中之電子而將n型層用作為LED之正端子及負端子兩者之接觸層。 圖5之器件包含生長於一生長基板上之一n型區域32，接著一發光層34 (其可安置於一發光區域中)及一p型區域36。上文在隨附圖4之內文中描述n型區域32、發光層34及p型區域36。一隧道接面38形成於p型區域36上。 在一些實施例中，隧道接面38包含與p型區域36直接接觸之一高度摻雜之p型層(亦指稱一p++層)及與p++層直接接觸之一高度摻雜之n型層(亦指稱一n++層)。(在一些實施例中，隧道接面38之p++層可充當器件中之p型區域，使得不需要一分離之p型區域)。在一些實施例中，隧道接面38包含夾置於p++層與n++層之間的一層不同於p++層及n++層之一成分。在一些實施例中，隧道接面38包含夾置於p++層與n++層之間的一InGaN層。在一些實施例中，隧道接面38包含夾置於p++層與n++層之間的一AlN層。隧道接面38與n型層40直接接觸，如下文所描述。 p++層可為(例如)摻雜有一受體(諸如Mg或Zn)達約1018
cm−3
至約5×1020
cm−3
之一濃度之InGaN或GaN。在一些實施例中，p++層摻雜至約2×1020
cm−3
至約4×1020
cm−3
之一濃度。n++層可為(例如)摻雜有一受體(諸如Si或Ge)達約1018
cm−3
至約5×1020
cm−3
之一濃度之InGaN或GaN。在一些實施例中，n++層摻雜至約7×1019
cm−3
至約9×1019
cm−3
之一濃度。隧道接面38通常非常薄，(例如)隧道接面38可具有在自約2 nm至約100 nm之範圍內之一總厚度，且p++層及n++層之各者可具有在自約1 nm至約50 nm之範圍內之一厚度。在一些實施例中，p++層及n++層之各者可具有在自約25 nm至約35 nm之範圍內之一厚度。p++層及n++層可不必要為相同厚度。在一實施例中，p++層係15 nm之摻雜Mg之InGaN且n++層係30 nm之摻雜Si之GaN。p++層及n++層可具有一分級摻雜物濃度。例如，與下伏p型區域36相鄰之p++層之一部分可具有自下伏p型區域之摻雜物濃度分級至p++層中之所要摻雜物濃度之一摻雜物濃度。類似地，n++層可具有自與p++層相鄰之一最大值分級至與形成於隧道接面38上之n型層40相鄰之一最小值之一摻雜物濃度。隧道接面38製造成足夠薄及足夠摻雜使得隧道接面38在以反向偏壓模式傳導電流時顯示低串聯電壓降。在一些實施例中，跨越隧道接面38之電壓降係約0.1 V至約1 V。 包含一InGaN或AlN或p++層與n++層之間的其他適合層之實施例可對III族氮化物中之極化場起槓桿作用以幫助對準用於穿隧之帶。此極化效應可減少n++層及p++層中之摻雜需求且減少所需穿隧距離(可能允許較高電流)。p++層與n++層之間的層之成分可不同於p++層及n++層之成分，及/或可經選定以引起歸因於存在於III族氮化物材料系統中之不同材料之間的極化電荷之帶重新對準。 US8039352 B2中描述適合隧道接面之實例，其以引用的方式併入本文中。 一n型接觸層40形成於隧道接面38上，與n++層直接接觸。 在圖5之器件中，p型區域36及隧道接面38之p++層對應於圖1之p型區域100；隧道接面38之n++層及n型接觸層40對應於圖1之III族氮化物薄膜104；n型區域32及主動區域34對應於圖1之III族氮化物薄膜102。 第一金屬接點及第二金屬接點44及42分別形成於n型接觸層40及n型區域32上。一台面可經蝕刻以形成一覆晶器件(如圖5中所繪示)或可使用任何其他適合器件結構。第一金屬接點及第二金屬接點44及42可為相同材料(諸如鋁)，儘管此並不需要；可使用任何適合(若干)接觸金屬。 在圖6之器件中，多個LED生長於彼此之頂上且經由一隧道接面串聯連接。在圖6之器件中，多個LED產生於一單一LED之佔覆蓋區內，其可大幅增加每單位面積所產生之光通量。另外，藉由在一較低驅動電流下驅動由一隧道接面連接之LED，各LED可依其峰值效率操作。在一單一LED中，此將導致光輸出之一下降，然而藉由在一給定晶片區域中具有串聯連接之兩個或兩個以上LED，可維持光輸出且大幅改良效率。因此，圖6中所繪示之隧道接面器件可用於需要高效率之應用及/或需要每單位面積之高通量之應用中。 圖6之器件包含生長於一生長基板上之一n型區域32，接著一發光層34 (其可被安置於一發光區域中)及一p型區域36 (如上文所描述，隧道接面之p++層可作為p型區域36，使得不需要一分離之p型區域)。上文在隨附圖4之內文中描述n型區域32、發光層34及p型區域36。如上文所描述，一隧道接面38係形成於p型區域36上。一第二器件結構(包含一第二n型區域46、一第二發光層48及一第二p型區域50)係形成於隧道接面38上。隧道接面38經定向使得p++層係與第一LED之p型區域36直接接觸，且n++層係與第二LED之n型區域46直接接觸。 在圖6之器件中，p型區域36及隧道接面38之p++層對應於圖1之p型區域100；隧道接面38之n++層、n型層46、主動區域48及p型區域50對應於圖1之III族氮化物薄膜104 (若溝渠與p型區域50直接接觸，則溝渠亦將活化p型區域50，儘管p型區域50 (若其係最後生長之層)亦可藉由一習知退火來活化)；n型區域32及主動區域34對應於圖1之III族氮化物薄膜102。 第一金屬接點及第二金屬接點54及52分別係形成於第一LED之n型區域32及第二LED之p型區域50上。可蝕刻一台面以形成一覆晶器件(如圖6中所繪示)，或可使用任何其他適合器件結構。在一些實施例中，一額外隧道接面及n型層可係形成於第二LED之p型區域50上，以使第二金屬接點52形成於一n型層上，如圖5之器件中所繪示。 儘管圖6中繪示兩個主動區域，但若與各主動區域相鄰之p型區域係由一隧道接面自與下一主動區域相鄰之n型區域分離，則任何數目個主動區域可被包含於所繪示之兩個金屬接點之間。由於圖6之器件僅具有兩個接點，所以兩個發光層同時發射光且無法個別及單獨被啟動。在其他實施例中，堆疊中之個別LED可藉由形成額外接點而單獨被啟動。在一些實施例中，一器件可具有足夠接面，使得該器件可依一典型線路電壓(諸如(例如) 110伏特、220伏特等等)操作。 兩個發光層可經製造具有相同成分，使得其等發射相同色彩之光，或具有不同成分，使得其等發射不同色彩(即不同峰值波長)之光。例如，具有兩個接點之一三個主動區域器件可經製造使得第一主動區域發射紅光，第二主動區域發射藍光，且第三主動區域發射綠光。當被活化時，器件可產生白光。由於主動區域經堆疊使得其等似乎自相同區域發射光，所以此等器件可避免其中色彩混合呈現於組合來自相鄰而非堆疊主動區域之紅光、藍光及綠光之一器件中的問題。在具有發射不同波長之光之主動區域之一器件中，產生最短波長之光之主動區域可被定位為最靠近光自其提取之表面，一般而言係一LED中之藍寶石、SiC或GaN生長基板。將最短波長主動區域放置於靠近輸出表面可最小化歸因於其他主動區域之量子井中之吸收的損耗，且可藉由將較長波長主動區域定位為較靠近由接點所形成之散熱器來減少對較敏感較長波長量子井的熱衝擊。量子井層亦可變得足夠薄，使得量子井層中之光的吸收是低的。自器件發射之混合光的色彩可藉由選擇發射各色彩之光之主動區域的數目來控制。例如，人眼對綠色光子非常敏感，且對紅色光子及藍色光子不那麼敏感。為產生平衡白光，一堆疊主動區域器件可具有一單一綠色主動區域及多個藍色及紅色主動區域。 圖4、圖5及圖6之器件係藉由使一III族氮化物半導體結構生長於一生長基板30上而形成，如本技術中所已知。生長基板通常係藍寶石，但可為任何適合基板(諸如(例如) SiC、Si、GaN)或一複合基板(諸如(例如)一藍寶石模板上之GaN)。III族氮化物半導體結構經生長於其上之生長基板之一表面可在生長之前經圖案化、變粗糙或紋理化，其可改良自器件提取光。與生長表面(即在一覆晶組態中大多數光透過其提取之表面)相對之生長基板之一表面可在生長之前或之後經圖案化、變粗糙或紋理化，其可改良自器件提取光。 金屬接點經常包含多個導電層(諸如一反射金屬及一保護金屬(其可防止或減少反射金屬之電遷移))。反射金屬經常係銀，但可使用(若干)任何適合材料。金屬接點經彼此電隔離達可填充有一介電質(諸如矽之氧化物或任何其他適合材料)之一間隙。可形成用於曝露n型區域32之部分的多個通孔；金屬接點不受限於圖4、圖5及圖6中所繪示之配置。金屬接點可經重新分佈以形成具有一介電質/金屬堆疊之焊墊，如本技術中所已知。 為形成至LED之電連接，一或多個互連件係形成於所繪示之兩根金屬接點上或經電連接至所繪示之兩個金屬接點。互連件可為(例如)焊料、凸塊、金層或任何其他適合結構。 基板30可經薄化或完全移除。在一些實施例中，藉由薄化而曝露之基板30的表面經圖案化、紋理化或變粗糙，以改良光提取。 本文所描述之器件之任何者可與一波長轉換結構組合。波長轉換結構可含有一或多個波長轉換材料。波長轉換結構可係直接連接至LED、被安置為靠近LED但不直接連接至LED或與LED隔開。波長轉換結構可為任何適合結構。波長轉換結構可自LED分離形成，或就地與LED一起形成。 自LED分離形成之波長轉換結構之實例包含可藉由燒結或任何其他適合程序形成之陶瓷波長轉換結構；波長轉換材料，諸如粉末磷光體，其安置於透明材料中，諸如聚矽氧或玻璃，其經輥壓、澆鑄或以其他方式形成為一薄片，接著切割成個別波長轉換結構；及波長轉換材料，諸如安置於一透明材料上，諸如聚矽氧，其形成為一撓性薄片，其可層壓或以其他方式安置於一LED上。 就地形成之波長轉換結構之實例包含波長轉換材料，諸如粉末磷光體，其與一透明材料混合，諸如聚矽氧，且施配、網版印刷、蠟印、模製或以其他方式安置於LED上；及波長轉換材料，其藉由電泳、蒸汽或任何其他適合類型之沈積塗佈於LED上。 多個形式之波長轉換結構可用於一單一器件中。僅作為一實例，一陶瓷波長轉換構件可與一模製波長轉換構件組合，其中相同或不同波長轉換材料位於陶瓷及模製構件中。 波長轉換結構可包含(例如)習知磷光體、有機磷光體、量子點、有機半導體、II-VI族或III-V族半導體、II-VI族或III-V族半導體量子點或奈米晶體、染料、聚合物或發光之其他材料。 波長轉換材料吸收由LED發射之光且發射一或多個不同波長之光。由LED發射之未轉換之光通常係自結構提取之光之最終光譜之部分，儘管其不需要如此。一般組合之實例包含與一發射黃光之波長轉換材料組合之一發射藍光之LED、與一發射綠光及紅光之波長轉換材料組合之一發射藍光之LED、與發射藍光及黃光之波長轉換材料組合之一發射UV之LED及與發射藍光、綠光及紅光之波長轉換材料組合之一發射UV之LED。發射其他色彩之光之波長轉換材料可添加以調整自結構提取之光之光譜。 本文所描述之實施例可併入任何適合發光器件。本發明之實施例不受限於所繪示之特定結構。 一些實施例之一些特徵可省略或與其他實施例一起實施。本文所描述之器件元素及方法元素可互換且用於本文所描述之實例或實施例之任何者中或自本文所描述之實例或實施例之任何者省略。 儘管在上文所描述之實例及實施例中半導體發光器件係發射藍光或UV光之一III族氮化物LED，但除LED之外之半導體發光器件(諸如雷射二極體)在本發明之範疇內。另外，本文所描述之原理可應用於半導體發光器件或自其他材料系統(諸如其他III-V族材料、III族磷化物、III族砷化物、II-VI族材料、ZnO或Si基材料)製成之其他器件。 已詳細描述本發明，熟習技術者應瞭解鑑於本發明，可在不會背離本文所描述之發明概念之精神之情況下對本發明進行修改。因此，不意欲本發明之範疇受限於所繪示及描述之特定實施例。 Cross-Reference to Related Applications This application claims the priority of US Provisional Patent Application No. 62 / 339,448 filed on May 20, 2016 and European Patent Application No. 16179661.0 filed on July 15, 2016. US Provisional Patent Application No. 62 / 339,448 and European Patent Application No. 16179661.0 are incorporated herein. An annealing is required in a hydrogen-free atmosphere to activate the p-type layer in a III-nitride device to limit the device design. It has been experimentally shown that hydrogen cannot diffuse through n-type III-nitride materials, and hydrogen cannot easily diffuse through semiconductor materials laterally corresponding to half the diameter of a typical device wafer. Therefore, to make activation annealing effective, the p-type layer cannot be covered by any other layer. Without an effective annealing, the device remains without a p-type layer, or has a p-type layer with a very low doping concentration, thus rendering it useless. Accordingly, a device with a buried p-type layer (such as a device with a tunnel junction or a device in which the p-type layer is grown before the n-type layer) cannot be grown by MOCVD followed by annealing A conventional procedure is formed. In an embodiment of the invention, a device structure is grown with a buried p-type layer. A trench exposing part of the buried p-type layer is formed in the device structure. Next, the annealed structure allows hydrogen to diffuse laterally out of the buried p-type layer into the trench, where hydrogen can escape to the surrounding environment. FIG. 1 illustrates a part of a semiconductor device structure. The structure of FIG. 1 is grown on a growth substrate 30, which may be, for example, sapphire, SiC, Si, a non-III-nitride material, GaN, a composite substrate, or any other suitable substrate. An optional III-nitride film 102 can be grown before the p-type region 100, although the III-nitride film 102 is not required. The III-nitride thin film 102 may include, for example, a nucleation growth layer or a buffer layer, a smooth layer that may be GaN or any other III-nitride material, an n-type layer, a light-emitting layer or an active layer, an undoped layer, a The active area of the device and / or any other suitable layer or material. The p-type region 100 includes at least a binary, ternary, quaternary, or quaternary group III nitride layer doped with a p-type dopant, such as, for example, Mg or any other suitable material. A group III nitride film 104 is grown on the p-type layer 100 so that the p-type layer 100 is buried by the group III nitride film 104. The III-nitride thin film 104 may include an n-type layer, a p-type layer, an active region of the device, a light-emitting layer, an undoped layer, and / or any other suitable layer or material. After or during growth, the trench 106 is formed in the semiconductor structure. The trench 106 may extend through the entire thickness of the III-nitride film 104 so that the bottom of the trench 106 is located in the p-type region 100, as shown in FIG. Alternatively, the trench 106 may extend through the entire thickness of both the III-nitride film 104 and the p-type region 100 such that the bottom of the trench 106 is located in the III-nitride film 102, is the surface of the growth substrate 30, or extends to growth Substrate 30. The width 108 of the trench 106 may be (for example) (in some embodiments) at least 0.05 μm, (in some embodiments) no greater than 50 μm, (in some embodiments) at least 0.5 μm and (in some embodiments) ) Not more than 15 μm. In some embodiments, the trench is kept as small as possible to avoid loss of light emitting area. The trenches 106 are spaced so that all p-type regions 100 are separated from a trench by a distance no greater than the maximum diffusion length of hydrogen during later annealing. During annealing, the maximum spacing 110 between the trenches 106 may be twice the average or maximum diffusion length of hydrogen. The pitch 110 can be determined by the conditions of the annealing, which can determine the maximum lateral diffusion length of hydrogen during annealing-different annealings can have different maximum lateral diffusion lengths. The maximum spacing 110 between the nearest adjacent trenches may be (in some embodiments) at least 1 μm, (in some embodiments) no greater than 500 μm, (in some embodiments) at least 5 μm and (in some implementations) In the example) not more than 250 μm. The semiconductor structure shown in FIG. 1 may be annealed after the trench 106 is formed. During annealing, hydrogen is driven out of the p-type region 100 into the trench 106, where hydrogen can escape from the semiconductor structure into the surrounding environment. In some embodiments, after annealing, the trench 106 may be filled with an insulating material 114. The insulating material 114 allows a metal contact to be formed on a surface having a trench without inadvertently causing a short circuit. The insulating material 114 may be formed at any stage of the process after annealing-for example, in an embodiment in which the growth substrate is removed, the trench 106 may be filled with the insulating material 114 before or after removing the growth substrate, or performed therein In this etched embodiment, the trench 106 may be filled with insulating material 114 before or after etching to expose a buried layer. In some embodiments, the trench 106 is used as a through hole in which a metal contact is formed to contact a p-type region in a p-side lower device, as shown in FIG. 9. In the embodiment where the metal contacts 134 are formed in the trench 106 in contact with the p-type region 100, a sequence of metals and insulators are deposited and patterned so that the metal contacts are only in contact with the buried p-type region 100 or other The desired layer (in the bottom of the trench 132 as shown in FIG. 9) instead of the upper layer (III-nitride film 104) is in direct contact. For example, an insulating material 130 may be disposed on the sidewall of the trench between the contact metal 134 and the semiconductor layer not directly in contact with the metal contact. In some embodiments, the trench 106 is exposed to air or ambient gas, or is coated with a thin passivation layer (eg, SiO 2 ) rather than filled. Accordingly, in some embodiments, the trench 106 may be partially or completely filled with an insulating or passivating material. 2 is a plan view of a portion of a top surface 112 of one of the structures of FIG. As shown in FIG. 2, in some embodiments, the trenches 106 can be isolated from each other and surrounded by a portion of a continuous semiconductor structure. Accordingly, in some embodiments, the semiconductor materials are all electrically connected, and the electrical isolation islands without semiconductor materials are formed by the trench 106. In some embodiments, some or all of the trenches may be connected to each other to form an isolation island of semiconductor material-for example, in some embodiments, the trench 106 may define the boundary of a single device that is later separated from a wafer of semiconductor material. A single device formed on a wafer of a device may have trenches connected to each other to define the boundary of the device or an isolation island of semiconductor material within the device, and isolated from each other and formed within the isolation island of semiconductor material One or more other ditches. FIG. 3 illustrates a method of forming a device. In block 120, a group III nitride structure with a buried p-type region is grown on a growth substrate. In block 122, the trench 106 is formed in a grown III-nitride structure. The trench 106 is shown in FIGS. 1 and 2. The trench 106 may be formed by any suitable technique, including, for example, dry etching, wet etching, or a combination of dry etching and wet etching. In some embodiments, the method of forming the trench can affect the diffusion of hydrogen out of the exposed surface of the semiconductor material formed by etching the trench. For example, p-type GaN is known to be converted to n-type GaN during dry etching. If the thickness of the p-type surface converted to n-type is too large, the diffusion of hydrogen can be blocked, so that hydrogen accumulates at the type-converted surface and cannot escape. Accordingly, in some embodiments, after dry etching to form the trench 106, a wet etch cleaning may be used to clean the surface of the trench to remove the n-type conversion layer, or to reduce the thickness of the n-type conversion layer to hydrogen easily Thickness spreads through it. In some embodiments, the semiconductor structure may be selectively grown to form trenches during growth, as shown in FIGS. 7 and 8. For example, as shown in FIG. 7, a group III nitride film 102 and a p-type region 100 are grown on a substrate 30. A mask material 120 (such as SiO 2 ) may be disposed on the p-type region 100 and then patterned so that the mask material remains in the region where the trench is formed. The mask material is not limited to the position shown in FIG. 7. For example, in various embodiments, the masking material is formed directly on the growth substrate, on one surface of the partially grown group III nitride film 102, on the surface of a fully grown group III nitride film 102, partially grown On one surface of the p-type region 100, or on the surface of the fully grown p-type region 100, as shown. The mask material can be formed in any layer of the device, on any surface (including directly formed on the growth substrate 30), has any thickness, and can extend through multiple layers, as long as the mask material and the p-type region 100 At least a part is in direct contact. The group III nitride film 104 is grown on the mask material 120. The growth will eventually cover the mask material via lateral overgrowth, so that the regions 122 between adjacent mask regions are filled with III-nitride material, as depicted in FIG. 8. When the die is cut after growth, a wet etch or other suitable technique can be used to remove the mask material, thereby generating an embedded trench 124 through which hydrogen can escape during activation annealing. During activation annealing, hydrogen escapes from the embedded trench through the side of the wafer, where the embedded trench is exposed to the surrounding environment. Returning to FIG. 3, in block 124, the annealed III-nitride structure is activated to activate the buried p-type by, for example, driving off hydrogen that has formed a complex with the p-type dopant in the p-type region region. FIGS. 4, 5 and 6 show devices including a buried p-type region that can be activated by trench formation and annealing, as shown in FIGS. 1, 2, and 3. FIG. 4 shows a device in which the p-type region is grown before the n-type region. 5 and 6 illustrate devices including tunnel junctions. For clarity, the ditch is omitted from Figs. 4, 5 and 6. In particular, the devices depicted in FIGS. 4, 5 and 6 can be, for example, about 1 mm on one side, meaning that tens or even hundreds of trenches can be formed in a single device. In any of the devices depicted in FIGS. 4, 5, and 6, one or more of the trenches may be used as vias in which the metal contacts of the buried layer of the device are placed, as noted above description. In some embodiments, the p-type region of a III-nitride device is grown before the light-emitting layer and the n-type region. In the conventional group III nitride LED, the n-type region is first grown on a substrate, followed by the light-emitting layer and the p-type semiconductor. The internal field of a group III nitride LED grown under the n-side increases as the forward bias increases. Therefore, as the device bias (current) increases, the internal electric field increases, thereby reducing electron hole overlap, and thereby reducing radiation efficiency. The devices are grown in reverse order (where the p-type region is first grown on the substrate) to invert the inner field. In a group III nitride LED grown under the p-side, the internal field system is opposite to the built-in polarization field. Therefore, as the forward bias (current) increases, the radiation efficiency of this device can increase. FIG. 4 shows an example of a device in which the p-type region is grown before the light-emitting layer and the n-type region. This semiconductor structure may incorporate any suitable device; embodiments of the invention are not limited to the vertical devices shown. In embodiments where the original growth substrate is removed (such as, for example, a flip chip device), the structure 102 may be completely removed to electrically contact the p-type region, or a hole / ditch may be etched through the structure 102 To expose a portion of the p-type region on which a metal contact can be formed. In embodiments where the substrate remains (such as, for example, a lateral die device), one contact may be placed on the top surface of the semiconductor structure, and the other contact may be placed to expose the p-type region by etching Expose one on the surface. The device shown in FIG. 4 includes a semiconductor structure 10 grown on a growth substrate (not shown). The p-type region 12 is grown first, and then includes an active or light-emitting region of at least one light-emitting layer 14, and then an n-type region 16. The p-type region 12 corresponds to the buried p-type region 100 of FIG. 1; the active region 14 and the n-type region 16 correspond to the group III nitride film 104 of FIG. 1; the group III nitride film 102 of FIG. 1 may be a core The crystal growth or buffer structure (not shown in the figure) may be omitted. A metal p-contact 18 is disposed on the p-type region 12; a metal n-contact 20 is disposed on the n-type region 16. The semiconductor structure 10 includes a light emitting or active region sandwiched between the n-type region and the p-type region. The n-type region 16 may include a plurality of layers with different compositions and dopant concentrations, including, for example, n-type or even p-designed for specific optical properties, material properties, or electrical properties required for the light-emitting region for efficiently emitting light Type device layer. The light emitting layer 14 may be included in the light emitting or active area. Examples of suitable light emitting regions include a single thick or thin light emitting layer, or a multiple quantum well light emitting region including multiple thin or thick light emitting layers separated by a barrier layer. The p-type region 12 may include a plurality of layers with different compositions, thicknesses, and dopant concentrations, including preparation layers, such as buffer layers or nucleation crystal growth layers, and / or layers designed to facilitate removal of the growth substrate, which may It is p-type, n-type or unintentionally doped, and unintentionally doped layers or n-type layers. After growth, the semiconductor structure can be processed into any suitable device. In some embodiments, a III-nitride device includes a tunnel junction. A tunnel junction (TJ) is a structure that allows electrons to tunnel from the valence band of a p-type layer to the conduction band of an n-type layer with reverse bias. When an electron tunnels, a hole remains behind the p-type layer, so that carriers are generated in both layers. Accordingly, in an electronic device (such as a diode) in which only a small leakage current flows with a reverse bias, a large current can be carried across a tunnel junction with a reverse bias. A tunnel junction requires a specific alignment of the conduction band and the valence band at the p / n tunnel junction. It is usually used in other material systems with very high doping (such as p ++ / n ++ junction in (Al) GaAs material system Reached). Group III nitride materials have an inherent polarization that generates an electric field at the heterogeneous interface between different alloy components. This polarization field can be used to achieve the required band alignment for tunneling. 5 and 6 illustrate two devices including tunnel junctions. In the device of FIG. 5, a tunnel junction is placed between the p-type region and the metal contact that injects current into the p-type region. The contact may be formed on an n-type layer, which may have a better sheet resistance than the p-type layer and therefore better current spreading. In the device illustrated in FIG. 5, the n-type layer is used as both the positive and negative terminals of the LED by converting holes from a p-type region to electrons in an n-type contact layer through a tunnel junction The contact layer. The device of FIG. 5 includes an n-type region 32 grown on a growth substrate, followed by a light-emitting layer 34 (which can be disposed in a light-emitting region) and a p-type region 36. The n-type region 32, the light-emitting layer 34, and the p-type region 36 are described above in the context accompanying FIG. A tunnel junction 38 is formed on the p-type region 36. In some embodiments, the tunnel junction 38 includes a highly doped p-type layer (also referred to as a p ++ layer) in direct contact with the p-type region 36 and a highly doped n-type layer in direct contact with the p ++ layer ( Also referred to as an n ++ layer). (In some embodiments, the p ++ layer of the tunnel junction 38 may serve as a p-type region in the device, so that a separate p-type region is not required). In some embodiments, the tunnel junction 38 includes a layer sandwiched between the p ++ layer and the n ++ layer, which is a component different from the p ++ layer and the n ++ layer. In some embodiments, the tunnel junction 38 includes an InGaN layer sandwiched between the p ++ layer and the n ++ layer. In some embodiments, the tunnel junction 38 includes an AlN layer sandwiched between the p ++ layer and the n ++ layer. The tunnel junction 38 is in direct contact with the n-type layer 40, as described below. The p ++ layer may be, for example, InGaN or GaN doped with an acceptor (such as Mg or Zn) at a concentration of about 10 18 cm −3 to about 5 × 10 20 cm −3 . In some embodiments, the p ++ layer is doped to a concentration of about 2 × 10 20 cm −3 to about 4 × 10 20 cm −3 . The n ++ layer may be, for example, InGaN or GaN doped with an acceptor (such as Si or Ge) at a concentration of about 10 18 cm −3 to about 5 × 10 20 cm −3 . In some embodiments, the n ++ layer is doped to a concentration of about 7 × 10 19 cm −3 to about 9 × 10 19 cm −3 . The tunnel junction 38 is generally very thin, for example, the tunnel junction 38 may have a total thickness in the range from about 2 nm to about 100 nm, and each of the p ++ layer and n ++ layer may have a thickness of from about 1 nm To a thickness in the range of about 50 nm. In some embodiments, each of the p ++ layer and the n ++ layer may have a thickness in the range from about 25 nm to about 35 nm. The p ++ layer and n ++ layer may not necessarily be the same thickness. In one embodiment, the p ++ layer is 15 nm Mg-doped InGaN and the n ++ layer is 30 nm Si-doped GaN. The p ++ layer and n ++ layer may have a graded dopant concentration. For example, a portion of the p ++ layer adjacent to the underlying p-type region 36 may have a dopant concentration graded from the dopant concentration of the underlying p-type region to a desired dopant concentration in the p ++ layer. Similarly, the n ++ layer may have a dopant concentration ranging from a maximum value adjacent to the p ++ layer to a minimum value adjacent to the n-type layer 40 formed on the tunnel junction 38. The tunnel junction 38 is made thin enough and sufficiently doped so that the tunnel junction 38 shows a low series voltage drop when conducting current in a reverse bias mode. In some embodiments, the voltage drop across the tunnel junction 38 is about 0.1 V to about 1 V. Embodiments that include an InGaN or AlN or other suitable layer between the p ++ layer and the n ++ layer can leverage the polarization field in the III-nitride to help align the band for tunneling. This polarization effect can reduce the doping requirements in the n ++ and p ++ layers and reduce the required tunneling distance (which may allow higher currents). The composition of the layer between the p ++ layer and the n ++ layer may be different from the composition of the p ++ layer and the n ++ layer, and / or may be selected to cause polarization between different materials attributable to the group III nitride material system The band of charge is realigned. Examples of suitable tunnel junctions are described in US8039352 B2, which is incorporated herein by reference. An n-type contact layer 40 is formed on the tunnel junction 38 and directly contacts the n ++ layer. In the device of FIG. 5, the p ++ layer of the p-type region 36 and the tunnel junction 38 corresponds to the p-type region 100 of FIG. 1; the n ++ layer of the tunnel junction 38 and the n-type contact layer 40 correspond to the group III nitrogen of FIG. The compound film 104; the n-type region 32 and the active region 34 correspond to the group III nitride film 102 of FIG. The first and second metal contacts 44 and 42 are formed on the n-type contact layer 40 and the n-type region 32, respectively. A mesa may be etched to form a flip chip device (as shown in FIG. 5) or any other suitable device structure may be used. The first and second metal contacts 44 and 42 may be the same material (such as aluminum), although this is not required; any suitable contact metal (s) may be used. In the device of FIG. 6, multiple LEDs are grown on top of each other and connected in series via a tunnel junction. In the device of FIG. 6, multiple LEDs are generated within the coverage area of a single LED, which can greatly increase the luminous flux generated per unit area. In addition, by driving LEDs connected by a tunnel junction at a lower drive current, each LED can operate according to its peak efficiency. In a single LED, this will cause one of the light outputs to decrease, but by having two or more LEDs connected in series in a given wafer area, the light output can be maintained and the efficiency greatly improved. Therefore, the tunnel junction device illustrated in FIG. 6 can be used in applications requiring high efficiency and / or applications requiring high throughput per unit area. The device of FIG. 6 includes an n-type region 32 grown on a growth substrate, followed by a light-emitting layer 34 (which can be disposed in a light-emitting region) and a p-type region 36 (as described above, the tunnel junction is The p ++ layer can serve as the p-type region 36, so that a separate p-type region is not required). The n-type region 32, the light-emitting layer 34, and the p-type region 36 are described above in the context accompanying FIG. As described above, a tunnel junction 38 is formed on the p-type region 36. A second device structure (including a second n-type region 46, a second light-emitting layer 48, and a second p-type region 50) is formed on the tunnel junction 38. The tunnel junction 38 is oriented so that the p ++ layer directly contacts the p-type region 36 of the first LED, and the n ++ layer directly contacts the n-type region 46 of the second LED. In the device of FIG. 6, the p-type region 36 and the p ++ layer of the tunnel junction 38 correspond to the p-type region 100 of FIG. 1; the n ++ layer, the n-type layer 46, the active region 48, and the p-type region 50 of the tunnel junction 38 Corresponding to the group III nitride film 104 of FIG. 1 (if the trench is in direct contact with the p-type region 50, the trench will also activate the p-type region 50, although the p-type region 50 (if it is the last layer grown) can also A conventional annealing to activate); the n-type region 32 and the active region 34 correspond to the group III nitride film 102 of FIG. The first and second metal contacts 54 and 52 are formed on the n-type region 32 of the first LED and the p-type region 50 of the second LED, respectively. A mesa can be etched to form a flip chip device (as shown in FIG. 6), or any other suitable device structure can be used. In some embodiments, an additional tunnel junction and n-type layer may be formed on the p-type region 50 of the second LED, so that the second metal contact 52 is formed on an n-type layer, as shown in the device of FIG. 5 Shown in. Although two active regions are shown in FIG. 6, if the p-type region adjacent to each active region is separated from the n-type region adjacent to the next active region by a tunnel junction, any number of active regions can be Included between the two metal contacts shown. Since the device of FIG. 6 has only two contacts, the two light-emitting layers emit light at the same time and cannot be activated individually and individually. In other embodiments, individual LEDs in the stack can be activated individually by forming additional contacts. In some embodiments, a device may have sufficient junctions so that the device can operate with a typical line voltage (such as, for example, 110 volts, 220 volts, etc.). The two light-emitting layers can be manufactured to have the same composition, so that they emit light of the same color, or have different compositions, so that they emit light of different colors (ie, different peak wavelengths). For example, three active area devices with one of two contacts may be manufactured such that the first active area emits red light, the second active area emits blue light, and the third active area emits green light. When activated, the device can produce white light. Since the active areas are stacked so that they seem to emit light from the same area, these devices can avoid the problem in which color mixing is present in one device that combines red, blue, and green light from adjacent non-stacked active areas. In a device with an active region that emits light of different wavelengths, the active region that produces the shortest wavelength of light can be positioned closest to the surface from which the light is extracted, generally speaking it is grown in sapphire, SiC or GaN in an LED Substrate. Placing the shortest wavelength active region close to the output surface can minimize the loss of absorption due to quantum wells in other active regions, and can be located by positioning the longer wavelength active region closer to the heat sink formed by the junction Reduce thermal shock to more sensitive longer wavelength quantum wells. The quantum well layer can also be thin enough so that the absorption of light in the quantum well layer is low. The color of the mixed light emitted from the device can be controlled by selecting the number of active areas that emit light of each color. For example, the human eye is very sensitive to green photons and less sensitive to red and blue photons. To produce balanced white light, a stacked active area device can have a single green active area and multiple blue and red active areas. The devices of FIGS. 4, 5 and 6 are formed by growing a III-nitride semiconductor structure on a growth substrate 30, as is known in the art. The growth substrate is usually sapphire, but can be any suitable substrate (such as, for example, SiC, Si, GaN) or a composite substrate (such as, for example, GaN on a sapphire template). One surface of the growth substrate on which the III-nitride semiconductor structure is grown can be patterned, roughened, or textured before growth, which can improve the extraction of light from the device. A surface of the growth substrate opposite to the growth surface (ie, the surface through which most of the light in a flip-chip configuration is extracted) can be patterned, roughened, or textured before or after growth, which can improve extraction from the device Light. Metal contacts often include multiple conductive layers (such as a reflective metal and a protective metal (which can prevent or reduce electromigration of the reflective metal)). The reflective metal is often silver, but any suitable material (several) can be used. The metal contacts are electrically isolated from each other to fill a gap with a dielectric (such as silicon oxide or any other suitable material). A plurality of through holes for exposing the portion of the n-type region 32 can be formed; the metal contacts are not limited to the configurations shown in FIGS. 4, 5 and 6. The metal contacts can be redistributed to form a pad with a dielectric / metal stack, as is known in the art. To form an electrical connection to the LED, one or more interconnects are formed on the two metal contacts shown or electrically connected to the two metal contacts shown. The interconnect may be, for example, solder, bumps, gold layers, or any other suitable structure. The substrate 30 may be thinned or completely removed. In some embodiments, the surface of the substrate 30 exposed by thinning is patterned, textured, or roughened to improve light extraction. Any of the devices described herein can be combined with a wavelength conversion structure. The wavelength conversion structure may contain one or more wavelength conversion materials. The wavelength conversion structure may be directly connected to the LED, placed close to the LED but not directly connected to or separated from the LED. The wavelength conversion structure may be any suitable structure. The wavelength conversion structure can be formed separately from the LED, or can be formed together with the LED in situ. Examples of wavelength conversion structures formed separately from LEDs include ceramic wavelength conversion structures that can be formed by sintering or any other suitable process; wavelength conversion materials, such as powder phosphors, which are disposed in transparent materials, such as polysilicon or glass, It is rolled, cast, or otherwise formed into a sheet, which is then cut into individual wavelength conversion structures; and wavelength conversion materials, such as placed on a transparent material, such as polysiloxane, which are formed into a flexible sheet, which Can be laminated or otherwise placed on an LED. Examples of wavelength conversion structures formed in situ include wavelength conversion materials, such as powder phosphors, mixed with a transparent material, such as polysiloxane, and dispensed, screen-printed, wax-printed, molded, or otherwise placed in LED; and wavelength conversion material, which is coated on the LED by electrophoresis, steam, or any other suitable type of deposition. Multiple forms of wavelength conversion structures can be used in a single device. As just an example, a ceramic wavelength conversion member may be combined with a molded wavelength conversion member, in which the same or different wavelength conversion materials are located in the ceramic and the molded member. The wavelength conversion structure may include, for example, conventional phosphors, organic phosphors, quantum dots, organic semiconductors, group II-VI or group III-V semiconductors, group II-VI or group III-V semiconductor quantum dots or nanocrystals , Dyes, polymers or other materials that emit light. The wavelength conversion material absorbs the light emitted by the LED and emits light of one or more different wavelengths. The unconverted light emitted by the LED is usually part of the final spectrum of light extracted from the structure, although it need not be. Examples of general combinations include a blue-emitting LED combined with a yellow-emitting wavelength conversion material, a blue-emitting LED combined with a green- and red-emitting wavelength conversion material, and a blue- and yellow-emitting wavelength-conversion material combination A UV-emitting LED and a UV-emitting LED in combination with a wavelength conversion material that emits blue, green, and red light. Wavelength conversion materials that emit light of other colors can be added to adjust the spectrum of light extracted from the structure. The embodiments described herein may incorporate any suitable light emitting device. The embodiments of the present invention are not limited to the specific structures shown. Some features of some embodiments may be omitted or implemented together with other embodiments. The device elements and method elements described herein are interchangeable and used in or omitted from any of the examples or embodiments described herein. Although the semiconductor light emitting device is one of group III nitride LEDs emitting blue light or UV light in the examples and embodiments described above, semiconductor light emitting devices other than LEDs (such as laser diodes) are Within the category. In addition, the principles described herein can be applied to semiconductor light emitting devices or made from other material systems (such as other group III-V materials, group III phosphides, group III arsenides, group II-VI materials, ZnO or Si-based materials) Into other devices. The present invention has been described in detail, and those skilled in the art should understand that in view of the present invention, the present invention can be modified without departing from the spirit of the inventive concept described herein. Therefore, it is not intended that the scope of the invention be limited to the specific embodiments shown and described.