JP5908587B2 - フィードバックループにおける位相補正を備えた位相ロックドループ - Google Patents
フィードバックループにおける位相補正を備えた位相ロックドループ Download PDFInfo
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- JP5908587B2 JP5908587B2 JP2014525058A JP2014525058A JP5908587B2 JP 5908587 B2 JP5908587 B2 JP 5908587B2 JP 2014525058 A JP2014525058 A JP 2014525058A JP 2014525058 A JP2014525058 A JP 2014525058A JP 5908587 B2 JP5908587 B2 JP 5908587B2
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Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
- H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Pulse Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/204,448 | 2011-08-05 | ||
| US13/204,448 US8497716B2 (en) | 2011-08-05 | 2011-08-05 | Phase locked loop with phase correction in the feedback loop |
| PCT/US2012/049226 WO2013022679A1 (en) | 2011-08-05 | 2012-08-01 | Phase locked loop with phase correction in the feedback loop |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2014527755A JP2014527755A (ja) | 2014-10-16 |
| JP5908587B2 true JP5908587B2 (ja) | 2016-04-26 |
Family
ID=46750446
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014525058A Active JP5908587B2 (ja) | 2011-08-05 | 2012-08-01 | フィードバックループにおける位相補正を備えた位相ロックドループ |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US8497716B2 (enExample) |
| EP (1) | EP2740219B1 (enExample) |
| JP (1) | JP5908587B2 (enExample) |
| KR (1) | KR101633886B1 (enExample) |
| CN (1) | CN103814524B (enExample) |
| IN (1) | IN2014CN00291A (enExample) |
| WO (1) | WO2013022679A1 (enExample) |
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| US8629700B2 (en) * | 2012-01-19 | 2014-01-14 | Qualcomm Incorporated | Capacitive multiplication in a phase locked loop |
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| US8786337B2 (en) * | 2012-05-14 | 2014-07-22 | Ensphere Solutions, Inc. | Low jitter clock generator for multiple lanes high speed data transmitter |
| US8674731B1 (en) * | 2013-01-22 | 2014-03-18 | Applied Micro Circuits Corporations | Fractional phase-locked loop with dynamic divide ratio adjustment |
| US9020089B2 (en) * | 2013-07-12 | 2015-04-28 | Infineon Technologies Ag | Phase-locked loop (PLL)-based frequency synthesizer |
| US9762250B2 (en) | 2013-11-27 | 2017-09-12 | Silicon Laboratories Inc. | Cancellation of spurious tones within a phase-locked loop with a time-to-digital converter |
| DE102014104478B4 (de) * | 2014-03-31 | 2022-05-12 | Apple Inc. | Eine Schaltung, eine integrierte Schaltung, ein Sender, ein Empfänger, ein Sende-Empfangs-Gerät, ein Verfahren zum Erhalten von Kalibrierungsdaten und ein Verfahren zum Erzeugen einesLokaloszillatorsignals |
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| CN107528588A (zh) * | 2016-06-21 | 2017-12-29 | 马维尔国际贸易有限公司 | 模拟分数n锁相环 |
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| US9853650B1 (en) * | 2016-11-21 | 2017-12-26 | Realtek Semiconductor Corp. | Method and apparatus of frequency synthesis |
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| US10439793B2 (en) * | 2017-05-03 | 2019-10-08 | Global Unichip Corporation | Device and method for recovering clock and data |
| US10944409B2 (en) * | 2017-07-24 | 2021-03-09 | Intel Corporation | Phase-locked loop and method for the same |
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| US10541721B2 (en) * | 2017-09-26 | 2020-01-21 | Analog Devices Global Unlimited Company | Modulation index adjustment |
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| US10680626B2 (en) * | 2017-10-27 | 2020-06-09 | Mediatek Inc. | Method and associated signal system improving mitigation of injection-pulling effect |
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| KR102527388B1 (ko) * | 2018-04-06 | 2023-04-28 | 삼성전자주식회사 | 디지털-타임 컨버터 회로를 포함하는 위상 고정 루프 회로, 클럭 신호 생성기 및 이의 동작 방법 |
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| CN108809305B (zh) * | 2018-05-02 | 2021-10-08 | 深圳市鼎阳科技股份有限公司 | 一种减小射频信号源杂散的方法和射频信号源 |
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| CN113508529B (zh) * | 2019-03-30 | 2025-10-03 | 华为技术有限公司 | 多通道多载波收发机 |
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| CN110719100B (zh) * | 2019-11-19 | 2021-04-23 | 复旦大学 | 一种分数频全数字锁相环及其控制方法 |
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| CN113810046B (zh) * | 2020-06-12 | 2025-05-16 | 武汉芯泰科技有限公司 | 一种快速自动频率校准装置及方法 |
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| CN115242243B (zh) * | 2022-07-28 | 2025-10-31 | 西安电子科技大学芜湖研究院 | 一种延迟锁相环电路及其控制方法 |
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| CN116015287B (zh) * | 2022-12-31 | 2024-03-19 | 成都电科星拓科技有限公司 | 一种基于频率转电压电路校正tdc步进的方法及装置 |
| CN119449023A (zh) * | 2024-10-10 | 2025-02-14 | 苏州雷科微技术有限公司 | 一种基于多路射频锁相环的功率合成电路与自校正方法 |
| KR102845037B1 (ko) | 2024-12-12 | 2025-08-13 | 주식회사 램쉽 | 위상 고정 루프용 모드 변환형 디지털 시간 변환기 |
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-
2011
- 2011-08-05 US US13/204,448 patent/US8497716B2/en active Active
-
2012
- 2012-08-01 CN CN201280043541.1A patent/CN103814524B/zh not_active Expired - Fee Related
- 2012-08-01 JP JP2014525058A patent/JP5908587B2/ja active Active
- 2012-08-01 IN IN291CHN2014 patent/IN2014CN00291A/en unknown
- 2012-08-01 EP EP20120751182 patent/EP2740219B1/en not_active Not-in-force
- 2012-08-01 WO PCT/US2012/049226 patent/WO2013022679A1/en not_active Ceased
- 2012-08-01 KR KR1020147006009A patent/KR101633886B1/ko not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN103814524B (zh) | 2016-08-24 |
| CN103814524A (zh) | 2014-05-21 |
| IN2014CN00291A (enExample) | 2015-04-03 |
| US20130033293A1 (en) | 2013-02-07 |
| EP2740219A1 (en) | 2014-06-11 |
| EP2740219B1 (en) | 2015-05-20 |
| KR101633886B1 (ko) | 2016-07-08 |
| WO2013022679A1 (en) | 2013-02-14 |
| KR20140058608A (ko) | 2014-05-14 |
| JP2014527755A (ja) | 2014-10-16 |
| US8497716B2 (en) | 2013-07-30 |
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