JP5898587B2 - パターン形成方法 - Google Patents
パターン形成方法 Download PDFInfo
- Publication number
- JP5898587B2 JP5898587B2 JP2012176841A JP2012176841A JP5898587B2 JP 5898587 B2 JP5898587 B2 JP 5898587B2 JP 2012176841 A JP2012176841 A JP 2012176841A JP 2012176841 A JP2012176841 A JP 2012176841A JP 5898587 B2 JP5898587 B2 JP 5898587B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- polymer
- processed
- pattern
- physical guide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 35
- 230000007261 regionalization Effects 0.000 title description 4
- 229920000642 polymer Polymers 0.000 claims description 43
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 10
- 239000010410 layer Substances 0.000 description 24
- 229920001400 block copolymer Polymers 0.000 description 18
- 238000002408 directed self-assembly Methods 0.000 description 15
- 239000000463 material Substances 0.000 description 15
- 239000000758 substrate Substances 0.000 description 11
- 229910003481 amorphous carbon Inorganic materials 0.000 description 10
- 238000000926 separation method Methods 0.000 description 9
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 8
- 239000004926 polymethyl methacrylate Substances 0.000 description 8
- XLLIQLLCWZCATF-UHFFFAOYSA-N 2-methoxyethyl acetate Chemical compound COCCOC(C)=O XLLIQLLCWZCATF-UHFFFAOYSA-N 0.000 description 4
- 230000018109 developmental process Effects 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000002202 Polyethylene glycol Substances 0.000 description 2
- 239000004793 Polystyrene Substances 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 229920001223 polyethylene glycol Polymers 0.000 description 2
- 229920005604 random copolymer Polymers 0.000 description 2
- 238000001338 self-assembly Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000001900 extreme ultraviolet lithography Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000005191 phase separation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000009154 spontaneous behavior Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3088—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Inorganic Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Shaping Of Tube Ends By Bending Or Straightening (AREA)
- Drying Of Semiconductors (AREA)
Description
102 被加工膜
103 SOC膜
104 SOG膜
104a 傾斜面
107 ブロックコポリマー層
Claims (5)
- 被加工膜上に第1膜を形成し、
前記第1膜上に、前記第1膜より撥水性の高い第2膜を形成し、
前記第2膜に、ホール側壁部が傾斜面となるホールパターンを形成し、
前記ホールパターンが形成された前記第2膜をマスクに前記第1膜を加工して物理ガイドを形成し、
前記物理ガイドのホール部内に少なくとも2種以上のセグメントを含むポリマー層を形成し、
前記ポリマー層をミクロ相分離させ、第1ポリマー部及び第2ポリマー部を含む自己組織化相を形成し、
前記自己組織化相の前記第1ポリマー部を除去し、
前記第1ポリマー部の除去後、前記第2ポリマー部をマスクに前記被加工膜を加工する、
パターン形成方法。 - 被加工膜上に、凹部の側壁面の少なくとも上部が傾斜面となっている物理ガイドを形成し、
前記物理ガイドの前記凹部内に少なくとも2種以上のセグメントを含むポリマー層を形成し、
前記ポリマー層をミクロ相分離させ、第1ポリマー部及び第2ポリマー部を含む自己組織化相を形成し、
前記自己組織化相を用いて前記被加工膜を加工する、
パターン形成方法。 - 前記自己組織化相の前記第1ポリマー部を除去し、
前記第1ポリマー部の除去後、前記第2ポリマー部をマスクに前記被加工膜を加工する、
請求項2に記載のパターン形成方法。 - 前記被加工膜上に第1膜を形成し、
前記第1膜上に第2膜を形成し、
前記第2膜に、ホール側壁部が傾斜面となるホールパターンを形成し、
前記ホールパターンが形成された前記第2膜をマスクに前記第1膜を加工して前記物理ガイドを形成することを特徴とする請求項2に記載のパターン形成方法。 - 前記第2膜は前記第1膜より高い撥水性を有することを特徴とする請求項4に記載のパターン形成方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012176841A JP5898587B2 (ja) | 2012-08-09 | 2012-08-09 | パターン形成方法 |
US13/762,892 US20140045341A1 (en) | 2012-08-09 | 2013-02-08 | Pattern forming method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012176841A JP5898587B2 (ja) | 2012-08-09 | 2012-08-09 | パターン形成方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014036126A JP2014036126A (ja) | 2014-02-24 |
JP5898587B2 true JP5898587B2 (ja) | 2016-04-06 |
Family
ID=50066516
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012176841A Expired - Fee Related JP5898587B2 (ja) | 2012-08-09 | 2012-08-09 | パターン形成方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US20140045341A1 (ja) |
JP (1) | JP5898587B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103999191B (zh) * | 2011-12-15 | 2016-10-19 | 英特尔公司 | 用于单次曝光-自对准的双重、三重以及四重图案化的方法 |
US9466527B2 (en) | 2014-02-23 | 2016-10-11 | Tokyo Electron Limited | Method for creating contacts in semiconductor substrates |
US9229326B2 (en) * | 2014-03-14 | 2016-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for integrated circuit patterning |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6117793A (en) * | 1998-09-03 | 2000-09-12 | Micron Technology, Inc. | Using silicide cap as an etch stop for multilayer metal process and structures so formed |
JP5414011B2 (ja) * | 2006-05-23 | 2014-02-12 | 国立大学法人京都大学 | 微細構造体、パターン媒体、及びそれらの製造方法 |
US20100327413A1 (en) * | 2007-05-03 | 2010-12-30 | Lam Research Corporation | Hardmask open and etch profile control with hardmask open |
JP5118073B2 (ja) * | 2009-01-26 | 2013-01-16 | 信越化学工業株式会社 | レジスト下層膜形成方法及びこれを用いたパターン形成方法 |
US9233840B2 (en) * | 2010-10-28 | 2016-01-12 | International Business Machines Corporation | Method for improving self-assembled polymer features |
JP5537400B2 (ja) * | 2010-12-22 | 2014-07-02 | 株式会社東芝 | パターン形成方法及び装置 |
-
2012
- 2012-08-09 JP JP2012176841A patent/JP5898587B2/ja not_active Expired - Fee Related
-
2013
- 2013-02-08 US US13/762,892 patent/US20140045341A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
JP2014036126A (ja) | 2014-02-24 |
US20140045341A1 (en) | 2014-02-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5802233B2 (ja) | パターン形成方法 | |
JP5752655B2 (ja) | パターン形成方法 | |
JP5758363B2 (ja) | パターン形成方法 | |
JP5764102B2 (ja) | パターン形成方法 | |
JP5758422B2 (ja) | パターン形成方法 | |
JP5902573B2 (ja) | パターン形成方法 | |
JP6219674B2 (ja) | ブロック共重合体を使用したエッチング | |
TWI546617B (zh) | 藉由嵌段共聚物之自組裝而在基板上提供微影特徵之方法 | |
JP5813604B2 (ja) | パターン形成方法 | |
JP2015023063A (ja) | パターン形成方法及びマスクパターンデータ | |
US20140242799A1 (en) | Pattern formation method and method for manufacturing semiconductor device | |
TW201727360A (zh) | 形成圖案的方法 | |
US20130210226A1 (en) | Pattern formation method | |
JP5898587B2 (ja) | パターン形成方法 | |
JP2014135435A (ja) | 半導体装置の製造方法 | |
JP2016058584A (ja) | パターン形成方法、フォトマスク、及びナノインプリント用テンプレート | |
US9371427B2 (en) | Pattern forming method | |
JP6262044B2 (ja) | パターン形成方法および半導体装置の製造方法 | |
JP2014060189A (ja) | パターン形成方法及び塗布装置 | |
TWI569094B (zh) | 藉由嵌段共聚物之自組裝而在基板上提供微影特徵之方法 | |
JP6059608B2 (ja) | パターン形成方法 | |
US20180275519A1 (en) | Pattern Formation Method | |
US20140045124A1 (en) | Method of manufacturing semiconductor device | |
JP6346132B2 (ja) | パターン形成方法 | |
Sato et al. | Directed self-assembly lithography for half-pitch sub-15 nm pattern fabrication process |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20140828 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20150617 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20150623 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150805 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20160205 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20160304 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 5898587 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
LAPS | Cancellation because of no payment of annual fees |