JP5891562B2 - 差分論理によって保護される暗号化回路において異常を検出するための方法、及び当該方法を実現するための回路 - Google Patents
差分論理によって保護される暗号化回路において異常を検出するための方法、及び当該方法を実現するための回路 Download PDFInfo
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- JP5891562B2 JP5891562B2 JP2011522468A JP2011522468A JP5891562B2 JP 5891562 B2 JP5891562 B2 JP 5891562B2 JP 2011522468 A JP2011522468 A JP 2011522468A JP 2011522468 A JP2011522468 A JP 2011522468A JP 5891562 B2 JP5891562 B2 JP 5891562B2
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000011156 evaluation Methods 0.000 claims abstract description 30
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- 238000001514 detection method Methods 0.000 claims description 54
- 239000013598 vector Substances 0.000 claims description 8
- 230000000153 supplemental effect Effects 0.000 claims description 3
- 230000006870 function Effects 0.000 abstract description 14
- 238000004364 calculation method Methods 0.000 abstract description 13
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
- G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/55—Detecting local intrusion or implementing counter-measures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/602—Providing cryptographic facilities or services
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computer Security & Cryptography (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- General Health & Medical Sciences (AREA)
- Bioethics (AREA)
- Health & Medical Sciences (AREA)
- Tests Of Electronic Circuits (AREA)
- Logic Circuits (AREA)
- Emergency Protection Circuit Devices (AREA)
- Selective Calling Equipment (AREA)
- Storage Device Security (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Hardware Redundancy (AREA)
Description
− 暗号化及びその双対処理である復号化による情報の機密性
− 又は、署名及び署名照合の処理による情報の一貫性のみ
− 暗号化動作時に測定された消費電力の測定値に基づいて中央装置によって実行される処理の特定を試みるSPA(Simple Power Analysis)。
− 消費電力の差分解析DPA(Differential Power Analysis)。消費電力の多くの測定で統計的演算(ランダムメッセージに対し、一定の鍵を使用して暗号化動作時に実行し、鍵のごく一部分に対して行われる仮定を有効または無効にする)を使用する。
− 「テンプレート」タイプの攻撃。第1の段階で、機密情報が一切含まれないということを除き、攻撃対象の装置と同じ装置を使用して、鍵のごく一部分の値によって指数化された消費モデルを構築し、第2の段階で、攻撃対象の装置の消費電力の数回の測定を使用して、測定された消費電力と最も近いモデルを特定し、これによってこのサブ鍵の値を特定する。
− (0、0)はプリチャージ段階時の静止状態:aの値は定義されておらず、Ωで示される。
− (1、0)は、評価段階中のアクティブ状態。ここでa=1
− (0、1)は、評価段階中の他のアクティブ状態。ここでa=0
st=T(at、bt) (1)
sf=F(af、bf) (2)
− プリチャージ段階で、デュアル信号のペアが状態(Qt、Qf)=(0、0)と異なる。
− 評価段階で、信号のペアが状態(Qt、Qf)=(0、1)又は(Qt、Qf)=(1、0)と異なる。
− プリチャージ状態では、影響を受ける可能性がかなりある。
− 多重故障の場合、その他の変数が修正及び検出され得る。
− ほとんどの攻撃では、両方の信号で同時にビット反転を行うことができない。例えば、温度、電圧、又は周波数を使用することによる前の位置決め時間の違反に基づく攻撃。
− プリチャージ段階では、PRE/EVALは値0を取り、マルチプレクサ35からの出力として「OR」ゲート34の出力が伝送される。
− 評価段階では、PRE/EVALは値1を取り、「XNOR」フリップフロップ33の出力がマルチプレクサ35からの出力として伝送される。
Af=−At−1 (5)
Bf=−Bt−1 (6)
Claims (5)
- 二進数に対応する構成要素で構成されるとともに論理変数と呼ばれる第1の構成要素ペア(at、af)および第2の構成要素ペア(bt、bf)を処理するために構成され、プリチャージ段階でa t とa f とb t とb f とが0であり、評価段階でa t とa f 、b t とb f がそれぞれ補完関係であり、a t とb t が非補完関係であり、セル(T)の第1のネットワークが前記第1の構成要素ペアの第1の構成要素と前記第2の構成要素ペアの第1の構成要素とで論理関数を実行し、デュアルセル(F)の第2のネットワークが前記第1の構成要素ペアの第2の構成要素と前記第2の構成要素ペアの第2の構成要素との補足ロジック内で動作する回路である差分論理によって保護される回路であって、
2つ以上の検出モジュールを具備し、
前記検出モジュールは、それぞれ、
前記第1の構成要素ペアの第1の構成要素と前記第2の構成要素ペアの第1の構成要素とを一まとめにした第1のベクトル(At、Bt)と、前記第1の構成要素ペアの第2の構成要素と前記第2の構成要素ペアの第2の構成要素とを一まとめにした第2のベクトル(Af、Bf)とのそれぞれに、二進数で1のビットを付加し、該ビットを付加した第1のベクトルと該ビットを付加した第2のベクトルとの間で、各ベクトルの要素の乗算累積演算を実行する2つの乗算累積器(81、82)と、
前記2つの乗算累積器による演算の結果の差異を計算し、該計算した差異が前記プリチャージ段階または前記評価段階で、前記2つの乗算累積器による演算の結果に差異が検出された場合に、予め定めた値を出力するゼロコンパレータと
を具備する
ことを特徴とする回路。 - 前記検出モジュールの前記ゼロコンパレータ(84)の出力は、前記2つの演算の結果が一致しない状態の検出により、安定した出力
- 前記回路が暗号化回路であることを特徴とする請求項1または2のいずれか一項に記載の回路。
- 前記回路がFPGAタイプのプログラマブル回路であることを特徴とする請求項1〜3のいずれか一項に記載の回路。
- 前記回路のタイプがASICであることを特徴とする請求項1〜3のいずれか一項に記載の回路。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0855537A FR2935059B1 (fr) | 2008-08-12 | 2008-08-12 | Procede de detection d'anomalies dans un circuit de cryptographie protege par logique differentielle et circuit mettant en oeuvre un tel procede |
FR0855537 | 2008-08-12 | ||
PCT/EP2009/059886 WO2010018071A1 (fr) | 2008-08-12 | 2009-07-30 | Procede de detection d'anomalies dans un circuit de cryptographie protege par logique differentielle et circuit mettant en oeuvre un tel procede |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012505563A JP2012505563A (ja) | 2012-03-01 |
JP5891562B2 true JP5891562B2 (ja) | 2016-03-23 |
Family
ID=40548652
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011522468A Active JP5891562B2 (ja) | 2008-08-12 | 2009-07-30 | 差分論理によって保護される暗号化回路において異常を検出するための方法、及び当該方法を実現するための回路 |
Country Status (10)
Country | Link |
---|---|
US (1) | US8955160B2 (ja) |
EP (1) | EP2324442B1 (ja) |
JP (1) | JP5891562B2 (ja) |
KR (1) | KR101722790B1 (ja) |
CN (1) | CN102124470B (ja) |
AT (1) | ATE545095T1 (ja) |
CA (1) | CA2733667C (ja) |
ES (1) | ES2386061T3 (ja) |
FR (1) | FR2935059B1 (ja) |
WO (1) | WO2010018071A1 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
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FR2929470B1 (fr) * | 2008-03-25 | 2010-04-30 | Groupe Ecoles Telecomm | Procede de protection de circuit de cryptographie programmable, et circuit protege par un tel procede |
US9081929B2 (en) * | 2012-01-06 | 2015-07-14 | New York University | Systems, processes and computer-accessible medium for providing logic encryption utilizing fault analysis |
US10891396B2 (en) | 2016-05-27 | 2021-01-12 | Samsung Electronics Co., Ltd. | Electronic circuit performing encryption/decryption operation to prevent side- channel analysis attack, and electronic device including the same |
FR3091370B1 (fr) | 2018-12-28 | 2021-04-09 | St Microelectronics Rousset | Circuit de protection |
FR3091367B1 (fr) * | 2018-12-28 | 2020-12-18 | St Microelectronics Rousset | Protection d’un microcontrôleur |
CN110321737B (zh) * | 2019-06-28 | 2020-12-11 | 兆讯恒达科技股份有限公司 | 一种数据加密标准协处理器防注入式攻击的方法 |
US11321457B2 (en) * | 2019-09-16 | 2022-05-03 | Nuvoton Technology Corporation | Data-sampling integrity check by sampling using flip-flops with relative delay |
CN112491410B (zh) * | 2020-11-18 | 2023-11-28 | 杭州师范大学 | 一种基于预充电逻辑与掩码技术的功耗恒定性门电路单元 |
US11783026B2 (en) * | 2021-01-05 | 2023-10-10 | Nuvoton Technology Corporation | Processor with in-band fault-injection detection |
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JPH0438793A (ja) * | 1990-06-04 | 1992-02-07 | Toshiba Corp | データ転送制御回路およびこれを用いたダイナミック型半導体記憶装置 |
US5332931A (en) * | 1991-06-24 | 1994-07-26 | Harris Corporation | High speed differential comparator |
GB9611994D0 (en) * | 1996-06-07 | 1996-08-07 | Systolix Ltd | A field programmable processor |
US5825878A (en) * | 1996-09-20 | 1998-10-20 | Vlsi Technology, Inc. | Secure memory management unit for microprocessor |
US7743262B2 (en) * | 1997-07-15 | 2010-06-22 | Silverbrook Research Pty Ltd | Integrated circuit incorporating protection from power supply attacks |
AU2557399A (en) * | 1998-01-02 | 1999-07-26 | Cryptography Research, Inc. | Leak-resistant cryptographic method and apparatus |
US7587044B2 (en) * | 1998-01-02 | 2009-09-08 | Cryptography Research, Inc. | Differential power analysis method and apparatus |
WO2000002342A2 (en) * | 1998-07-02 | 2000-01-13 | Cryptography Research, Inc. | Leak-resistant cryptographic indexed key update |
DE19941682A1 (de) * | 1999-09-01 | 2001-03-15 | Infineon Technologies Ag | Sicherheitsempfindliche Chipkarten |
GB2365153A (en) * | 2000-01-28 | 2002-02-13 | Simon William Moore | Microprocessor resistant to power analysis with an alarm state |
DE10044837C1 (de) * | 2000-09-11 | 2001-09-13 | Infineon Technologies Ag | Schaltungsanordnung und Verfahren zum Detektieren eines unerwünschten Angriffs auf eine integrierte Schaltung |
CN1922564B (zh) * | 2004-02-24 | 2011-01-26 | Nxp股份有限公司 | Ic侵入检测 |
DE102004020576B4 (de) * | 2004-04-27 | 2007-03-15 | Infineon Technologies Ag | Datenverarbeitungsvorrichtung mit schaltbarer Ladungsneutralität und Verfahren zum Betreiben einer Dual-Rail-Schaltungskomponente |
DE102005037357B3 (de) * | 2005-08-08 | 2007-02-01 | Infineon Technologies Ag | Logikschaltung und Verfahren zum Berechnen eines maskierten Ergebnisoperanden |
DE102005055158B4 (de) * | 2005-11-18 | 2008-08-28 | Infineon Technologies Ag | Schaltungsanordnung mit einer Einrichtung zur Erkennung von Manipulationsversuchen und Verfahren zur Erkennung von Manipulationsversuchen bei einer Schaltungsanordnung |
KR100850202B1 (ko) * | 2006-03-04 | 2008-08-04 | 삼성전자주식회사 | Ecc 패스트 몽고매리 전력 래더 알고리즘을 이용하여dfa 에 대응하는 암호화 방법 |
JP2007323019A (ja) * | 2006-06-05 | 2007-12-13 | Sony Corp | 暗号処理装置 |
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JP4453697B2 (ja) * | 2006-12-15 | 2010-04-21 | ソニー株式会社 | 演算処理装置、および演算処理制御方法、並びにコンピュータ・プログラム |
JP2009289104A (ja) * | 2008-05-30 | 2009-12-10 | Dainippon Printing Co Ltd | 故障攻撃を検知する機能を備えたセキュリティデバイス |
-
2008
- 2008-08-12 FR FR0855537A patent/FR2935059B1/fr not_active Expired - Fee Related
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- 2009-07-30 JP JP2011522468A patent/JP5891562B2/ja active Active
- 2009-07-30 CA CA2733667A patent/CA2733667C/en active Active
- 2009-07-30 US US13/058,706 patent/US8955160B2/en active Active
- 2009-07-30 KR KR1020117003337A patent/KR101722790B1/ko active IP Right Grant
- 2009-07-30 WO PCT/EP2009/059886 patent/WO2010018071A1/fr active Application Filing
- 2009-07-30 ES ES09806408T patent/ES2386061T3/es active Active
- 2009-07-30 CN CN200980131525.6A patent/CN102124470B/zh active Active
- 2009-07-30 AT AT09806408T patent/ATE545095T1/de active
- 2009-07-30 EP EP09806408A patent/EP2324442B1/fr active Active
Also Published As
Publication number | Publication date |
---|---|
KR20110083591A (ko) | 2011-07-20 |
CA2733667A1 (en) | 2010-02-18 |
EP2324442A1 (fr) | 2011-05-25 |
ATE545095T1 (de) | 2012-02-15 |
US20120124680A1 (en) | 2012-05-17 |
JP2012505563A (ja) | 2012-03-01 |
US8955160B2 (en) | 2015-02-10 |
CA2733667C (en) | 2017-11-07 |
WO2010018071A1 (fr) | 2010-02-18 |
EP2324442B1 (fr) | 2012-02-08 |
CN102124470A (zh) | 2011-07-13 |
ES2386061T3 (es) | 2012-08-08 |
KR101722790B1 (ko) | 2017-04-05 |
FR2935059B1 (fr) | 2012-05-11 |
FR2935059A1 (fr) | 2010-02-19 |
CN102124470B (zh) | 2015-04-08 |
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