ATE545095T1 - Verfahren für den nachweis von anomalien in einer durch differenzielle logik geschützten kryptografischen schaltung und schaltung zur umsetzung dieses verfahrens - Google Patents

Verfahren für den nachweis von anomalien in einer durch differenzielle logik geschützten kryptografischen schaltung und schaltung zur umsetzung dieses verfahrens

Info

Publication number
ATE545095T1
ATE545095T1 AT09806408T AT09806408T ATE545095T1 AT E545095 T1 ATE545095 T1 AT E545095T1 AT 09806408 T AT09806408 T AT 09806408T AT 09806408 T AT09806408 T AT 09806408T AT E545095 T1 ATE545095 T1 AT E545095T1
Authority
AT
Austria
Prior art keywords
cells
circuit
logic
implementing
detecting anomalies
Prior art date
Application number
AT09806408T
Other languages
English (en)
Inventor
Jean-Luc Danger
Sylvain Guilley
Florent Flament
Original Assignee
Inst Telecom Telecom Paristech
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inst Telecom Telecom Paristech filed Critical Inst Telecom Telecom Paristech
Application granted granted Critical
Publication of ATE545095T1 publication Critical patent/ATE545095T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/55—Detecting local intrusion or implementing counter-measures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/602—Providing cryptographic facilities or services

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • General Health & Medical Sciences (AREA)
  • Bioethics (AREA)
  • Health & Medical Sciences (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Logic Circuits (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Storage Device Security (AREA)
  • Hardware Redundancy (AREA)
  • Selective Calling Equipment (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
AT09806408T 2008-08-12 2009-07-30 Verfahren für den nachweis von anomalien in einer durch differenzielle logik geschützten kryptografischen schaltung und schaltung zur umsetzung dieses verfahrens ATE545095T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0855537A FR2935059B1 (fr) 2008-08-12 2008-08-12 Procede de detection d'anomalies dans un circuit de cryptographie protege par logique differentielle et circuit mettant en oeuvre un tel procede
PCT/EP2009/059886 WO2010018071A1 (fr) 2008-08-12 2009-07-30 Procede de detection d'anomalies dans un circuit de cryptographie protege par logique differentielle et circuit mettant en oeuvre un tel procede

Publications (1)

Publication Number Publication Date
ATE545095T1 true ATE545095T1 (de) 2012-02-15

Family

ID=40548652

Family Applications (1)

Application Number Title Priority Date Filing Date
AT09806408T ATE545095T1 (de) 2008-08-12 2009-07-30 Verfahren für den nachweis von anomalien in einer durch differenzielle logik geschützten kryptografischen schaltung und schaltung zur umsetzung dieses verfahrens

Country Status (10)

Country Link
US (1) US8955160B2 (de)
EP (1) EP2324442B1 (de)
JP (1) JP5891562B2 (de)
KR (1) KR101722790B1 (de)
CN (1) CN102124470B (de)
AT (1) ATE545095T1 (de)
CA (1) CA2733667C (de)
ES (1) ES2386061T3 (de)
FR (1) FR2935059B1 (de)
WO (1) WO2010018071A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2929470B1 (fr) * 2008-03-25 2010-04-30 Groupe Ecoles Telecomm Procede de protection de circuit de cryptographie programmable, et circuit protege par un tel procede
US9081929B2 (en) * 2012-01-06 2015-07-14 New York University Systems, processes and computer-accessible medium for providing logic encryption utilizing fault analysis
US10891396B2 (en) 2016-05-27 2021-01-12 Samsung Electronics Co., Ltd. Electronic circuit performing encryption/decryption operation to prevent side- channel analysis attack, and electronic device including the same
FR3091367B1 (fr) 2018-12-28 2020-12-18 St Microelectronics Rousset Protection d’un microcontrôleur
FR3091370B1 (fr) * 2018-12-28 2021-04-09 St Microelectronics Rousset Circuit de protection
CN110321737B (zh) * 2019-06-28 2020-12-11 兆讯恒达科技股份有限公司 一种数据加密标准协处理器防注入式攻击的方法
US11321457B2 (en) * 2019-09-16 2022-05-03 Nuvoton Technology Corporation Data-sampling integrity check by sampling using flip-flops with relative delay
CN112491410B (zh) * 2020-11-18 2023-11-28 杭州师范大学 一种基于预充电逻辑与掩码技术的功耗恒定性门电路单元
US11783026B2 (en) * 2021-01-05 2023-10-10 Nuvoton Technology Corporation Processor with in-band fault-injection detection

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JPH0438793A (ja) * 1990-06-04 1992-02-07 Toshiba Corp データ転送制御回路およびこれを用いたダイナミック型半導体記憶装置
US5332931A (en) * 1991-06-24 1994-07-26 Harris Corporation High speed differential comparator
GB9611994D0 (en) * 1996-06-07 1996-08-07 Systolix Ltd A field programmable processor
US5825878A (en) * 1996-09-20 1998-10-20 Vlsi Technology, Inc. Secure memory management unit for microprocessor
US7743262B2 (en) * 1997-07-15 2010-06-22 Silverbrook Research Pty Ltd Integrated circuit incorporating protection from power supply attacks
EP1050133B2 (de) * 1998-01-02 2009-05-27 Cryptography Research Inc. Leckresistentes kryptographisches verfahren und vorrichtung
US7587044B2 (en) * 1998-01-02 2009-09-08 Cryptography Research, Inc. Differential power analysis method and apparatus
US6539092B1 (en) * 1998-07-02 2003-03-25 Cryptography Research, Inc. Leak-resistant cryptographic indexed key update
DE19941682A1 (de) * 1999-09-01 2001-03-15 Infineon Technologies Ag Sicherheitsempfindliche Chipkarten
GB2365153A (en) * 2000-01-28 2002-02-13 Simon William Moore Microprocessor resistant to power analysis with an alarm state
DE10044837C1 (de) * 2000-09-11 2001-09-13 Infineon Technologies Ag Schaltungsanordnung und Verfahren zum Detektieren eines unerwünschten Angriffs auf eine integrierte Schaltung
DE602005018457D1 (de) * 2004-02-24 2010-02-04 Nxp Bv Verfahren und Einrichtung zum Schützen einer integrierten Schaltung mittels Einbrucherkennung durch Monte-Carlo-Analyse
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DE102005037357B3 (de) * 2005-08-08 2007-02-01 Infineon Technologies Ag Logikschaltung und Verfahren zum Berechnen eines maskierten Ergebnisoperanden
DE102005055158B4 (de) * 2005-11-18 2008-08-28 Infineon Technologies Ag Schaltungsanordnung mit einer Einrichtung zur Erkennung von Manipulationsversuchen und Verfahren zur Erkennung von Manipulationsversuchen bei einer Schaltungsanordnung
KR100850202B1 (ko) * 2006-03-04 2008-08-04 삼성전자주식회사 Ｅｃｃ 패스트 몽고매리 전력 래더 알고리즘을 이용하여ｄｆａ 에 대응하는 암호화 방법
JP2007323019A (ja) * 2006-06-05 2007-12-13 Sony Corp 暗号処理装置
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Also Published As

Publication number Publication date
EP2324442B1 (de) 2012-02-08
CN102124470B (zh) 2015-04-08
KR101722790B1 (ko) 2017-04-05
KR20110083591A (ko) 2011-07-20
FR2935059B1 (fr) 2012-05-11
WO2010018071A1 (fr) 2010-02-18
US20120124680A1 (en) 2012-05-17
EP2324442A1 (de) 2011-05-25
FR2935059A1 (fr) 2010-02-19
CA2733667C (en) 2017-11-07
US8955160B2 (en) 2015-02-10
CA2733667A1 (en) 2010-02-18
JP5891562B2 (ja) 2016-03-23
JP2012505563A (ja) 2012-03-01
CN102124470A (zh) 2011-07-13
ES2386061T3 (es) 2012-08-08

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