JP5876011B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine that generates a big hit state by a lottery process caused by a gaming operation, and more particularly to a gaming machine that realizes enrichment of production contents and customer services by utilizing a large number of operation means.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7-7-7, a big hit state is established, and the big winning opening is repeatedly opened to generate a gaming state advantageous to the player.

  Whether or not to generate such a game state is determined by a jackpot lottery executed on the condition that a game ball has won at the symbol start opening, and the above symbol variation operation is based on this lottery result. It has become a thing. For example, when the lottery result is in a winning state, an effect operation called reach action or the like is executed for about 20 seconds, and then the special symbols are aligned. On the other hand, a similar reach action may be executed even in the case of a lost state. In this case, the player pays close attention to the big hit state and pays close attention to the transition of the performance operation.

  Further, before the final result is finalized, a notice effect is also executed in which a character appears or the effect movable body starts to rotate, and a big hit state is invited. The effect movable body, for example, rotates at a predetermined angle in a predetermined direction at the time of an effect operation that is likely to reach a big hit state, and notifies the lottery result with a predetermined reliability (Patent Documents 1 to 3). ).

  In addition, as a kind of notice effect, there is a case where a button effect accompanied by a button operation by the player is executed, and in response to the player's effect selection by the button operation, the number of times the button is hit, the hitting speed, etc. There are cases where the production is configured to progress.

  In addition to the effect buttons, an inquiry button may be arranged. This inquiry button is typically pressed at a timing before the game starts, and the past game performance of the gaming machine is displayed. Then, the displayed game result is a powerful judgment material as to whether or not the game should be started on the gaming machine.

JP 2009-000411 A JP 2008-259920 A JP 2008-245679 A

  By the way, in the case where the above-described effect buttons and inquiry buttons are arranged on the gaming machine, there is an advantage that game contents and presentation information can be enriched as the number of these buttons increases. Similarly, if the production movable body is increased to enrich the production contents, the number of sensors such as limit switches tends to increase accordingly. There is also a demand to increase the number of monitoring sensors arranged as a security measure.

  However, in such a case, the number of wires increases in response to an increase in detection signals from the operation buttons and sensors, so that there is a problem that the device configuration including the wiring routing route becomes complicated. Therefore, as a countermeasure, it is conceivable that a plurality of detection signals are serially transmitted through a single signal line. Therefore, the device configuration and the control operation are complicated.

  The present invention has been made in view of the above-described problems, and does not complicate the device configuration even when the number of detection signals increases, and a gaming machine in which signal transmission is realized by a configuration that is extremely simplified The purpose is to provide.

In order to achieve the above object, the present invention comprises a main control means for executing a lottery process caused by a predetermined lottery process detection signal, and a sub-control means that operates based on a control command received from the main control means. If the lottery result is a winning state, it is a gaming machine that makes a transition to a gaming state advantageous to the player, and receives a plurality of control processing detection signals different from the lottery processing detection signals; and A computer circuit of a sub-control means that is connected to the peripheral terminal unit by a serial communication line and executes a control operation corresponding to the detection signal for control processing received via the peripheral terminal unit, peripheral terminal unit receives the operation start signal from the output port of the computer circuit, while retaining acquires the control processing detection signals as parallel data, the output of the computer circuit Upon receiving the clock signal from the over preparative, the control processing detection signal held at the time, is configured to have a signal conversion circuit for outputting as the serial data to the computer circuit in synchronism with the clock signal, the computer The circuit has a first means for outputting an operation start signal to the signal conversion circuit every predetermined time, and starts operation after the first means outputs the operation start signal to convert a predetermined number of clock signals. Second means for outputting to the circuit, and third means for acquiring serial data output from the signal conversion circuit in synchronization with the clock signal output by itself corresponding to the clock signal output from the second means. and, as a detection signal for the control process, the signal changes in response to the manual operation, a signal which varies in response to the occurrence of abnormality, or varying in response to progression of the effect control operation All or part of the signal is included.

  In the peripheral terminal of the present invention, it is sufficient to arrange a signal conversion circuit. Since this signal conversion circuit does not require an oscillation circuit for a clock pulse or the like, the circuit configuration can be simplified extremely.

  The signal conversion circuit of the present invention has (1) a function for acquiring and holding a control processing detection signal when receiving an operation start signal, and (2) a control processing detection signal held at that time when receiving a clock signal. Is typically realized by a shift register, since it suffices to exhibit a function of outputting one bit at a time to the control unit in synchronization with the clock signal. In this case, the operation start signal is a latch pulse, and if a shift register having the same configuration is connected in series, the signal transmission line can be used for a latch pulse and for a clock signal no matter how many detection signals for control processing increase. A total of three control signal detection signals are sufficient.

  Further, the signal conversion circuit of the present invention outputs one bit at a time to the control unit in synchronization with the clock signal, and the third means obtains serial data bit by bit in synchronization with the clock signal. And stop bits can be omitted, and rapid serial communication can be realized.

  Specifically, the second means outputs the same number N of clock signals as a plurality of control processing detection signals to finish the processing, and the third means detects N bits of serial data for N control processing detections. If it is acquired as a signal, a so-called start bit, stop bit, or parity bit can be omitted.

  The present invention is preferably used for subsequent control operations on condition that the N control processing detection signals acquired by the third means are all at the same level over a plurality of acquisitions.

  Here, the level of the detection signal for control processing changes in response to manual operation, changes in response to the occurrence of an abnormal situation, or automatically changes in response to the progress of the production control operation. Is preferred. In relation to this configuration, when the control unit of the present invention recognizes a level change of the detection signal for control processing, it is preferable to start a game operation, a notification operation, or an alarm operation in response thereto.

  Further, it is preferable that the clock signal has a first edge and a second edge, and the signal conversion circuit outputs the control processing detection signal in synchronization with the first edge of the clock signal. In this case, the clock signal has a first edge and a second edge, and the control unit acquires the detection signal for control processing output from the signal conversion circuit in synchronization with the second edge of the clock signal. Is preferred. Note that the gaming machine of the present invention is typically a bullet ball game machine or a revolving game machine.

  According to the present invention described above, smooth and normal signal transmission can be realized without complicating the device configuration even if the number of detection signals increases and without affecting other processing.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a block diagram which shows circuit structures, such as an effect control part. It is a circuit diagram explaining the structure of a switch signal transmission board | substrate. It is a flowchart explaining operation | movement of an effect control part. It is a flowchart explaining a switch signal input process. It is a flowchart explaining the modification of a switch signal input process. It is the circuit block diagram and flowchart explaining the modification of switch signal input processing. It is a circuit block diagram and flowchart explaining another modification of switch signal input processing. It is a flowchart explaining a part of FIG. 10 in detail.

  Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side, not from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. On the other hand, a speaker is disposed below the glass door 6.

  The front plate 7 is provided with an upper plate 8 for storing game balls for launching, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and a launch handle at the lower part of the front frame 3. 10 are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  On the left side of the outer peripheral surface of the upper plate 8, two effect buttons 11a and 11b are provided. These effect buttons 11a and 11b are provided at positions that can be operated with the left hand of the player, and the player can operate without releasing the right hand from the launch handle 10. The left and right effect buttons 11a and 11b function as selection decision buttons for game contents and game progression, for example. Further, when the game state becomes the button chance state, for example, it is possible to exert an advantageous influence on the game progress by repeatedly hitting one of the effect buttons 11a and 11b at a high speed.

  A cross key 4 is disposed on the right side of the outer peripheral surface of the upper plate 8. The cross key 4 is an inquiry button that is operated when it is desired to know the gaming performance of the gaming machine. The cross key 4 is provided with four selection buttons S1 to S4 on the top, bottom, left and right, and a center determination button S0.

  For example, when the center determination button S0 is pressed prior to the start of the game, such as during a demonstration screen, a menu screen for displaying results is displayed on the display device DISP. Thereafter, when a necessary selection item on the menu screen is selected by any one of the selection buttons S1 to S4 and the determination button S0 is pressed, the game results of the selected item are displayed. The game results include the number of fluctuating effects, the number of jackpots, etc. up to the current day or the previous day.

  In addition, an operation panel 12 for ball lending operation for the card-type ball lending machine is provided on the right part of the upper plate 8, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a game ball for a predetermined amount A ball lending switch for instructing the lending of the player and a return switch for instructing the return of the card at the end of the game are provided.

  As shown in FIG. 2, a guide rail 13 made of a metal outer rail and an inner rail is provided in an annular shape on the surface of the game board 5, and a central opening HO extending toward the back side is provided in the approximate center. It has been. A display device DISP composed of a liquid crystal color display is arranged at the bottom of the central opening HO.

  An effect movable body AMU that is rotated by a rotary motor RO is disposed in a space formed in front of the display device DISP so as to be movable up and down. The effect movable body AMU is configured to be held by the left and right movable bodies MV1, MV2 that move up and down integrally. In the normal state, the effect movable body AMU is lifted by the movable bodies MV1 and MV2 and stands by at the origin position.

  A symbol starting port 15, a big winning port 16, a normal winning port 17, and a gate 18 are arranged at appropriate positions in the game area 5a. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  The display device DISP is a device that variably displays a specific symbol related to the big hit state and displays a background image and various characters in an animated manner. This display device DISP has a special symbol display part Da to Dc in the center and a normal symbol display part 19 in the upper right part. And, in the special symbol display parts Da to Dc, a reach effect is executed that expects a big hit state to be invited, or in the special symbol display parts Da to Dc and the surroundings, a notice effect that informs the result of the success / failure is executed. Is done.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time, and the lottery extracted at the time when the game ball passes through the gate 18 is extracted. The stop symbol determined by the random number for use is displayed and stopped.

  The symbol start opening 15 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws. It is opened only for a predetermined time or until a predetermined number of game balls are detected.

  When a game ball wins the symbol start port 15, the display symbols of the special symbol display portions Da to Dc change for a predetermined time and are determined based on the lottery result corresponding to the winning timing of the game ball to the symbol start port 15. Stop at the stop symbol. In addition, in special symbol display parts Da-Dc and its circumference, a notice effect may be performed between a series of symbol effects. In addition, as a kind of notice effect, the effect movable body AMU may descend to the position of the central opening HO. Then, the lowered effect movable body AMU is driven by the rotary motor RO and rotates clockwise or counterclockwise, and then rises to the original position.

  The big winning opening 16 is controlled to open and close by, for example, an opening / closing plate 16a that can be opened forward. When the stop symbol after the symbol change in the special symbol display portions Da to Dc is a big hit symbol such as “777”, Is started, and the opening / closing plate 16a is opened.

  After the opening / closing plate 16a of the big prize opening 16 is opened, the opening / closing plate 16a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. In such an operation, the special game is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol among the special symbols, there is a privilege that the game after the end of the special game becomes a high probability state (probability variation state). Is granted.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations. A dashed line in the figure mainly indicates a DC voltage line.

  As shown in the figure, this pachinko machine GM mainly receives a 24V AC and outputs various DC voltages, power supply abnormality signals ABN1, ABN2, a system reset signal (power reset signal) SYS, and the like, and a game control operation. Based on the main control board 21 that performs overall control, the effect control board 22 that executes the lamp effect and the sound effect based on the control command CMD received from the main control board 21, and the control command CMD ′ received from the effect control board 22 The image control board 23 for driving the display device DISP, the payout control board 24 for controlling the payout motor M based on the control command CMD "received from the main control board 21, and paying out the game balls. It is mainly composed of a launch control board 25 that responds and launches a game ball.

  However, in this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the command relay board 26 and the effect interface board 27. Further, the control command CMD ′ output from the effect control board 22 is transmitted to the image control board 23 via the effect interface board 27, and the control command CMD ″ output from the main control board 21 is the main board relay board. It is transmitted to the payout control board 24 via 28.

  The main control board 21, the effect control board 22, the image control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer. Thus, the circuits mounted on the control boards 21 to 24 and the operations realized by the circuits are collectively referred to as a function. In this specification, the main control unit 21, the effect control unit 22, and the image control unit 23 are used. , And the payout control unit 24. All or part of the effect control unit 22, the image control unit 23, and the payout control unit 24 is a sub-control unit.

  By the way, the pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 1 is the panel side member GM2.

  3, the frame-side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, a frame relay board 32, and a switch signal transmission board 33. These circuit boards are respectively fixed at appropriate positions of the front frame 3. The switch signal transmission board 33 individually receives each switch signal from the effect button 11 and the cross key 4, converts them into a serial switch signal Sin, and outputs them to the effect control board 22. ing. As shown in the figure, the serial switch signal Sin is transmitted through the path of the switch signal transmission board 33 → the frame relay board 32 → the frame relay board 31 → the production interface board 27 → the production control board 22, but the production control board 22 outputs the serial switch signal Sin. The clock signal CK and the latch signal LT to be transmitted are transmitted to the switch signal transmission board 33 through a reverse path (see FIG. 4).

  On the other hand, on the back of the game board 5, a main control board 21, an effect control board 22, an image control board 23, and an effect interface board 27 are fixed together with the display device DISP and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place.

  The effect interface board 27 is connected to a motor connection board 34 for driving the drive motors M1, M2 and the rotary motor RO and a lamp connection board 35 for driving the LED group. Here, the effect interface board 27 receives signals transmitted / received to / from each effect member in various effect operations such as a lamp effect, a sound effect, a movable effect, and a button effect executed by the control of the effect control board 22. Plays the relay function.

  The power supply board 20 is connected to the main board relay board 28 through the connection connector C2, and is connected to the power supply relay board 30 through the connection connector C3. The power supply board 20 is provided with a power supply monitoring unit MNT that monitors whether AC power is turned on or off. When power supply monitoring unit MNT detects that AC power is turned on, it maintains system reset signal SYS at L level for a predetermined time, and then transitions it to H level.

  Further, when power supply monitoring unit MNT detects the interruption of the AC power supply, power supply abnormality signals ABN1 and ABN2 are immediately shifted to the L level. The power supply abnormality signals ABN1 and ABN2 quickly become H level after the power is turned on.

  Incidentally, the system reset signal of this embodiment is generated by a DC power supply based on an AC power supply. For this reason, after detecting the turning-on of the AC power supply (usually turning on the power switch) and increasing it to the H level, the H level is maintained unless the DC power supply voltage drops to an abnormal level. Therefore, even if the AC power supply is in an instantaneous power interruption state while the DC power supply voltage is maintained, the system reset signal SYS does not reset the CPU. The power supply abnormality signals ABN1 and ABN2 are also output even when the AC power supply is instantaneously stopped.

  The main board relay board 28 outputs the power abnormality signal ABN1, the backup power supply BAK, and DC5V, DC12V, and DC32V output from the power board 20 to the main control unit 21 as they are. On the other hand, the power relay board 30 outputs the system reset signal SYS received from the power board 20 and the AC and DC power supply voltages to the effect interface board 27 as they are. The production interface board 27 outputs the received system reset signal SYS to the production control unit 22 and the image control unit 23 as they are.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and directly receives the same power abnormality signal ABN2 and backup power supply BAK as the main control unit 21 receives together with other power supply voltages. Is receiving.

  The system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V has been turned on to the power supply board 20, and the one-chip microcomputer of the effect control unit 22 and the image control unit 23 by this power supply reset signal. The power is reset together with other IC elements.

  However, the system reset signal SYS is not supplied to the main control unit 21 and the payout control unit 24, and a power reset signal (CPU reset signal) is generated in the reset circuit RST of each of the circuit boards 21 and 24. ing. Therefore, for example, even if the connection connector C2 is rattled or noise is superimposed on the wiring cable, there is no possibility that the CPU of the main control unit 21 or the payout control unit 24 is abnormally reset. The effect control unit 22 and the image control unit 23 execute the effect operation in a dependent manner based on the control command from the main control unit 21, so that the power supply board 20 is avoided in order to avoid complication of the circuit configuration. The system reset signal SYS output from is used.

  By the way, the reset circuits RST provided in the main control unit 21 and the payout control unit 24 each have a built-in watchdog timer, and unless a regular clear pulse is received from the CPUs of the control units 21 and 24, Each CPU is forcibly reset.

  In this embodiment, the RAM clear signal CLR is generated by the main control unit 21 and transmitted to the one-chip microcomputer of the main control unit 21 and the payout control unit 24. Here, the RAM clear signal CLR is a signal for deciding whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. The initialization switch SW operated by the attendant is turned on. It has a value corresponding to the / OFF state.

  The main control unit 21 and the payout control unit 24 receive the power supply abnormality signals ABN1 and ABN2 from the power supply board 20 to start necessary end processing prior to a power failure or business end. The backup power supply BAK is a DC5V DC power source that retains data in the RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 24 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  As shown in FIG. 3, the main control unit 21 transmits a control command CMD ″ to the payout control unit 24 via the main board relay board 28, while the payout control unit 24 indicates a game ball payout operation. A prize ball counting signal, a status signal CON relating to an abnormality in the payout operation, and an operation start signal BGN are received, and the status signal CON includes, for example, a replenishment signal, a payout shortage error signal, and a lower plate full signal. The operation start signal BGN is a signal for notifying the main control unit 21 that the initial operation of the payout control unit 24 has been completed after the power is turned on.

  The main control unit 21 is connected to each game component of the game board 5 via the game board relay board 29. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The solenoids and the detection switch are configured to operate with a power supply voltage VB (12 V) supplied from the main control unit 21. Each switch signal indicating a winning state to the symbol starting port 15 is converted to a TTL level switch signal by an interface IC that operates with the power supply voltage VB (12 V) and the power supply voltage Vcc (5 V). Then, the data is transmitted to the main control unit 21.

  As shown in FIG. 4, the effect control unit 22 includes a one-chip microcomputer 40 that executes processing such as voice effect, lamp effect, button effect, notice effect by effect movable body, and data transfer, and a control program for the one-chip microcomputer 40. And the like, an audio reproduction output circuit 42 that reproduces and outputs an audio signal based on an instruction from the one-chip microcomputer 40, and an audio for storing compressed audio data that is the original data of the reproduced audio signal A memory 43 and a watchdog timer WDT are provided.

  The one-chip microcomputer 40 includes a parallel input / output port PIO and a serial input / output port SIO. From the parallel port PIO, motor control data for controlling the rotation of the elevating motors MO1, MO2 and the rotary motor RO is output to the motor control board 34 along with the control command CMD ′ and the strobe signal STB ′ in time sequence. Yes. An origin switch is provided in association with each of the lift motors MO1 and MO2, and the switch signal is input to the parallel port PIO. The origin switch ORG is used for collecting the effect movable body AMU in the origin area and accurately stopping at the origin position.

  The serial port SIO has a plurality of channels that can operate independently. In this embodiment, a part of the serial port SIO is used to connect the switch signal transmission board 33 and the lamp connection board 35 to each other. Realizes synchronous serial communication.

  As illustrated, the serial port SIO outputs a serial lighting signal Sout to the lamp connection board 35 in synchronization with the clock signal CK. A plurality of shift registers are mounted in series on the lamp connection board 35, and the serial lighting signal Sout output from the serial port SIO is received in time sequence in synchronization with the clock signal CK. Then, in synchronization with the latch signal LT ′ output from the parallel port PIO of the one-chip microcomputer 40, the serial lighting signal acquired by each shift register is output to the LED lamp as a parallel lighting signal.

  The serial port SIO supplies the clock signal CK to the switch signal transmission board 33 and receives the serial switch signal Sin from the switch signal transmission board 33. The serial switch signal Sin corresponds to a switch signal received from the cross key 4 or the effect buttons 11a and 11b.

  The switch signal transmission board 33 outputs a serial switch signal Sin in synchronization with the clock signal CK received from the serial port SIO. The serial port SIO outputs the serial switch signal Sin in synchronization with the clock signal CK. Obtained sequentially and stored as parallel data.

  The watchdog timer WDT is reset by a clear pulse periodically supplied from the one-chip microcomputer 40. When the clear pulse is interrupted due to a program runaway or the like, a reset signal RESET is output. As a result, the one-chip microcomputer 40 is forcibly reset to the initial state, and the program runaway state is solved.

  As shown in FIG. 4, the control command CMD and the strobe signal (interrupt signal) STB output from the main control board 21 are sent to the one-chip microcomputer 40 of the effect control board 22 via the buffer 48 of the effect interface board 27. Is supplied. The interrupt signal STB is supplied to the interrupt terminal INT of the one-chip microcomputer. Then, the effect control unit 22 acquires the control command CMD by the reception interrupt process activated by the strobe signal STB.

  The control command CMD acquired by the effect control unit 22 includes (1) an abnormality notification and other notification control commands, and (2) a control for specifying an outline of various effect operations resulting from winning at the symbol start opening. Commands (variation pattern commands) are included. Here, the outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end, and the result of winning or failing in the big hit lottery. In addition to these, the change pattern command including the presence or absence of the reach effect or the notice effect may be specified, but even in this case, the specific content of the effect content is not specified.

  Therefore, when the effect control unit 22 acquires the variation pattern command CMD, the effect lottery is subsequently performed, and the effect outline specified by the acquired variation pattern command is further specified.

  For example, the specific contents of the reach effect and the notice effect are determined. Then, in accordance with the determined specific game content, a lamp effect by blinking the LED group and a sound effect preparation operation by the speaker are performed, and the image control unit 23 is synchronized with the effect operation by the lamp and the speaker. The control command CMD ′ related to the rendered symbol effect is output. Further, during the advance notice operation using the effect movable body AMU, the lift motors MO1 and MO2 are synchronously rotated to lower the effect movable body AMU, and then the rotary motor RO is operated to perform the effect operation of the effect movable object AMU. The

  In order to realize such a symbol effect synchronized with the effect operation, the effect control unit 22 outputs a control command CMD ′ to the effect interface board 27 together with a strobe signal (interrupt signal) STB ′ for the image control unit 23. To do. When the production control unit 22 receives a notification control command related to the display device or another control command for error processing, the production control unit 22 directly sends the control command to the production interface board 27 together with the interrupt signal STB ′. Output toward.

  Corresponding to the configuration of the effect control board 22, the effect interface board 27 is configured to receive an 8-bit control command CMD 'and a 1-bit interrupt signal STB'. These data CMD ′ and STB ′ are output to the image control board 23 via the buffer circuit 46 as they are. The effect interface board 27 receives the serial lighting signal Sout for driving the lamp output from the effect control unit 22 and supplies it to the LED lamp group via the lamp connection board 34. As a result, a lamp effect corresponding to the control command CMD output from the main control unit 21 is realized.

  On the other hand, at the time of button production during the game operation or at the demonstration screen production before the start of the game operation, the production interface board 27 is a serial switch indicating the ON / OFF state of the production button 11 and the cross key 4 from the switch signal transmission board 33. The signal Sin is received and transmitted to the serial port SIO of the effect control unit 22.

  The image control unit 23 receives a control command via the effect interface board 27 and executes an image control operation, a VDP that drives the display device DISP based on an instruction from the one-chip microcomputer, and a graphic ROM And a control ROM and a watchdog timer WDT for forcibly resetting the one-chip microcomputer.

  The system reset signal SYS is supplied via the effect interface board 27 to the reset terminal RESET of the built-in CPU of the one-chip microcomputer of the effect control unit 22 and the image control unit 23. Each CPU is reset.

  Next, the circuit configuration of the switch signal transmission board 33 will be described with reference to FIG. As shown in FIG. 5A, the switch signal transmission board 33 is configured around a shift register 50, an input buffer circuit 51, and a filter circuit 52. The input buffer circuit 51 includes a pull-up resistor R and an inverter IN, and logically inverts a switch signal received from the cross key 4 or the effect button 11. In this embodiment, since the two effect buttons 11a and 11b and the five-point cross key 4 are used, a switch signal having a total length of 7 bits is sent to the shift register 50 via the input buffer circuit 51. It is supplied to seven input terminals (B to H). The input terminal (A) of the least significant bit is connected to the ground.

  The filter circuit 52 constitutes a CR low-pass filter composed of resistors R1 and R2 of about 50 to 100Ω and capacitors C1 and C2 of about 50 to 100 pF. As described above, in this embodiment, the time constant of the filter circuit 52 is designed to be 2.5 to 10 × 10 −9 [S], and overshoot and undershoot are prevented even at a communication speed of about 2 Mbps to 8 Mbps. Suppressing and realizing serial communication without malfunction can be realized.

  However, in this embodiment, the communication speed is set to 100,000 bps corresponding to the serial bit length of the serial switch signal Sin being 8 bits. Even if this communication speed is set, the communication time required for one communication is about 80 μS, and even if this communication process is repeatedly executed every 2 mS, other processes are not adversely affected. When the serial bit length increases, it is preferable to increase the communication speed correspondingly. However, even when the communication speed is increased to about 8 Mbps, the filter circuit 52 prevents the malfunction. .

  As the shift register 50, for example, TC74VHC165F (Toshiba) whose internal circuit is shown in FIG. 5B is used. The parallel input terminals B to H of the shift register 50 are supplied with switch signals indicating the ON / OFF states of the two contacts of the effect buttons 11 a and 11 b and the five contacts of the cross key 4. On the other hand, the parallel input terminal A is fixed to the ground level. The data of these parallel input terminals A to H are acquired by the internal register in synchronization with the falling timing of the latch signal LT.

  As shown in the figure, in this embodiment, the serial input terminal INPUT and the prohibition terminal INHIBIT of the shift register 50 are fixed at the L level. Therefore, when the clock signal CK is supplied, the data acquired in the shift register 50 is output as serial data QH (serial switch signal Sin) in synchronization with the rising edge of the clock signal CK. The output serial switch signal Sin is transmitted from the switch signal transmission board 33 to the effect control board 22 and supplied to the serial port SIO. The serial port SIO is configured to sequentially acquire the serial switch signal Sin in synchronization with the falling edge of the clock signal CK output by itself. It should be noted that the substantially acquired data is 7 bits long, and specifies the ON / OFF states of the two contacts of the effect buttons 11a and 11b and the five contacts of the cross key 4.

  Next, the operation of the effect control unit 22 will be described. As shown in FIG. 6, the effect control unit 22 includes a main process (a) that is started when the CPU is reset, a reception interrupt process (b) that is activated by the strobe signal STB, and a first process that is activated every 10 mS. The timer interrupt process (c) and the second timer interrupt process (d) activated every 2 mS are included.

  As shown in FIGS. 6B and 6C, at the time of a reception interrupt, unless a communication abnormality is recognized (ST30), a reception command is stored in the buffer area (ST31), and if there is a first timer interrupt, The interrupt flag is set to ON (ST35).

  In addition, as shown in FIG. 6D, in the second timer interruption process, a lamp effect process (ST40) for driving the illumination lamp, and an effect motor process (ST41) for driving the effect movable body AMU as necessary. The switch signal input process (ST42) for acquiring the serial switch signal Sin from the switch signal transmission board 33 is executed every 2 mS.

  On the other hand, in the main process (CPU reset process) shown in FIG. 6A, first, the initial setting in the one-chip microcomputer 40 is executed (ST10). This initial setting includes internal setting processing of the serial port SIO, and the frequency of the clock signal CK supplied from the output terminal of the serial port SIO to the shift register 50 of the switch signal transmission board 33 is set to a desired baud rate. Correspondingly, for example, it is set to 100 kHz.

  The serial port SIO connected to the switch signal transmission board 33 is set to the serial reception mode by clock synchronization, and the serial switch signal Sin transmitted to the input terminal of the serial port SIO is at the falling edge of the clock signal CK. Set to be acquired synchronously. The acquired data is stored in order in the reception buffer of the serial port SIO for each byte, and the reception completion flag is set when acquisition of data of the specified bit length is completed. In this embodiment, the specified bit length is set to 8 bits, but the specified bit length is divided into 2 bits for the effect button, 5 bits for the cross key, and 1 bit for the dummy.

  When the initial setting as described above is completed, a backup determination process is executed (ST11). The backup determination process is a process for determining the validity of the data stored in the backup process (ST26). Data stored in the backup process (ST26) is not particularly limited. For example, (1) a checksum operation sum value for predetermined data in the RAM area, (2) specific data discretely stored in the RAM area, (3) Backup data in which predetermined data in the RAM area is stored in another area can be exemplified.

  In the backup determination process, it is also determined whether an important operation flag indicating the operation state is irrational. The irrationality in the operation flag is, for example, a case where both the operation flag indicating that the variation effect is being performed and the operation flag indicating that the jackpot operation is being set. In this gaming machine, after the variation effect is finished, the game shifts to a big hit operation, so the two operation flags cannot be set at the same time. If such a situation is detected, other saved data is stored. Even if legitimacy is recognized, it judges that it is not normal.

  Even in such a case, when the validity cannot be confirmed in the determinations of steps ST11 to ST12, the entire area of the RAM is initialized, the production control unit 22 is cold-started, and the process proceeds to step ST16. (ST13).

  By the way, unlike the main control unit 21 and the payout control unit 24, the production control unit 22 is not provided with a backup power source, and therefore it may not be possible to detect legitimate data in the backup determination process (ST11). However, the CPU is reset not only at the time of power reset corresponding to power-on, but also at the time of abnormal reset when the CPU reset signal becomes an active level due to noise or a watchdog timer.

  Therefore, in this embodiment, a backup determination process (ST11 to ST12) is provided in order to continue the game operation up to that point and to hot start the operation of the effect control unit 22 as much as possible when the CPU is reset abnormally. Yes.

  However, since not all data is determined in the backup determination process (ST11), the operation of the effect control unit 22 should be returned to the initial state when the CPU is repeatedly abnormally reset. Accordingly, the abnormality counter is incremented (+1) to count the number of abnormal resets (ST14), and if the value of the abnormality counter exceeds a predetermined value (for example, 2), the RAM clear process in step ST13 is performed to cold start. (ST15).

  As described above, even when the CPU is abnormally reset, if the backup determination (ST11) makes a correct determination and the number of abnormal resets is equal to or less than a predetermined value, the effect control unit 22 is hot-started and the game up to that point Operation continues.

  When the initial operation as described above is completed, necessary initial settings are then performed for the audio reproduction output circuit (audio reproduction IC) 42 (ST16). Thereafter, the CPU of the one-chip microcomputer 40 is set to the interrupt permitting state (ST17), then the random number value is updated (ST18), and a timer interrupt at 10 mS intervals is waited (ST19). Note that the updated random value is used in the effect lottery process in order to randomize the effect operation.

  As shown in FIG. 6C, an interrupt flag is set every time a timer interrupt occurs at an interval of 10 mS (ST35). Therefore, in the process of step ST19 of the main process, it is repeatedly checked that the interrupt flag is turned ON. . When the interrupt flag is turned on, the timer update process is executed after resetting the interrupt flag to off (ST20). In the timer update process, the value of a clock timer that manages the progress of the production scenario is updated.

  Subsequently, command analysis processing is executed for the control command (reception command) received in the reception interrupt processing (FIG. 6B) (ST21). The received command includes not only the variation pattern command but also an abnormality notification or other notification control command. When a control command for notification is received, the control command is transferred to the downstream image control unit 23 and a necessary notification operation is executed.

  In addition, when the variation pattern command is received, the effect lottery is performed, the effect outline specified by the acquired variation pattern command is further specified, and the effect command CMD ′ for specifying the specified effect content is transmitted to the image control unit. (ST21). Further, a flag setting process of an effect flag necessary for starting the effect operation specified by the effect command is executed (ST21).

  Next, after executing error processing (ST22), switch signal management processing is executed (ST23). The switch signal management process (ST23) is a process for advancing the rendering operation and the notification operation in response to the ON operation of the rendering buttons 11a and 11b and the cross key 4. As described above, the ON operation of the effect buttons 11a and 11b and the cross key 4 is checked every 2 mS by the switch signal input process (ST42).

  Therefore, when the operation of the cross key 4 is permitted, the control command CMD ′ indicating the contact position (S0 to S4) of the cross key 4 is transmitted to the image control unit 23, and the image control unit 23 receiving this transmits the control command CMD ′. The game result designated by the player is displayed on the display device DISP. On the other hand, when the operation of the effect buttons 11a and 11b is permitted, an effect flag corresponding to the operation is set.

  Next, an effect scenario for the lamp effect (ST40), the effect motor process (ST41), and the sound effect (ST25) is created or updated while referring to the value of the effect flag and the timing timer (ST24). Next, an audio effect based on the created or updated effect scenario is executed (ST25).

  When the sound effect (ST25) is finished, the process proceeds to step ST17 after the backup process (ST26) is executed. Examples of the backup processing include not only checksum calculation but also processing for storing specific data discretely, processing for storing all data in the work area, and the like.

  Next, the switch signal input process (ST42) executed every 2 mS will be described with reference to FIG.

  As shown in FIG. 7, in the switch signal input process, first, the latch signal LT is output from the parallel port (ST50). Specifically, as shown in FIG. 5C, the latch signal LT that is constantly at the H level is lowered to the L level for a predetermined time. As shown in FIGS. 4 and 5, the latch signal LT whose level has dropped is transmitted to the switch signal transmission board 33 and supplied to the LOAD terminal of the shift register 50.

  Then, the shift register 50 acquires the data of the parallel input terminals A to H in the internal register in synchronization with the falling edge of the latch signal LT. Since this acquisition operation is repeatedly executed every 2 mS, the acquisition data is always at the L level unless the player operates any button, and in this sense, the acquisition process seems to be useless.

  However, by adopting the configuration of the present embodiment, it is possible to reliably grasp the ON operation without reading over even an inquiry button that cannot be predicted when it is pressed, such as the cross key 4. In addition, since the switch signal is checked every 2 mS, it is possible to reliably grasp the ON / OFF state regardless of how fast the effect button 11 is operated, and to measure the player's button operation speed, etc. You can also.

  As shown in FIG. 5C, the CPU returns the latch signal whose level has been lowered to the H level, and then starts outputting the clock signal CK from the output terminal of the serial port SIO (ST51). As described above, the clock signal CK is transmitted to the switch signal transmission board 33 as a shift clock of the shift register 50.

  The shift register 50 that has received the clock signal CK outputs the decision button signal S0 (H input terminal) of the cross key 4 at the rise of the first clock signal CK, and at the rise of the second clock signal, The selection button signal S1 (G input terminal) of the cross key 4 is output, and thereafter the same operation is repeated to generate the serial switch signal Sin (see FIG. 5B).

  The serial switch signal Sin output from the shift register 50 in this way is supplied to the input terminal of the serial port SIO. As described above, in this embodiment, the serial switch signal Sin is initially set to be acquired for each bit in synchronization with the falling edge of the clock signal CK (ST10). In addition, every time 1 byte of data is acquired, 1 byte data is stored in the serial buffer SIO reception buffer in sequence, and reception is completed when data of the specified bit length (8 bits in this embodiment) has been acquired. Initial setting is made so that the register is set (ST10).

  Since the serial port SIO is initialized as described above, when eight clock signals CK are output, the reception process of the serial switch signal Sin is completed, and 1-byte data is stored in the reception buffer and received. A completion flag will be set. Therefore, the CPU that has finished the process of step ST51 waits for the reception process in the serial port SIO to be completed by checking the repeated reception completion flag (ST52).

  When it is confirmed that the reception completion flag is set, the CPU stops outputting the clock signal CK and checks the error detection register of the serial port SIO to confirm that no communication error has occurred (ST54). . If a communication error is recognized, the error bit and the reception buffer are cleared and the process ends (ST55). As a result, the acquired data this time is ignored.

  As will be described below, the serial switch signal Sin of this embodiment is not provided with a start bit, a stop bit, or a parity bit, so that a framing or parity error does not become a problem. At best, there are only overrun errors. However, in this embodiment, since the specified bit length is 8 bits, an overrun error does not occur in practice, and therefore the processing of steps ST54 to ST55 can be eliminated.

  In any case, in this embodiment, the clock signal CK is not constantly output from the serial port SIO, but the output of the clock signal CK is started when necessary (ST51). The data to be processed can always be divided by the decision key signal S0 of the cross key 4, and in this sense, the start bit is not necessary.

  In this embodiment, since the processing is completed by outputting a clock signal having a specified bit length (ST53), it is not necessary to add a stop bit to the serial switch signal Sin. Furthermore, since no parity bit is used in this embodiment, the switch signal can be acquired with the minimum necessary communication time excluding the start bit, stop bit, and parity bit, and can be repeatedly executed every 2 ms. There is no risk of taking the processing time of other effects processing.

  Similarly, according to the configuration of this embodiment, a circuit configuration for adding a start bit, a stop bit, a parity bit, and the like is not necessary, and the serial port SIO is intermittently operated. Not only is there no waste, but even if the frequency of the clock signal is increased, there is no possibility of becoming a steady noise source for other circuit elements.

  As described above, in this embodiment, there is no problem other than an overrun error, but it cannot be said that bit corruption due to electromagnetic noise does not occur in a high noise environment. Therefore, in consideration of this point, on the condition that the same data is repeatedly received a plurality of times (M), a button effect and a game performance display operation are started based on the acquired data. The number M of continuous acquisitions is set as appropriate. For example, when M = 10, all switch signals having an 8-bit length (substantially 7-bit length) have the same value for 2 mS × 10 = 20 mS. Is a condition for acquiring the switch signal.

  As a result, the transition timing of each switch signal cannot be accurately grasped, and as shown by the broken line in FIG. 7B, when M = 10, grasping of the transition timing is delayed by about 20 mS to 40 mS. become. However, since the switch signal which is a problem in this embodiment is a signal corresponding to the manual operation of the player, the detection delay of about 40 mS has substantially no problem. Conversely, electromagnetic noise and the like usually converge within 20 mS, so that the influence of noise can be eliminated without providing a parity bit or the like.

  Based on the above, the processing of steps ST56 to ST63 will be described. In this embodiment, M data buffers are provided corresponding to the number of consecutive acquisitions M, and 1-byte data acquired every 2 mS is stored at the address indicated by the pointer PT unless a communication error is detected. It is configured to be.

  That is, when no communication abnormality is recognized in the 1-byte data acquired this time, the pointer PT is updated (ST56), the 1-byte data is stored in the data buffer area indicated by the pointer PT, and then the serial port. The SIO reception buffer is cleared (ST57). Next, it is determined whether or not the pointer PT matches the final address MAX (ST58). If they match, the pointer is rewritten to the start address START (ST59).

  Subsequently, it is determined whether or not all the M pieces of stored data match (ST60). If there is even one piece of data that does not match, the processing is finished as it is. Therefore, although it cannot respond quickly at the time of transition of the switch signal, the delay time of about 2 mS × M × 2 at the maximum is not harmful, and conversely, it is effective for noise elimination as described above.

  On the other hand, if all of the M stored data match, it is determined whether or not the data matches the past data OLD (ST61). The past data is stored at the OLD address and means the data acquired most recently (only 2 mS × M before).

  Here, the case where the data stored in the data buffer matches the past data OLD is when the switch signal transitioned in response to the ON operation is stable, and when the effect button 11 or the cross key 4 is not ON. You could think so. However, in either case, the current data does not need to be a problem, so the processing is finished as it is.

  On the other hand, if the data stored in the data buffer does not match the past data OLD, it is considered that the level of any switch signal has changed. Accordingly, the current acquired data (data stored in the data buffer) is stored in the LVL address as a switch level signal, and the bit transitioned from the past data is specified and stored in the EDG address as a switch edge signal (ST62).

  The bits that have transitioned from the past data are specified by, for example, an XOR logic operation of all the bit inverted data of the past data and the current acquired data. In this case, a bit that becomes 0 after the XOR logic operation means a transition bit. Then, whether the transition from 0 to 1 or 1 to 0 can be specified by the current acquired data (switch level signal).

  When the switch level signal and the switch edge signal are stored in the LVL address and the EDG address in this way, the current acquired data is stored in the OLD address and the switch signal input process is finished (ST63). As described above, the data of the LVL address and the EDG address are read out in the switch signal management process (ST23) and reflected in the display operation of the button effect and the game performance.

  Although the embodiments have been described in detail above, the specific description does not particularly limit the present invention. In particular, the serial switch signal transmitted from the switch signal transmission board does not need to be 8 bits long, and may be longer than that. In this case, shift registers 50 as shown in FIG. 5B are connected in series, and the clock signal CK is transmitted through all the shift registers 50.

  Similarly, the specified bit length set in the serial port SIO is not necessarily 8 bits, and may be set to 7 bits or 9 bits or more corresponding to the number of switch signals. Of course, the number M of areas of the data buffer is appropriately increased or decreased according to noise characteristics and the like.

  In the embodiment, the switch signal such as the origin switch of the lifting motor is transmitted to the parallel port. However, the switch signal such as the limit switch of the effect movable body that moves at a relatively low speed is transmitted in the form of a serial switch signal. May be. In this case, the circuit configuration formed on the switch signal transmission board 33 may be provided on the motor connection board 34. For sensors arranged for crime prevention, it is not necessary to detect the level transition of the switch signal so quickly. It is preferable to transmit in the form of a serial switch signal. In such a case, the device configuration does not become complicated even if the number of sensors or the number of switches increases.

  Further, the serial data acquisition method is not limited to the configuration shown in FIG. That is, in the configuration of FIG. 7, all data coincidence determination is executed every 20 mS (2 mS × M) (ST60), but it is also preferable to perform all data coincidence determination every 2 mS as shown in FIG. (See ST58 to ST59 in FIG. 8).

  In the configuration of FIG. 7, as shown in FIG. 8B, when the switch signal transitions immediately after the timing of storing the received data at the START address (start timing of 20 mS), the data of timing T1 is acquired at timing T2. Therefore, the detection timing is delayed by about 40 mS at maximum. On the other hand, according to the configuration of FIG. 8A, even in the same state, as shown in FIG. 8C, the data at timing T0 is acquired at timing T1, so that the detection delay time is reduced. It can be suppressed to about 22 mS.

  If switch signals that should be detected relatively quickly, such as the motor origin position detection sensor, and switch signals that do not require quickness, such as inquiry buttons, are mixed, the operation details corresponding to the game operation state Is preferably switched.

  FIG. 9 is a diagram for explaining a circuit configuration and operation contents in such a case. As shown in FIG. 9A, in this circuit configuration, the upstream shift register 50 and the downstream shift register 50b for the clock signal CK are connected in series, and the latch signal LT and the clock signal CK are supplied in common. doing.

  Further, the inquiry button contact switch signal is supplied to the parallel input terminal of the upstream shift register 50a, and the origin sensor signals P0 and P1 and the switch signal from the effect button are supplied to the parallel input terminal of the downstream shift register 50b. P2 to P5 are supplied. The origin sensor signals P0 and P1 are supplied in duplicate to two parallel input terminals.

  The switch signal input process in such a circuit configuration is as shown in FIG. 9B. First, it is determined whether or not a game operation is in progress (ST70). If the demo screen is being displayed, 16 clock signals CK are supplied to the shift registers 50a and 50b to obtain a 16-bit switch signal, and an inquiry is made based on the 1-byte data of the upstream shift register 50a. The button pressing operation is determined (ST71).

  On the other hand, if the game operation is in progress, in order to shorten the communication time, eight clock signals CK are supplied to the shift registers 50a and 50b, and only the 8-bit data of the downstream shift register 50b is acquired (ST72). .

  Then, if a moving effect that requires acquisition of the origin sensor signals P0 and P1 is being performed, the origin sensor signal P0 is obtained on condition that bit0 and bit1 match (ST74). Similarly, the origin sensor signal P1 is acquired on condition that bit2 and bit3 match (ST74).

  As described above, in the embodiment of FIG. 9, during the movable performance, the switch signal input process (ST42) is not repeated a plurality of M times, as long as a plurality of bits that receive duplicate data match, one time of the serial switch signal Sin. The acquisition process can be completed by reading. Therefore, it is possible to prevent a delay in detection of a sensor signal that requires quickness, and the delay time for detection is about an interrupt cycle (2 mS) at the maximum.

  On the other hand, during button effects that do not require speed as high as motor rotation control, the number of repetitions of the switch signal input process is suppressed to about 3 times, and after that, bit4 to bit7 match three times in succession. (Step ST61 and below).

  Incidentally, FIG. 10A shows a switch signal transmission board 33 similar to FIG. The switch signal transmission board 33 includes an upstream shift register 50a that receives contact switch signals S0 to S7 of an inquiry button, and a midstream shift register that receives origin sensor signals P0 and P1 and switch signals P2 to P5 from a production button. 50b and a downstream shift register 50c that receives the sensor signals E0 to E3 from the monitoring sensor.

  As the monitoring sensor, an open / close monitoring sensor for monitoring the opening / closing of the front frame 3 and the glass door 6, a magnetic sensor for detecting a static magnetic field such as a permanent magnet, and a powerful switch that illegally turns on a detection switch such as the symbol start port 15. An example is a radio wave sensor that detects a radiated magnetic field. As illustrated, the sensor signals E0 to E3 are supplied to the two parallel input terminals in an overlapping manner.

  The switch signal input process is as shown in FIG. 10B. Also in this case, after the latch signal LT is first output (ST79), it is determined whether or not a game operation is in progress (ST80). If the demonstration screen is being displayed, 24 clock signals CK are supplied to the shift registers 50a to 50c to obtain a 24-bit switch signal (ST81).

  Then, abnormality determination processing is executed based on the abnormality monitoring sensor signal SEi supplied redundantly to the parallel input terminals. This is to quickly detect illegal acts regardless of whether or not a game operation is in progress.

  The specific contents of the abnormality determination process are as shown in FIG. First, for the sensor signal Ei having a length of 8 bits, the sensor signal Ei in which the corresponding 2 bits do not match is evaluated as being at a normal level, and then it is determined whether or not there is an abnormal bit (SS1). ). For example, when an 8-bit sensor signal indicates a monitoring sensor [E3, E3, E2, E2, E1, E1, E0, E0] and the abnormal level is 1, [11100001] is [11000000] ] Is determined to be abnormal. In this case, only the sensor signal E3 has an abnormal level.

  If no abnormality is detected based on the determination in step SS1, all error detection timers are cleared to 0 (SS2). If an abnormality is detected, the corresponding error detection timer is incremented. And update (SS3).

  The error detection timer takes into account the possibility that an abnormal situation is erroneously detected due to the influence of noise or the like, and is used to confirm that an abnormal situation is detected continuously for a reference time (eg, 6 mS). Is done. In this embodiment, four error detection timers ER1 to ER4 are prepared corresponding to the four monitoring sensors E3 to E0.

  Next, it is determined whether there are any error detection timers ER1 to ER4 that have reached the reference value TH (SS4). In this embodiment, since the reference time is 6 mS and the execution period of the switch signal input process (ST42) is 2 mS, the reference value TH is 3, and the switch signal input process (ST42) is continuously performed three times or more. Whether or not the same abnormal state is detected becomes a problem. Since the error detection timer is cleared to 0 when the abnormal state recovers in the middle of three times (SS2), erroneous detection of an abnormal situation due to noise or the like is eliminated by this clearing operation.

  If an error detection timer exceeding the reference value TH is detected by the determination in step SS4, the corresponding abnormality notification timers TM1 to TM4 are initialized. The initial set value is not particularly limited, but is an initial value that guarantees an abnormality notification time of about 30 seconds. As the abnormality notification timer, four types TM1 to TM4 are prepared corresponding to the four monitoring sensors E0 to E3.

  Next, after storing the four abnormality notification flags ALM1 to ALM4 in the respective storage areas OLD1 to OLD4, setting processing corresponding to the values of the abnormality notification timers TM1 to TM4 is executed (SS6 to SS9). Here, four abnormality notification flags ALM1 to AML4 are prepared corresponding to the abnormality notification timers TM1 to TM4, and indicate whether or not the abnormality notification operation is being performed.

  Then, the abnormality notification flags ALM1 to ALM4 are set to 0 corresponding to the abnormality notification timers TM1 to TM4 which are 0 (SS7). On the other hand, the abnormality notification flags ALM1 to ALM4 are set to 1 corresponding to the abnormality notification timers TM1 to TM4 which are not 0 (SS8), and the values of the abnormality notification timers TM1 to TM4 corresponding to the abnormality notification flags ALM1 to ALM4 which are 1 are set. Is decremented (SS9).

  Subsequently, it is determined whether or not the abnormality notification flags ALM1 to ALM4 have changed in the switch input process (SS10). Specifically, the values of the abnormality notification flags ALM1 to ALM4 stored in the storage areas OLD1 to OLD4 in the process of step SS6 are compared with the values of the abnormality notification flags ALM1 to ALM4 updated thereafter.

  When the abnormality notification flag ALMi changed from 0 to 1 is detected, the corresponding error notification operation is started (SS11).

  On the other hand, when the abnormality notification flag ALMi changed from 1 to 0 is detected in the determination of step SS10, the corresponding error notification operation is stopped (SS12). If the changed abnormality notification flag ALMi does not exist, the abnormality monitoring subroutine process is terminated without doing anything.

  By the way, when the abnormal situation continues even after the error notification operation starts, the increment process of the corresponding error detection timer ERI is continued (SS3), so that the abnormal situation continues even if the 30 second abnormal notification time expires. As long as this is done, the error notification operation does not end.

  As described above, in this embodiment, in addition to redundantly supplying sensor signals from the same monitoring sensor to the parallel input terminals to determine coincidence, an abnormality notification operation is started on condition that the abnormality level is continued three times. Therefore, even if the monitoring sensor signal is transmitted by the serial transmission method, there is no risk of malfunction. In addition, since the sensor signal from the monitoring sensor also adopts a serial transmission method, even if the number of monitoring sensors increases, the original game control is not so much affected.

  The abnormality determination process (ST82) in FIG. 10B has been described above, and the description of the subsequent processes will be continued. When the abnormality determination process is completed, the inquiry button pressing operation is determined based on the 1-byte data of the upstream shift register 50a, and the corresponding process is executed (ST83). Also in this case, taking the influence of noise into consideration, the corresponding process is executed on condition that the same data is received N times consecutively.

  By the way, in the determination of step ST80, when it is determined that the game operation is currently being performed, 16 clock signals CK are supplied to the shift registers 50a to 55c, whereby a 16-bit switch including the monitoring sensor signal is supplied. A signal is acquired (ST84).

  First, abnormality determination processing is executed for the monitoring sensor Ei (ST85). The contents of the abnormality determination process are the same as when the demonstration screen is being displayed, as shown in FIG. As described above, in this embodiment, the sensor signal from the monitoring sensor Ei is acquired every 2 mS even during the game operation, so that an abnormal situation is not overlooked. In addition, by taking double and triple noise countermeasures, erroneous detection of abnormal situations is prevented.

  When such abnormality determination processing is completed, the subsequent processing is the same as steps ST74 to ST75 shown in FIG. 9B, and the movable effect operation is performed based on the origin sensor signals P0 and P1 and the switch signals P2 to P5. (ST87) or button effect operation (ST88) is appropriately executed.

GM gaming machine 33 peripheral terminal unit 22 control unit LT operation start signal CK clock signal Sin switch signal 50 signal conversion circuit ST50 first means ST51 to ST53 second means ST51 to ST53 third means

Claims (1)

A main control means for executing a lottery process resulting from a predetermined lottery process detection signal and a sub-control means that operates based on a control command received from the main control means, and if the lottery result is a winning state, A gaming machine that shifts to a gaming state advantageous to a person,
Peripheral terminal unit that receives a plurality of control processing detection signals different from the lottery processing detection signal, and is connected to the peripheral terminal unit via a serial communication line, and corresponds to the control processing detection signal received via the peripheral terminal unit A computer circuit of a sub-control means for executing a control operation to be configured,
The peripheral terminal unit is
When the operation start signal is received from the output port of the computer circuit, the control processing detection signal is acquired and held as parallel data, while when the clock signal is received from the output port of the computer circuit, the control processing is held at that time The detection signal is configured to have a signal conversion circuit that outputs the detection signal as serial data to the computer circuit in synchronization with the clock signal.
The computer circuit is:
A first means for outputting an operation start signal to the signal conversion circuit every predetermined time;
A second means for starting the operation after the first means outputs the operation start signal and outputting a predetermined number of clock signals to the signal conversion circuit;
Third means for acquiring serial data output by the signal conversion circuit in response to the clock signal output by the second means in synchronization with the clock signal output by itself;
Have
As the control processing detection signal, all or part of a signal that changes in response to a manual operation, a signal that changes in response to the occurrence of an abnormal situation, or a signal that changes in response to the progress of an effect control operation A gaming machine characterized by being included .