JP4970582B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a ball ball game machine or a slot machine that generates a big hit state by a lottery process caused by a gaming operation, and more particularly to a gaming machine that eliminates a malfunction caused by noise or the like.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7-7-7, a big hit state is established, and the big winning opening is repeatedly opened to generate a profit state advantageous to the player.

  However, in actuality, whether or not the big hit state is determined in advance by the big hit lottery process executed at the time of winning the game ball, and the symbol display unit performs a symbol variation operation exclusively to enliven the player Yes. In the jackpot lottery process, for example, the output value of a hardware-configured random number generation circuit is used as a random number value RND for jackpot determination, and it is determined whether or not it is a jackpot state by comparing this with a jackpot winning value Hit. (Patent Document 1).

  The random number generation circuit is typically as shown in FIG. 11, and includes an oscillation circuit 71 that generates a count clock Φ, a counter 72 that counts the count clock Φ, and a latch that temporarily holds the output of the counter 72. And a circuit 73. In this type of random number generation circuit, the winning switch signal is turned on when the detection switch provided at the symbol start port detects the passage of the game ball. The input terminal CK and the input terminal of the input port 74 are supplied. Therefore, when the winning switch signal is turned on, the count value of the counter 72 at that time is temporarily held in the latch circuit 73.

  On the other hand, the one-chip microcomputer 70 grasps the ON state of the winning switch signal based on the output of the input port 74, and acquires the count value held in the latch circuit 73 at that time as the random value RND.

  In addition, the detection switch arranged at the symbol start opening is configured, for example, by incorporating a high-frequency oscillation circuit and a detection coil. When the game ball 75 passes through the detection coil 76, an ON signal is generated based on the impedance change at that time. Is output (FIG. 12).

Japanese Patent Application No. 2006-157626 JP 2001-293183 A

  By the way, an electromagnetic solenoid is disposed adjacent to the symbol start port on the game board, which returns an ON / OFF operation, and a large number of game balls as magnetic bodies circulate on the game board. Therefore, the detection switch may malfunction due to the influence of electromagnetic noise or irregular movement of a large number of magnetic materials. When the detection switch is turned on, the big hit lottery process is executed in response to this, so that if the detection switch malfunctions, a configuration that can reliably detect this is desired.

In view of this point, Patent Document 2 teaches a software configuration for accurately determining that a game ball has passed through a winning opening. However, in the invention, “first detection means for detecting a winning of a game ball at the winning opening” and “second detection for detecting an on or off state in the first detection means at every interruption time” "Means" is required. Therefore, there is no choice but to make a determination across a plurality of interrupt processes.
In addition to the above-mentioned problems, pachinko machines and other gaming machines have a very short product life of only a few months, so that the playability can be changed greatly only by changing the control program without greatly changing the circuit configuration. desired. Here, in order to change the playability, it is effective to change the arrangement position and the number of arrangements of various winning awards including the symbol start opening arranged on the game board. Therefore, there is a demand for a circuit configuration that can be used in common even when the number of winning holes arranged on the game board changes.

  The present invention has been made in view of the above problems, and can detect a malfunction of the detection switch on the game board and can be used in common even if the playability changes greatly. An object of the present invention is to provide a ball game machine having the following.

In order to achieve the above object, the present invention generates a random number generation circuit or a random number generation process when a specific switch signal is turned ON among switch signals output from a plurality of detection sensors arranged on the game board. A gaming machine having a main control unit that executes a lottery process based on the random number value generated to generate a profit state advantageous to a player, wherein the main control unit is a relay connected to the plurality of detection sensors The board is divided into a main control board that receives the switch signal of the detection sensor via the relay board, and the main control board has a difference in the number of the detection sensors due to a difference in the model of the gaming machine. Regardless, the switch circuit is configured to receive the switch signal by the input circuit having the same configuration, and the number of the input terminals on the detection sensor side of the relay board corresponding to the number of the detection sensors is set. On the other hand, the output terminal on the main control board side is provided more than the number of the detection sensors, and the relay board has an internal configuration so as to transmit a switch signal received by one of the input terminals to a plurality of the output terminals. As a result, the input circuit is configured so that the switch signal in the ON state can be redundantly acquired from different input signal lines without generating an input signal line that is in an open state . The lottery process in the main control unit is executed on condition that the plurality of switch signals are all at the same logic level .

  The input circuit of the present invention adopts the same configuration regardless of the type of gaming machine, but the active element such as an IC and the passive element such as a resistor and a capacitor are all the same including the model number, Although the configuration is the same, the model number of the passive element may be different.

  In the present invention, preferably, when the detection sensor detects the passage of a game ball, a signal current limited by a limiting resistor having a resistance value R flows through the detection sensor, whereby the switch signal is turned on in the control board. The state is grasped. Here, it is preferable that each of the limiting resistors is provided on the main control board in correspondence with the plurality of detection sensors. The limiting resistor is connected between an input signal line connected to the input circuit and a DC power source of the main control board, and a connection point of the limiting resistor and the input signal line is connected to the input circuit. It is effective to be connected to the input terminal.

  In the relay board of the present invention, it is effective that the switch signal received by one of the input terminals is directly transmitted in common to the two output terminals of the relay board. FIG. 10 illustrates this circuit configuration. In this case, the circuit configuration of the main control unit includes a case where the input terminals and the output terminals of the relay board are directly connected in a one-to-one correspondence and a case where one input terminal and the N output terminals are directly connected. There is no need to change. Note that passive elements such as resistors are not prohibited until the circuit constants are changed.

  In the relay board of the present invention, the switch signal received by one of the input terminals passes through the auxiliary resistor r ′ having a resistance value sufficiently smaller than ½ of the resistance value R of the limiting resistor, and the two output terminals of the relay board. May be transmitted in common. FIG. 4 exemplifies this circuit configuration, and the main control unit can make all the circuit components the same including the model number.

  According to the present invention described above, it is possible to reliably detect a malfunction of the detection switch on the game board. Also, even if the playability changes greatly and the number of winning holes on the game board changes, most circuit configurations can be used in common.

It is a perspective view of the pachinko machine shown in an embodiment. It is the front view which illustrated in detail the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a block diagram which shows the circuit structure of a game board relay board. It is a block diagram which shows the deformation | transformation circuit structure of a game board relay board. It is a circuit diagram which shows an example of a random number generation circuit. It is a flowchart explaining the system reset process of a main control part. It is a flowchart explaining the timer interruption process of a main control part. It is a flowchart explaining a part of timer interruption process in detail. It illustrates a modified configuration of the game board relay board. It is a circuit diagram which shows the conventional random number generation circuit. It is drawing explaining the outline | summary of a detection switch.

  Hereinafter, embodiments of the present invention will be described in detail. FIG. 1 is a perspective view showing a pachinko machine GM according to the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side rather than from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. An upper plate 8 for storing game balls for launch is mounted on the front plate 7, and a lower plate 9 for storing game balls overflowing from or extracted from the upper plate 8 and a launch handle 10 are mounted at the bottom of the front frame 3. And are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

As shown in FIG. 2, the game board 5 is provided with a guide rail 13 formed of a metal outer rail and an inner rail in an annular shape, and a liquid crystal color display DISP is provided at the approximate center of the game area 5a inside. Has been placed. In addition, at a suitable place in the game area 5a, a symbol start opening 15, a big winning opening 16, a plurality of normal winning openings 17 (four on the left and right sides of the large winning opening 16), and a single gate 18 are arranged. . Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball. In the illustrated game board, the symbol starting port 15 is single, but two or more symbol starting ports can be provided without particularly changing the circuit configuration shown in FIG. Similarly, the number of the other winning awards 15 to 18 can be increased or decreased as appropriate without changing the circuit configuration (specifically, the circuit configuration of the main control board 21).

  The liquid crystal display DISP is a device that variably displays a specific symbol related to a big hit state and displays a background image and various characters in an animated manner. This liquid crystal display DISP has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. The special symbol display portions Da to Dc execute a reach effect that expects a big hit state to be invited, and the special symbol display portions Da to Dc and the surroundings perform a notice effect that informs the result of the determination indefinitely. The

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time, and the lottery extracted at the time when the game ball passes through the gate 18 is extracted. The stop symbol determined by the random number for use is displayed and stopped.

  For example, the symbol start opening 15 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws 150. When the stop symbol after the fluctuation of the normal symbol display unit 19 displays a winning symbol, it is opened and closed. The claw 15a is opened for a predetermined time. In addition, when a model is changed and an additional symbol start port is provided, for example, the second symbol start port is disposed immediately above the first symbol start port 15 without providing an electric tulip. The

  In any case, when a game ball is won at the symbol start port 15, the display symbols of the special symbol display portions Da to Dc are changed for a predetermined time, and based on the lottery result corresponding to the winning timing of the game ball at the symbol start port 15. Stop at the stop symbol determined. In addition, in special symbol display parts Da-Dc and its circumference, a notice effect may be performed between a series of symbol effects.

  The big winning opening 16 is controlled to open and close by, for example, an opening / closing plate 16a that can be opened forward, but when the stop symbol after the symbol change of the special symbol display portions Da to Dc is a big hit symbol such as “777”, the “big hit game” Is started, and the opening / closing plate 160 is opened.

  After the opening / closing plate 16a of the big prize opening 16 is opened, the opening / closing plate 16a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. In such an operation, the special game is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol of the special symbols, a privilege that the game after the end of the special game is in a high probability state is given.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations. A dashed line in the figure mainly indicates a DC voltage line.

As shown in the figure, this pachinko machine GM includes a power supply board 20 that receives AC 24V and outputs various DC voltages, a system reset signal SYS, etc., a main control board 21 that plays a central role in game control operations, and a main control board. An effect control board 22 that executes a lamp effect and a sound effect based on the control command CMD received from the control board 21; a liquid crystal control board 23 that drives the liquid crystal display DISP based on the control command CMD ′ received from the effect control board 22; Based on a control command CMD "received from the main control board 21, a payout control board 24 for controlling the payout motor M to pay out the game ball, and a launch control board 25 for firing the game ball in response to the player's operation, ,
It is structured around.

  However, in this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the command relay board 26 and the effect interface board 27. Further, the control command CMD ′ output from the effect control board 22 is transmitted to the liquid crystal control board 23 via the effect interface board 27, and the control command CMD ″ output from the main control board 21 is set to the main board relay board 28. Is transmitted to the payout control board 24 via.

  The main control board 21, the effect control board 22, the liquid crystal control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer. Accordingly, the circuits mounted on the control boards 21 to 24 and the operations realized by the circuits are collectively referred to as a function. In this specification, the main control unit 21, the effect control unit 22, and the liquid crystal control unit 23 are used. , And the payout control unit 24. All or part of the effect control unit 22, the liquid crystal control unit 23, and the payout control unit 24 is a sub-control unit.

  By the way, the pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and the new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame-side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, and a frame relay board 32, and these circuit boards are Each is fixed in place on the front frame 3. On the other hand, on the back of the game board 5, a main control board 21, an effect control board 22, and a liquid crystal control board 23 are fixed together with a liquid crystal display DISP and other circuit boards.

  And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place. In this embodiment, the connection connectors C1 to C4 are concentrated in the lower left of the game board 5 as viewed from the back. Then, with the glass door 6 open, the left end of the game board 5 is locked to the front frame 3 from the front side of the front frame 3 to secure a rotation fulcrum, and the game board 5 is rotated around the secured rotation fulcrum. By doing so, the game board 5 is fitted inside the front frame 3. When the game board 5 is fitted, all the connection connectors C1 to C4 are connected, and the connection between the frame side member GM1 and the board side member GM2 is completed, and the pachinko machine GM is operable. .

  As shown in FIG. 3, the power supply board 20 is connected to the main board relay board 28 through the connection connector C2, and is connected to the power supply relay board 30 through the connection connector C3. The main board relay board 28 outputs the system reset signal SYS, the RAM clear signal, the voltage drop signal, the backup power supply, DC12V, and DC32V received from the power board 20 to the main controller 21 as they are. Similarly, the power supply relay board 30 also outputs the system reset signal SYS received from the power supply board 20 and the AC and DC power supply voltages to the effect interface board 27 as they are. The production interface board 27 outputs the received system reset signal SYS to the production control unit 22 and the liquid crystal control unit 23 as they are.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and receives the same system reset signal SYS, RAM clear signal, voltage drop signal, backup power supply as the main control unit 21 receives. Directly with other power supply voltages.

  Here, the system reset signal SYS output from the power supply board 20 is a signal indicating that the AC power supply 24V is supplied to the power supply board 20, and the one-chip microcomputer or other IC element of each of the control units 21 to 24 by this signal. The power is reset. However, in this embodiment, the system reset signal SYS is not supplied to the random number generation circuit (FIG. 4) of the main control unit 21, and the power supply is reset to the random number generation circuit with a specific circuit configuration.

  The RAM clear signal received from the power supply board 20 by the main control unit 21 and the payout control unit 24 is a signal that determines whether or not to initialize all areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. Thus, it has a value corresponding to the ON / OFF state of the initialization switch operated by the staff.

  The voltage drop signal received from the power supply board 20 by the main control unit 21 and the payout control unit 24 is a signal indicating that the AC power supply 24V has started to drop. By receiving this voltage drop signal, each control unit 21, In 24, a necessary termination process is started prior to a power failure or business termination. The backup power source is a DC 5V DC power source that retains data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power source 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 25 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  On the other hand, the effect control unit 22 and the liquid crystal control unit 23 are not provided with the power supply backup function described above. However, as described above, the system reset signal SYS is commonly supplied to the effect control unit 22 and the liquid crystal control unit 23 via the power relay board 30 and the effect interface board 27, and other controls are performed. The power supply reset operation is realized at a timing substantially synchronized with the units 21 and 24.

  As illustrated, the main control unit 21 transmits a control command CMD "to the payout control unit 25 via the main board relay board 28, while the payout control unit 25 receives a prize ball indicating a payout operation of the game ball. A count signal and a status signal CON relating to an abnormality in the payout operation are received, and the status signal CON includes, for example, a replenishment out signal, a payout shortage error signal, and a lower plate full signal.

  The main control unit 21 is connected to each game component of the game board 5 via the game board relay board 29. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The switch signal includes two systems of winning switch signals SWa and SWb transmitted from the symbol start port 15 to the main control unit 21.

  FIG. 4 is a circuit diagram illustrating in detail the portion of the game board relay board 29. In this embodiment, since the symbol starting port 15 is single, the circuit configuration is as shown in FIG. 4B. However, when there are two symbol starting ports, the circuit configuration is as shown in FIG. As is apparent from the two circuit diagrams, there is no change in the circuit configuration of the main control board 21 even if the number of symbol start ports changes. Therefore, the same main control board 21 can be commonly used in a plurality of types of gaming machines that exhibit different playability.

As shown in FIG. 4B, the game board relay board 29 of the present embodiment includes two solenoids L1 and L2 corresponding to the opening / closing claws 15a and the opening / closing plate 16a, various winning holes 15 to 17 and the gate 18. A total of seven corresponding detection switches SW1 to SW7 are connected. Each of the detection switches SW1 to SW7 includes a high-frequency oscillation circuit and a detection coil, and is a through-type proximity switch that detects passage of a game ball based on a change in impedance of the detection coil. The equivalent circuit is as shown in FIG. 4C. The proximity switch main circuit, the switching transistor Q that is turned ON / OFF by the output of the proximity switch main circuit, the protective Zener diode ZD, the internal resistance r, It consists of

  Each of the detection switches SW1 to SW7 has a + terminal and a − terminal. By supplying a positive DC voltage to the + terminal, an ON current flows from the + terminal toward the ON state transistor. ing. Note that a current limiting resistor R needs to be connected in series outside the proximity switch. The current limiting resistor R has a relationship of r << R.

  As is clear from the comparison between FIG. 4 (a) and FIG. 4 (b), in the case of a gaming machine provided with two symbol start ports, eight detection switches SW1 to SW1 are connected to the input terminal of the game board relay board. Although SW8 is connected (FIG. 4A), in the case of the game board relay board 29 of the embodiment, only seven detection switches SW1 to SW7 are connected (FIG. 4B). However, the configuration on the main control board side of the game board relay board 29 is completely the same, and output terminals for eight detection switches are provided. On the main control board side of the game board relay board 29, the output terminal of the detection switch SW7 and the output terminal of the detection switch SW8 are short-circuited, and the shorted output terminal and the + output of the detection switch SW7 of the symbol start port 15 An auxiliary resistor having a resistance value r ′ is internally connected between the terminals. Here, the auxiliary resistor is provided for the purpose of protecting the detection switch SW7, and its resistance value r 'is sufficient to be a value sufficiently smaller than ½ of the limiting resistance value R (r' << R / 2).

  Incidentally, the main control board 21 has a driver 47 for driving the solenoids L1 and L2 and detection switches SW1 to SW7 corresponding to the sensors L1, L2 and SW1 to SW7 connected to the game board relay board 29. And a buffer 41 for receiving a winning switch signal. The input terminals of the driver 47 are pulled up to a DC power source + Vd through pull-up resistors each having a resistance value R. Note that the pull-up resistor also serves as a current limiting resistor for the detection switch. Further, a DC voltage Vs for driving the solenoid is supplied from the main control board 21 to the game board relay board 29.

  Since the main control board 21 and the game board relay board 29 are connected as described above, for example, when any of the detection switches SW1 to SW6 is turned on, the current flowing out from the DC voltage + Vd of the main control board 21 Flows through the path of the pull-up resistor (current limiting resistor) having the resistance value R → the game board relay board 29 → the + output terminal of the detection switch SWi. The input voltage to the buffer 41 is an L level of Vd × r / (r + R).

  On the other hand, when the detection switch SW7 at the symbol start port is in the ON state, ON currents flow through two paths that respectively pass through the pull-up resistors, and after these ON currents merge at the game board relay board 29, It flows into the + output terminal of the detection switch SW7. Here, since an auxiliary resistor having a resistance value r ′ is internally connected to the game board relay board 29, the input voltage to the buffer 41 slightly increases to Vd × (r ′ + r) / (r ′. + R + R / 2) (FIG. 4C), however, since the values of r and r ′ are sufficiently small (r, r ′ << R / 2), the input voltage to the buffer 41 is L level. Therefore, in the present embodiment, the number of the various winning awards including the symbol start port 15 can be appropriately changed without changing the circuit elements of the main control board 21 at all regardless of the increase or decrease in the number of the detection switches SWi. it can.

By the way, in the above description, the positive terminal of the detection switch SWi is connected to the main control board 21 via the game board relay board 29, but instead of such a configuration, the negative terminal of the detection switch SWi is connected to the game. It may be connected to the main control board 21 via the panel relay board 29. FIG. 5 shows this circuit example. In the main control board 21, the ON current flowing out from the negative terminal of the detection switch SWi is guided to the ground through a pull-down resistor having a resistance value R. Note that the pull-down resistor serves as both a load resistor and a current limiting resistor. Even when such a circuit configuration is adopted, the circuit configuration of the game board relay board 29 is substantially the same, and the circuit configuration of the main control board 21 is made common regardless of the number of symbol start ports.

  However, in the circuit configuration of FIG. 5, since the DC power source Vd of the main control board 21 is supplied to the game board relay board 29, there is a high possibility that electromagnetic noise is superimposed on the power line. For this reason, the DC power supply Vd cannot be shared with the power supply voltage of the computer circuit on the main control board. In this regard, in the configuration of FIG. 4, the power supply line of the DC power supply Vd is not routed to the outside, so the above problems are few.

  Further, in the circuit configuration of FIG. 5, the capacitor C must be connected in parallel to the load resistance R as a countermeasure against noise and chattering, so that the rising of the winning switch signal SW is slow, but in the circuit configuration of FIG. Since only the pull-up resistor can cope, the winning switch signal SW is not dull and is resistant to disturbance noise.

  FIG. 6 is a circuit diagram showing a random number generation circuit in the main control unit 21 in particular. The random number generation circuit is a circuit that generates a random number value RND used in the big hit lottery process (ST54 in FIG. 6) executed at the time of winning a game ball to the symbol start opening 15, and is received from the game board relay board 29. The system operates based on the system winning switch signals SWa and SWb.

  As shown in the drawing, the system reset signal SYS output from the power supply board 20 is not supplied to the random number generation circuit, and each IC element is reset by the power reset signal RST generated by itself when the power is turned on. Therefore, even if an unauthorized player misuses a plurality of connectors (such as C2) provided between the power supply board 20 and the main control board 21 to generate an intentional system reset signal SYS, Each IC element is not reset at the timing desired by the person.

  The random number generation circuit includes an oscillation circuit 40 that generates a count clock Φ, a buffer 41 that receives two winning switch signals SWa and SWb from the symbol start port 15, and a switch that temporarily holds the voltage levels of the winning switch signals SWa and SWb. The signal latch circuit 42, two series of counting circuits 43 that count the counting clock Φ, and an abnormality detection circuit 44 that detects an abnormality in the counting operation of the counting circuit 43 are mainly configured. In this embodiment, the abnormality detection circuit 44 also serves as a reset circuit that automatically generates a power supply reset signal, and therefore may be referred to as a reset circuit 44 in the following description.

  The winning switch signals SWa and SWb are also supplied to the input port 45, and the CPU core of the one-chip microcomputer 21A turns on the switch signal of the symbol start port 15 by periodic switch input processing (ST23 in FIG. 6). Duplicate status is grasped. Then, the CPU core that grasps the ON state of the winning switch signals SWa and SWb acquires the 16-bit data of the counting circuit 43 and sets it as the random value RND (ST27 in FIG. 6). The 16-bit data is acquired every 8 bits corresponding to the processing capability of the CPU core.

  Hereinafter, the circuit configuration will be described in more detail. The oscillation circuit 40 includes a crystal oscillation circuit OSC that oscillates a high-frequency pulse of about 25 MHz and a D-type flip-flop FF1 wired in a toggle manner. Then, the output signal of the crystal oscillation circuit OSC is supplied to the clock terminal CLK of the D-type flip-flop FF1, so that the oscillation frequency is divided by two to become a count clock Φ having a frequency of about 12.5 MHz.

The switch signal latch circuit 42 includes two D-type flip-flops FF2 and FF3. The D input terminal of each flip-flop FF2, FF3 has a buffer 41.
The winning switch signals SWa and SWb are supplied via. On the other hand, the inverted count clock Φ ′ is supplied to the clock terminals CLK of the flip-flops FF2 and FF3. Therefore, the value of the D input terminal at the signal edge of the inverted count clock Φ ′ (that is, the level value of the winning switch signals SWa and SWb) is acquired by the flip-flops FF2 and FF3 in synchronization with the inverted count clock Φ ′. The

  The counting circuit 43 includes two systems of 16-bit counters CTa and CTb, two latches (count value holding circuits) Ra and Rb each receiving the outputs of the counters CTa and CTb, and outputs of the latches Ra and Rb. The output register Ro outputs 8-bit data selected by the control signal CTL. The 16-bit counters CTa and CTb are both ripple counter type binary counters. The carry signal CYa of the 16-bit counter CTa is output as the detection pulse PL.

  A latch clock RCK which is a Q output signal of the flip-flops FF2 and FF3 is supplied to the first latch Ra and the second latch Rb. In synchronization with the edge of the latch clock RCK, the count values of the counters CTa and CTb at that time are acquired by the latches Ra and Rb having a 16-bit length, and the values are held until the next latch clock RCK is received.

  The output register Ro operates based on the control signal CTL output from the one-chip microcomputer 21A. The control signal CTL is 4-bit data for output switching. The upper 8 bits of the first latch Ra, the lower 8 bits of the first latch Ra, the upper 8 bits of the second latch Rb, and the lower 8 bits of the second latch Rb. Is selected and output to the data bus of the one-chip microcomputer 21A. Note that the output of the output register Ro is one of three states of H level, L level, and high impedance.

  The abnormality detection circuit 44 includes a D-type flip-flop FF4 wired in a toggle manner and a watchdog circuit 46. The detection pulse PL output from the counting circuit 43 is supplied to the clock terminal CLK of the D-type flip-flop FF4. Therefore, an output pulse obtained by dividing the detection pulse PL by two is output from the Q output terminal of the D-type flip-flop FF4.

  In this embodiment, TA8030S (TOSHIBA), which is a dedicated IC, is used as the watchdog circuit 46. In the watchdog circuit 46, when the clear pulse received at the clear terminal WD is interrupted, the oscillation circuit including the resistor R1 and the capacitor C1 enters a free-running state, and a pulse signal is output from the output terminal RST1. However, in a state where a regular clear pulse is supplied to the clear terminal WD, the output terminal RST1 maintains the H level.

  As shown in the drawing, the detection pulse PL divided by two is supplied to the clear terminal WD of the watchdog circuit 46 via the differential capacitor C3. Therefore, in the normal state where the counter CTa periodically outputs the carry signal CYa, the detection pulse PL functions as a clear pulse, so that the output terminal RST1 of the watchdog IC 46 maintains the H level. On the other hand, when the counter CTa stops the counting operation, the clear pulse (detection pulse PL) is interrupted, so that a pulse signal (abnormality detection signal ABN) is output from the output terminal RST1 of the watchdog IC 46 in the self-running state.

This abnormality detection signal ABN is supplied to the input port of the one-chip microcomputer 21A via a waveform shaping circuit by two NOT gates G3 and G4. Therefore, the one-chip microcomputer 21A can grasp the abnormality of the random number generation circuit by periodically determining the level of the abnormality detection signal ABN (ST24 in FIG. 8). Counter CT of random number generation circuit
Since the output values of a and CTb are used as the random value RND for the big hit lottery process (ST27 in FIG. 8), it is extremely important that the output values are updated at high speed as designed, and the abnormality detection circuit 44 has great significance. .

  By the way, the watchdog circuit 46 is configured such that after receiving a + 5V DC power supply, the output terminal RST2 rises to H level after a slight delay time τ1 determined by the resistor R1 and the capacitor C1. The output signal of the output terminal RST2 is nothing but the power supply reset signal, and therefore the watchdog circuit 46 also serves as the reset circuit 44.

  The power reset signal RST is supplied to the clear terminal CLR of each IC element in a state where the delay time τ2 is further increased by passing through the capacitor C2 and the two NOT gates G1 and G2. Specifically, the power reset signal RST is supplied to the four flip-flops FF1 to FF4 and the clear terminal CLR of the counting circuit 43.

  The power reset signal RST is supplied to each IC element at least by τ1 + τ2 from the power-on timing. This delay time τ1 + τ2 is related to the associated passive elements (R1, R2, C1, C2, etc.) It fluctuates depending on variations in characteristics of active elements (46, G1, G2, etc.) and temperature and humidity at that time. Therefore, the elapsed time from when the power is turned on until the counting circuit 43 actually starts the counting operation varies with each game machine, and varies depending on the daily temperature and humidity even in the same game machine. . According to a confirmation experiment in which variations of all the related elements were integrated, a variation of about 2.5 mS was confirmed as a whole in the delay time of the power reset operation.

  On the other hand, since the frequency of the count clock Φ is about 12.5 MHz, the difference in the count value of the count circuit 43 due to the above-described variation in delay time (time variation) becomes an enormous number of about 30000, and the prospects of the unauthorized player Completely fails. That is, even if the system reset signal SYS is generated or the power supply voltage is turned ON / OFF and the intentional winning switch signal SW is generated by some illegal method, the winning is achieved at the timing when the big hit winning value Hit is reached. It is impossible to supply the switch signal SW to the random number generation circuit.

  Next, an outline of a program of the main control unit 21 that controls the game operation in an integrated manner will be described. 7 to 9 are flowcharts showing a control program of the main control unit 21. The control program of the main control unit 21 includes a system reset process (FIG. 7) that is activated based on restoration or input of the power supply voltage, and a maskable timer interrupt process (FIG. 8 (FIG. 8 ( a)). Note that a Z80 CPU (Zilog) equivalent product is built in the one-chip microcomputer 21A that realizes these processes. The one-chip microcomputer 21A also has a built-in watchdog timer, and is configured to forcibly reset the CPU when periodic clear processing is interrupted.

  Hereinafter, the system reset processing program (main processing) will be described with reference to FIG. The main process starts when the initialization switch (not shown) is turned off and the power is turned on, such as when recovering from a power outage, and when the game hall is opened. May be turned on to turn on the power. Note that the runaway of the control program may start the watchdog timer and forcibly reset the CPU.

In any case, the Z80 CPU first sets itself to the interrupt disabled state (ST1) and sets to the interrupt mode 2 (ST2). Further, the value of the stack pointer SP in the CPU is initialized to the final address of the stack area (ST3). In this embodiment, the operation at the time of power shutdown is not resumed when the power is restored (the CPU register is not saved), so there is no problem even if the stack pointer SP is initially set. That is, when the stack pointer SP is initialized, there is no problem even if the return address (= start address of the random number update process ST21) of the power monitoring subroutine ST20 saved in the stack area before the power is shut down is destroyed. Absent.

  When the processing of step ST3 is completed, the values of the internal registers including each part of the one-chip microcomputer are initialized (ST4), and then the value of the RAM clear signal is determined (ST5). As described above, the RAM clear signal is a signal for determining whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer 21A, and the ON / OFF state of the initialization switch operated by the staff is set. It has a corresponding value.

  Here, assuming that the RAM clear signal is in the ON state, following the determination in step ST5, the entire area of the built-in RAM is cleared to zero (ST9). Therefore, the value of the backup flag BFL set in the process of step ST37 in FIG. 8B becomes zero together with other checksum values.

Next, a power-on command for notifying that the RAM area has been cleared to zero is output (ST10), and a CTC (Z80 counter timer circuit for outputting an interrupt signal INT for starting a timer interrupt operation (FIG. 8A) is output. ) Is initially set (ST11). Then, with the CPU set to the interrupt disabled state (ST12), update processing is executed for various counters (ST13), and then the CPU is returned to the interrupt enabled state and returns to step ST12.

  Therefore, in this embodiment, the counter is updated in a state where the timer interrupt is prohibited, and the interrupt signal INT supplied from the CTC to the CPU is accepted only immediately after the execution of step ST14. Therefore, after the timer interrupt process is completed, the process is always re-executed from the process of step ST12, and it is not necessary to save the CPU registers at the beginning of the timer interrupt process. In this way, the configuration that eliminates processing unrelated to game control is extremely effective for timer interrupt processing that should complete complex and sophisticated performance processing within a limited time within 2 mS.

  The counter updated in step ST13 includes an out symbol counter. This out symbol counter is used for the big hit lottery process (ST54) in the special symbol processing (ST27) in FIG. This is a counter for determining what kind of out-of-game is to be produced when the result is out-of-game.

  Returning to the determination process in step ST5, the initialization switch (RAM clear signal) is in the OFF state when the CPU is forcibly reset or when the CPU is restored from the power failure state. In such a case, the content of the backup flag BFL is determined following the determination in step ST5 (ST6). The backup flag BFL is data indicating that the operation of the power supply monitoring process of FIG. 8B has been executed. In this embodiment, the backup flag BFL is set to 5AH in the process of step ST37 when the power is turned off. It is cleared to zero in the process of step ST33 after the power is restored.

  When the power is turned on or when recovering from a power failure, the content of the backup flag BFL is 5AH. However, if the program goes into a runaway state for some reason and a CPU reset operation is caused by the watchdog timer, the backup flag BFL = 00H. Therefore, if BFL ≠ 5AH (normally BFL = 00H), the process proceeds from step ST6 to step ST9 to return the operation of the gaming machine to the initial state.

  On the other hand, if the backup flag BFL = 5AH, a checksum calculation for calculating a checksum value is executed (ST7). Here, the checksum operation is an 8-bit addition operation for the work area of the built-in RAM. When the checksum value is calculated, the calculation result is compared with the stored value at the SUM address in the RAM (ST8).

  In the SUM address, the checksum value by the same checksum calculation is stored in the power supply monitoring process (FIG. 8B) executed when the voltage drops (ST38). The stored calculation results are maintained by a backup power source together with other data in the built-in RAM. Therefore, the two should be matched by the determination in step ST8.

  However, if the checksum calculation (ST38) cannot be executed when the power is turned off, or if it can be executed, the data in the work area will be damaged until the checksum calculation (ST7) of the main process is executed. In such a case, the determination result in step ST8 is inconsistent. If data corruption is detected due to a discrepancy between the determination results, the process proceeds to step ST9 to execute a RAM clear process, and the operation of the gaming machine is returned to the initial state. On the other hand, if it is determined in step ST8 that the checksum value obtained by the checksum calculation (ST7) matches the stored value at the SUM address, the process proceeds to step ST11.

  Next, a timer interrupt processing program (FIG. 8A) that is started every 2 mS while interrupting the main processing described above will be described. When the timer interrupt occurs, the power supply monitoring process is immediately executed without saving the CPU register (ST20). This is because the timing at which the timer interrupt process is started is fixed immediately after step ST14.

  In the power supply monitoring process (ST20), the level of the voltage drop signal supplied from the power supply board 20 is determined. The specific processing content will be described later. When the power monitoring process (ST20) ends, the value of the winning counter RG used in the lottery operation in the normal symbol process (ST26) is updated (ST21). Note that the random value RND for jackpot determination used in the lottery operation in the special symbol process (ST27) is generated by the random number generation circuit of FIG. 6 and is not updated in the process of step ST21.

  When the winning random number update process (ST21) ends, a timer subtraction process is performed for the timer that manages the time of each gaming operation (ST22). The timer to be subtracted here is mainly used for managing the opening time of the electric tulip and the special winning opening and other game effect times.

  Subsequently, ON / OFF signals of various switches including the winning detection switches of the symbol start opening 15 and the big winning opening 16 are inputted, and the ON / OFF signals are stored in the work area (ST23). The winning switch signals SWa and SWb supplied from the symbol starting port 15 via two paths are acquired via the input port 45, and when the rising edges of the winning switch signals SWa and SWb are detected, the work area ( An ON signal is stored in the EDG address.

  FIG. 9A is a flowchart illustrating in detail the acquisition processing of the winning switch signals SWa and SWb. The winning switch signals SWa and SWb in this embodiment indicate the ON / OFF state of the same detection switch SW7. However, since the signal transmission path is different, disconnection or contact failure may occur in any of the paths. In addition, any data may be garbled due to the influence of electromagnetic noise or the like.

  Therefore, in the present embodiment, the validity of the winning switch signal to be acquired is ensured by comparing the two winning switch signals SWa and SWb. Note that it is possible to detect an abnormality with only simple processing (ST53 to ST56) in one interrupt processing.

  Hereinafter, description will be made based on FIG. 9A. First, the 8-bit data of the input port 45 is continuously and repeatedly acquired in the accumulator ACC and B register of the CPU (ST50, ST51). Of the 8-bit data of the input port 45, bit1 is the winning switch signal SWa and bit0 is the winning switch signal SWb.

  Steps ST50 to ST52 are repeated until the 8-bit data in the accumulator ACC and the B register coincide with each other, considering the case where the input data is not stable due to the influence of ringing or the like. Further, although the same winning switch signal is supplied from the detection switch SW7 to the lower 2 bits of the input port 45, it is considered that the transmission delay time is slightly different because the transmission path is different. That is, as shown in FIG. 9B, the rising timings of the winning switch signal SWa (bit1) and the winning switch signal SWb (bit0) may be shifted, so that steps ST50 to ST52 are also meant to absorb this time difference τ. This process is effective.

  If the accumulator ACC matches the 8-bit data in the B register as a result of the processing in steps ST50 to ST52, the 8-bit data in the ACC is right-shifted by 1 bit, and the right-shifted data is ANDed with the data in the B register. (ST53). Then, the AND data is ANDed with the mask data 01H to confirm that bit1 and bit0 of the acquired data match (ST53 to ST54).

  As described above, bit1 is the winning switch signal SWa and bit0 is the winning switch signal SWb, which should be essentially the same. However, when either of the two signal transmission paths has a disconnection or poor contact, the winning switch signal SWa and the winning switch signal SWb do not match. In addition, the two signals may not match due to the influence of noise.

  Therefore, in such a case, the processing of steps ST50 to ST56 is repeated while incrementing (+1) the abnormal count counter CTR (ST55). If the winning switch signal SWa and the winning switch signal SWb do not match no matter how many times these processes are repeated, it is determined that a failure has occurred and error processing is executed (ST57). As described above, in the present embodiment, the abnormality of the symbol start opening 15 and the winning switch signal SW, which is the most important for this type of gaming machine, can be quickly detected by an extremely simple program process.

  On the other hand, if bit 1 and bit 0 of the acquired data match, the data at the BUF address is acquired in ACC, all bits are inverted, and then ANDed with the data in the B register (ST58). In the BUF address, 8-bit data of the input port 45 acquired at the previous timer interruption is stored (see ST59). Therefore, the process of step ST58 determines whether or not the previous acquired data (8 bits) and the current acquired data (8 bits) completely match. For example, when the winning switch signal rises at the time of this timer interruption, the lower 2 bits of the acquired data do not match the lower 2 bits of the previous acquired data, and the result of the AND operation in step ST58 Two bits become one.

As described above, the ACC after the processing of step ST58 holds bit data indicating the rising edge of the acquired data. Therefore, next, the ACC data is stored in the EDG address, and the value of the B register holding the current acquired data is stored in the BUF address (ST59). The data of the EDG address is referred to in the special symbol process (ST27). The processing in the case where there is a single symbol start port has been described above, but when there are two symbol start ports and the independent winning switch signal SWa and winning switch signal SWb are acquired, the determination of step ST52 is made. Later, the process of step ST58 is executed. Therefore, only a very limited control program change is required.

  Now, returning to FIG. 8, the description will be continued. When the switch input process (ST23) is completed as described above, an error management process is performed (ST24). The error management process includes a determination as to whether an abnormality has occurred inside the device, such as whether or not the supply of game balls has stopped or the game balls are clogged. In this error management process (ST24), the level of the abnormality detection signal ABN is also determined. If an abnormality is recognized in the operation of the counting circuit 43, an error process including a notification process is started. In the present embodiment, since the random number value RND for jackpot determination is generated by the counting circuit 43, when the operation of the counter CTa is stopped, an abnormality detection signal is taken every 2 mS so that an appropriate action can be taken immediately. The ABN level is determined (ST24).

  Next, after executing the management process based on the prize ball counting signal received from the payout control unit 24 (ST25), the normal symbol process is performed (ST26). The normal symbol processing means determination as to whether or not to operate an ordinary electric accessory such as an electric tulip. Specifically, when it is determined that the game ball has passed through the gate based on the switch input result in step ST33, the winning counter RG updated in the random number updating process (ST21) is compared with the winning winning value. Done. If the comparison result is a winning state, the operation mode is changed to the winning operation mode. In addition, if it is a hit, processing for the operation of a normal electric accessory such as an electric tulip is performed.

  Then, the special symbol process which shows a principal part in FIG.9 (b) is performed (ST27). The special symbol process is a determination as to whether or not to operate a special electric accessory such as the special winning opening 16. First, it is determined whether or not the game ball has passed the symbol start port by the switch input process of step ST23 (ST60). Specifically, whether or not the winning switch signal is in an ON state is determined based on the bit 0 or bit 1 of the data at the EDG address. Whether the winning switch signal has risen or fallen is specified by bit 0 or bit 1 of the data at the BUF address.

  If it is determined that the winning switch signal is in the ON state, 16-bit length data relating to the winning switch signal SWa is acquired from the counting circuit 43 in FIG. 6 (ST61 to ST62). Specifically, the upper 8-bit data of the 16-bit latch Ra is acquired at the address RND_H while switching the output switching signal CTL, and subsequently, the lower 8-bit data of the 16-bit latch Ra is acquired at the address RND_L.

  After the acquisition processing of the 16-bit length data of the latch Ra related to the winning switch signal SWa is completed, the upper 8-bit length data of the 16-bit latch Rb related to the winning switch signal SWb is acquired in the B register (ST63). Then, the data of the B register and the address RND_H are compared, and it is determined whether or not the two numerical values are greatly different.

  If the 8-bit data matches or is approximately equal, the big hit lottery process is executed based on the 16-bit length data acquired at the addresses RND_H and RND_L (ST65). Then, if the lottery result is a winning state, the operation mode is changed to the big hit operation mode. In addition, if it is a big hit, processing for the operation of special electric accessories such as a big prize opening is performed.

On the other hand, if it is determined in step ST64 that the two numerical values are significantly different, it is assumed that an abnormality has occurred in any of the signal paths from the buffer 41 to the output register Ro in FIG. Judgment is made and error processing is executed (ST66). In the present embodiment, abnormality detection is performed based on the carry signal CYa of the counter CTa, and a ripple counter is used for the counters CTa and CTb. Therefore, the signal path abnormality relating to the winning switch signal SWa is detected. Can be grasped by the abnormality detection signal ABN. However, although the signal path related to the winning switch signal SWa is normal, the signal path related to the winning switch signal SWb may be abnormal. In such a case, all signal paths may become abnormal in the near future. Since the property is high, the meanings of steps ST63 to ST64 of this embodiment are not limited. If there are two symbol start ports, the processing of steps ST63 to ST64 is skipped.

  By the way, the reason why the lower 8 bit data of the latch Ra and the latch Rb is not considered as a problem in the determination of step ST64 is that (a) the same count clock Φ is supplied to the two counters CTa and CTb. This is because the count values of the counter CTa and the counter CTb may be different from each other, and (b) the timing of the latch clock RCK supplied through the two paths is shifted. Note that the difference in timing of the latch clock RCK can be expected not to exceed 255 in terms of the count clock Φ, so the upper 8 bits of the latch Ra and the latch Rb are determined.

  As described above, since the main part of the special symbol process (ST27) has been described, the description will be continued by returning to FIG. After the special symbol processing (ST27), the lighting operation of the LEDs managed by the main controller 21 is advanced (ST28), and the solenoid driving processing for realizing the opening / closing operation of the electric tulip, the big prize opening, etc. is executed (ST29). ), The CPU is returned to the interrupt permission state EI, and the timer interrupt is finished (ST30). As a result, the process returns from the interrupt process routine to the infinite loop process (FIG. 5) of the main process, and the process of step ST12 is executed.

  Next, the power supply monitoring process (ST20) shown in FIG. In the power supply monitoring process (ST20), first, a voltage drop signal supplied from the power supply board 20 is acquired through an input port (not shown) (ST31), and it is determined whether it is an abnormal level (ST32). If it is not an abnormal level, the abnormal number counter and the backup flag BFL are cleared to zero and the process is terminated (ST33).

  On the other hand, if the voltage drop signal is at an abnormal level, the abnormal number counter is incremented (+1) (ST34), and it is determined whether the counting result exceeds the upper limit value MAX (ST35). This is because the data acquired from the input port may be garbled due to the influence of noise or the like, and the abnormal level is continuously set for a predetermined number of times (for example, upper limit MAX = 2). In the case of maintaining, it is determined that the AC power source is actually shut off.

  Thus, in this embodiment, even when the power is shut off, the subsequent backup processing is not started immediately, and the operation start timing is delayed by MAX × 2 mS. However, (1) The power supply drop signal is not a drop in the DC power supply voltage, but a drop in the AC DC voltage is detected. (2) The DC power supply voltage is maintained for a while after the AC power supply is shut off by a large capacity capacitor. (3) The power supply monitoring process is repeated at a high speed (every 2 ms), and (4) the backup process is extremely simple and finishes quickly, so there is virtually no adverse effect.

  By the way, as a result of the determination in step ST35, if the count value of the abnormal number counter coincides with the upper limit value MAX, the abnormal number counter is cleared to zero (ST36), and then 5AH is set to the backup flag BFL (ST37). Next, the same calculation as in step ST7 of the main routine is executed for the same work area (work area), and the calculation result is stored (ST38). The operation to be executed is typically an 8-bit addition operation.

Thereafter, the one-chip microcomputer 21A is set in a RAM access prohibited state (ST39), and output data of all output ports is cleared (ST40). As a result, unreasonable data is prevented from being transmitted to the payout control unit 24 that starts the same type of power supply monitoring process later than the main control unit 21. When the above backup process is completed, the generation of the interrupt signal INT is prohibited by the setting process for the CTC, and the DC power supply voltage is lowered while repeating the infinite loop process (ST41). At this timing, the CPU is originally in an interrupt disabled state (see ST30). However, in this embodiment, an interrupt signal from the CTC is used to eliminate as much as possible the possibility of malfunction due to a drop in power supply voltage. INT output is also prohibited.

  The embodiment of the present invention has been specifically described above, but the specific description content does not limit the present invention at all, and various modifications can be made. For example, in the above description, the random number value RND for the big hit lottery is generated by the random number generation circuit shown in FIG. 6, but the random number value RND may be generated by a program process. In this case, for example, as in the case of the hit counter RG, the big hit counter may be periodically updated in the timer interrupt process.

  4 and 5, the auxiliary resistor r ′ is internally connected. However, the auxiliary resistor is omitted and the input terminal and the output terminal of the game board relay substrate 29 are connected inside the board. It may be short-circuited. However, in this case, it is preferable to change the resistance value R of the current limiting resistor of the main control board 21 and the capacitance value C of the capacitor.

  FIG. 10 is a circuit diagram showing such an embodiment. An ON current flows to the detection switch SW7 of the symbol start port 15 via two paths, but the input voltage to the buffer 41 becomes an L level of Vd × r / (R + r) (FIG. 10A )). On the other hand, in the case of the circuit configuration of FIG. 10B, the winning switch signal in the ON state becomes the H level of Vd × R / (r + R). Therefore, also in the embodiment of FIG. 10, only the resistance value R of the current limiting resistor is changed, and there is no need to change anything about the circuit configuration of the main control board. The limiting resistor having the resistance value 2R is actually configured by directly connecting two resistance elements having the resistance value R, and one of the resistance elements is short-circuited by the jumper line JP. Then, a limiting resistor having a resistance value of 2R is realized by cutting the jumper line as necessary.

  If the detection switch SWi having a wide allowable range for the ON current value is used and / or the resistance value R of the current limiting resistor is optimally designed, the circuit configuration of FIG. Can be realized. That is, the same main control board 21 can be used in common regardless of whether the number of symbol start ports is one or two.

SWi detection sensor 29 Relay board 21 Main control board 41 Input circuit

Claims (6)

When a specific switch signal is turned on among the switch signals output from a plurality of detection sensors arranged on the game board, a lottery process based on a random number generated by a random number generation circuit or a random number generation process is executed. A gaming machine having a main control unit for generating a profitable state advantageous to a player,
The main control unit is configured to be divided into a relay board connected to the plurality of detection sensors and a main control board that receives a switch signal of the detection sensor via the relay board, The switch signal is received by the input circuit having the same configuration regardless of the difference in the number of the detection sensors due to the difference in the machine type.
The number of input terminals on the detection sensor side of the relay board corresponding to the number of the detection sensors is provided, while the number of output terminals on the main control board side is provided more than the number of the detection sensors,
The relay board is internally configured to transmit a switch signal received by one of the input terminals to a plurality of the output terminals,
The input circuit is configured so that the switch signal in the ON state can be obtained from different input signal lines without generating an input signal line that is in an open state,
A ball game machine configured to execute the lottery process in the main control unit on condition that a plurality of switch signals obtained in duplicate are all at the same logic level .   When the detection sensor detects the passage of a game ball, a signal current limited by a limiting resistor having a resistance value R flows through the detection sensor, whereby the ON state of a switch signal is grasped on the control board. 1. A ball game machine according to 1.   The ball game machine according to claim 2, wherein the limiting resistor is provided on the main control board in correspondence with the plurality of detection sensors.   The limiting resistor is connected between an input signal line connected to the input circuit and a DC power source of the main control board, and a connection point between the limiting resistor and the input signal line is an input terminal of the input circuit The ball game machine according to claim 2 or 3, wherein the ball game machine is connected to.   5. The relay board is configured so that a switch signal received by one of the input terminals of the relay board is directly transmitted in common to two output terminals of the relay board. Ball game machine.   A switch signal received by one of the input terminals of the relay board is transmitted in common to the two output terminals of the relay board through an auxiliary resistor r ′ having a resistance value sufficiently smaller than 1/2 of the resistance value R. The bullet ball game machine according to claim 2, wherein the relay board is configured as described above.