JP2014087675A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine executing appropriate control operation without wasting a circuit space and with a highly universal circuit configuration.SOLUTION: A main control part 21 is configured to include an electron device 21A incorporating, along with a CPU, a circuit REV coping with an abnormality for resetting the CPU when the electron device 21A does not receive clear data until monitoring time. Designation of a function regarding whether the circuit REV coping with an abnormality is allowed to function and/or the monitoring time are set by setting data written to a predetermined function register 70 based on a control program.

Description

  The present invention relates to a gaming machine that generates a big hit state by a lottery process caused by a gaming operation, and more particularly to a gaming machine that can realize a high-level control operation while preventing waste of memory.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passing of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display time is changed in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7-7-7, a big hit state is established, and the big winning opening is repeatedly opened to generate a gaming state advantageous to the player.

  Whether or not to generate such a gaming state is determined by a jackpot lottery executed on the condition that a game ball is won at the symbol start opening, and the above symbol variation operation and other effect operations are Based on the lottery results.

  This type of gaming machine is composed of a plurality of circuit boards equipped with CPUs in order to enrich production operations, and executes a big hit lottery process to output a control command for specifying the lottery result. Generally, it is divided into a control board and a sub-control board that receives various control operations and executes various presentation operations (Patent Document 1).

  In addition, even if the program processing falls into an infinite loop due to the influence of noise or the like, there are not a few gaming machines equipped with a watch dog timer so as to quickly escape from the abnormal state (Patent Document 2).

JP 2011-104072 A JP 2002-224400 A

  However, since the watchdog timer has a timer circuit configured to be able to perform clear processing and a time constant circuit that defines a timeout time of the timer circuit, there is a problem that the circuit space for the timer circuit cannot be ignored. is there. In other words, because of the increasing sophistication of performance control operations in modern gaming machines, it is necessary to place high-function circuits and circuit elements in a limited circuit space, and heat radiation is more efficient than high-performance circuit elements. Therefore, there is a problem that it is desired to secure a margin in the circuit space as much as possible.

  In addition, the conventional watchdog timer regulates the time-out time with a time constant circuit composed of a capacitor and a resistor, so the time-out time differs from game machine to game machine due to variations in circuit element characteristics. there were. In other words, in order to realize complex and sophisticated control operations, the control interval specified by the timer interrupt cycle should be optimized to be short, and the timeout time should be optimized accordingly. is there.

  Furthermore, in this type of gaming machine, security countermeasures are important, but there is a configuration that can improve the security level without unnecessarily wasting memory space and without complicating the hardware configuration. desired. On the other hand, since this type of gaming machine generally has a short life cycle and it is necessary to develop new models one after another, it is desirable to have a configuration in which the gameability and the security level can be changed without changing the circuit configuration.

  The present invention has been made in view of the above problems, and provides a gaming machine capable of executing appropriate control operations without wasting circuit space and having a highly versatile circuit configuration. The purpose is to do.

  In order to achieve the above object, the present invention executes a lottery process caused by a predetermined switch signal and outputs a control command for specifying the lottery result, and a lottery result specified by the control command. The main control means includes a CPU that executes a control operation including a lottery process, a RAM that is appropriately accessed during the control operation, and a control unit. A control program that prescribes the operation, a ROM that stores operation parameters necessary for the control operation in a fixed manner, and an abnormality handling unit that resets the CPU if no clear data is received before the predetermined monitoring time is reached. A function register capable of setting data defining the internal operation of the element, and a single electronic element having a built-in function, and whether or not the abnormality handling means is functioned Ability specified, and / or monitoring time of the anomaly means is configured to be defined by the set data set to a predetermined function register, based on the control program.

  In the present invention, since the abnormality handling means is incorporated in a single electronic element together with the CPU, no additional circuit space is consumed for the abnormality handling means. Further, since the abnormality handling means is not exposed to the outside, it is effective in terms of security. Furthermore, since the monitoring time is defined in accordance with the setting data set by the control program, it is not necessary to change the circuit configuration of the main control means even if the model of the gaming machine is changed. Further, whether or not the abnormality handling means is functioned can be freely changed.

  In the present invention, it is preferable that the predetermined function register is configured such that the data write operation is disabled after the data is once written. Further, it is preferable that the function designation and the monitoring time are defined by setting data written in the same function register. Here, the monitoring time is preferably set based on the frequency of the counting clock of the counting means built in the electronic element.

  Further, it is preferable to have a configuration in which the write operation to the RAM can be prohibited after the CPU is reset based on the abnormality handling means.

  Further, the present invention executes a lottery process caused by a predetermined switch signal, outputs a control command for specifying the lottery result, and performs an effect operation corresponding to the lottery result specified by the control command. The main control means includes a CPU that executes a control operation including a lottery process, a RAM that is appropriately accessed during the control operation, and a control program that defines the control operation. And a ROM for permanently storing the operation parameters necessary for the control operation, an abnormality handling means for resetting the CPU if no clear data is received until a predetermined monitoring time, and the operation inside the device. A function register capable of setting data to be defined, and a single electronic element with a built-in function. Whether written repeatedly clearing data, or, in particular a plurality of function registers, by writing the provisions of clear data cyclically, and is configured to reset the CPU is avoided.

  In the present invention, since the CPU reset avoidance method can be selected, the function of the abnormality handling means can be appropriately changed according to the desired security level for each model of the gaming machine, and the circuit needs to be changed. Absent.

  As described above, according to the present invention, it is possible to execute an appropriate control operation without wasting circuit space and with a highly versatile circuit configuration.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a circuit diagram which shows the internal circuit of a one-chip microcomputer. It is a block diagram which shows the memory map of a memory circuit, the flowchart which shows operation | movement of a management program, and the circuit structure inside a one-chip microcomputer. It is a circuit block diagram which shows the structure of an abnormality response circuit. It is a block diagram which shows the circuit structure of a WDT clear circuit. It is a flowchart explaining the main process of a main control part. It is a flowchart explaining the timer interruption process of a main control part.

  Examples of the present invention will be described in detail below. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side rather than from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. An upper plate 8 for storing game balls for launch is mounted on the front plate 7, and a lower plate 9 for storing game balls overflowing from or extracted from the upper plate 8 and a launch handle 10 are mounted at the bottom of the front frame 3. And are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, the game board 5 is provided with a guide rail 13 formed of a metal outer rail and an inner rail in an annular shape, and a liquid crystal color display DISP is provided at the approximate center of the game area 5a inside. Has been placed. In addition, at a suitable place in the game area 5a, a symbol start opening 15, a big winning opening 16, a plurality of normal winning openings 17 (four on the right and left of the large winning opening 16), and a gate 18 serving as a passing opening are arranged. Yes. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  The liquid crystal display DISP is a device that variably displays a specific symbol related to a big hit state and displays a background image and various characters in an animated manner. This liquid crystal display DISP has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. And, in the special symbol display parts Da to Dc, a reach effect is executed that expects a big hit state to be invited, or in the special symbol display parts Da to Dc and the surroundings, a notice effect that informs the result of the success or failure is executed Is done.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time, and the lottery extracted at the time when the game ball passes through the gate 18 is extracted. The stop symbol determined by the random number for use is displayed and stopped.

  For example, the symbol start opening 15 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws 15a, and when the stop symbol after fluctuation of the normal symbol display unit 19 is a winning symbol, the opening and closing claws are displayed. 15a is released only for a predetermined time or until a predetermined number of game balls are detected.

  When a game ball wins the symbol start port 15, the display symbols of the special symbol display portions Da to Dc change for a predetermined time and are determined based on the lottery result corresponding to the winning timing of the game ball to the symbol start port 15. Stop at the stop symbol. In addition, in special symbol display parts Da-Dc and its circumference, a notice effect may be performed between a series of symbol effects.

  The big winning opening 16 is controlled to open and close by, for example, an opening / closing plate 16a that can be opened forward, but when the stop symbol after the symbol change of the special symbol display portions Da to Dc is a big hit symbol such as “777”, the “big hit game” Is started, and the opening / closing plate 16a is opened.

  After the opening / closing plate 16a of the big prize opening 16 is opened, the opening / closing plate 16a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. In such an operation, the special game is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol of the special symbols, the game after the end of the special game is in a high probability state (hereinafter referred to as a probability variation state). The privilege is granted.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations. A dashed line in the figure mainly indicates a DC voltage line.

  As shown in the figure, this pachinko machine GM is provided with a power supply board 20 that receives AC 24V and outputs various DC voltages, system reset signals (power reset signals) SYS, and the like, and a main control board 21 that plays a central role in game control operations. And an effect control board 22 that executes a lamp effect and a sound effect based on the control command CMD received from the main control board 21, and an image that drives the liquid crystal display DISP based on the control command CMD ′ received from the effect control board 22. The control board 23, the payout control board 24 for controlling the payout motor M based on the control command CMD "received from the main control board 21 and paying out the game ball, and the game ball is fired in response to the player's operation. The launch control board 25 is mainly configured.

  However, in this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the command relay board 26 and the effect interface board 27. Further, the control command CMD ′ output from the effect control board 22 is transmitted to the image control board 23 via the effect interface board 27, and the control command CMD ″ output from the main control board 21 is the main board relay board. It is transmitted to the payout control board 24 via 28.

  The main control board 21, the effect control board 22, the image control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer. Thus, the circuits mounted on the control boards 21 to 24 and the operations realized by the circuits are collectively referred to as a function. In this specification, the main control unit 21, the effect control unit 22, and the image control unit 23 are used. , And the payout control unit 24. All or part of the effect control unit 22, the image control unit 23, and the payout control unit 24 is a sub-control unit.

  By the way, the pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and the new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member GM1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame-side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, and a frame relay board 32, and these circuit boards are Each is fixed in place on the front frame 3. On the other hand, a main control board 21, an effect control board 22, and an image control board 23 are fixed to the back of the game board 5 together with a liquid crystal display DISP and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place.

  The power supply board 20 is connected to the main board relay board 28 through the connection connector C2, and is connected to the power supply relay board 30 through the connection connector C3. The main board relay board 28 outputs the system reset signal SYS, the RAM clear signal DEL, the voltage drop signal ABN, the backup power supplies BAK, DC12V, and DC32V received from the power board 20 to the main controller 21 as they are. Similarly, the power relay board 30 also outputs the system reset signal SYS received from the power board 20 and the AC and DC power supply voltages to the effect interface board 27 as they are. The production interface board 27 outputs the received system reset signal SYS to the production control unit 22 and the image control unit 23 as they are.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and the system reset signal SYS, the RAM clear signal DEL, the voltage drop signal ABN, the backup, which are received by the main control unit 21. The power supply BAK is directly received together with other power supply voltages.

  Here, the system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V is turned on to the power supply board 20, and the one-chip microcomputers of the respective control units 21 to 24 by this power supply reset signal. The other IC elements are reset in power supply.

  The RAM clear signal DEL received from the power supply board 20 by the main control unit 21 and the payout control unit 24 is a signal that determines whether or not to initialize all areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. Therefore, it has a value corresponding to the ON / OFF state of the initialization switch SWT operated by the attendant.

  The voltage drop signal ABN received from the power supply board 20 by the main control unit 21 and the payout control unit 24 is a signal indicating that the AC power supply 24V has started to drop. By receiving this voltage drop signal ABN, each control unit In 21 and 24, necessary end processing is started prior to a power failure or business end. The backup power supply BAK is a DC5V DC power source that retains data in the RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 24 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  On the other hand, the effect control unit 22 and the image control unit 23 are not provided with the power supply backup function described above. However, as described above, the production control unit 22 and the image control unit 23 are commonly supplied with the system reset signal SYS via the power relay board 30 and the production interface board 27. A power supply reset operation is realized at a timing substantially synchronized with the control units 21 and 24.

  As illustrated, the main control unit 21 transmits a control command CMD "to the payout control unit 24 via the main board relay board 28, while the payout control unit 24 receives a prize ball indicating a payout operation of the game ball. A count signal and a status signal CON relating to an abnormality in the payout operation are received, and the status signal CON includes, for example, a replenishment out signal, a payout shortage error signal, and a lower plate full signal.

  The main control unit 21 is connected to each game component of the game board 5 via the game board relay board 29. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The switch signal includes a winning switch signal SG transmitted from the symbol start port 15 to the main control unit 21.

  FIG. 4 illustrates a part of the internal configuration of the one-chip microcomputer 21 </ b> A of the main control unit 21. Here, a portion including a winning switch signal SG received from the detection switch of the symbol start port 15 via the game board relay board 29 is shown.

  As illustrated, the one-chip microcomputer 21A includes a CPU core equivalent to Z80CPU (Zilog), a counter timer circuit CTC equivalent to Z80CTC (counter timer circuit), a ROM and RAM memory circuit, and a setting register described later. Various function registers RT1 to RTn, an operation start circuit START that appropriately defines the execution operation start timing of the control program (user program) stored in the ROM, and an abnormality response circuit REV that resets the CPU core during an abnormal operation A random number generation circuit GNR that generates a random number value RND for lottery and an input port INP are mainly incorporated.

  The winning switch signal SG from the symbol start port 15 is supplied to the random number generation circuit GNR of the one-chip microcomputer 21A and the input port INP via the buffer circuit BUF arranged on the game board relay board 29. Yes. The input port INP is supplied not only with the symbol start port 15 but also with a switch signal from the big winning port 16 and the detection switch of the gate 18.

  The buffer circuit BUF of the game board relay board 29 has an open collector type output section, the input side is pulled up to 12V, and the output side is pulled up to 5V. When the game ball passes through the symbol start port 15 and enters a winning state, the buffer circuit BUF outputs a winning switch signal SG as a positive logic ON signal.

  The random number generation circuit GNR includes a counter CNT that circulates in a predetermined numerical range, and a latch circuit LT that holds the counter value of the counter CNT as a random value RND in synchronization with a changing edge at which the winning switch signal SG changes. Configured.

  As shown in the figure, the winning switch signal SG is also supplied to the input port INP so as to overlap the random number generation circuit GNR. Therefore, the CPU core can grasp the changing edge of the winning switch signal SG based on the input data from the input port INP. After this grasping, the CPU core obtains the random value RND from the latch circuit LT and performs the big hit lottery. It is supposed to run.

  FIG. 5A illustrates a memory map for the memory circuit (RAM + ROM) and various function registers RT1 to RTn of the one-chip microcomputer 21A. As shown in the figure, in this embodiment, the control program created by the gaming machine manufacturer and the fixed value data referred to by this control program are stored, for example, after address 8000H.

  In addition to the fixed value data, a parameter area capable of storing operation parameters transferred to the function register RTi when the CPU is reset is also secured in the ROM. Here, the operation parameter includes a set value that defines a waiting time until the control program starts to function.

  By the way, in this type of gaming machine, the capacity of control programs and fixed value data is strictly limited (for example, about 3 Kbytes each) due to legal restrictions, and security processing is included with this limited storage capacity. It is necessary to realize advanced processing. Therefore, in this embodiment, the function register RTi is effectively used to suppress the program amount of the control program and improve the security level (details will be described later).

  Further, the one-chip microcomputer 21A of the present embodiment is configured such that the management program is executed after the CPU reset and before the control program after the address 8000H is executed. Here, the management program is a kind of microprogram created by a chip manufacturer, and the specific operation content is as shown in FIG. 5B, for example.

  As shown in the figure, after the CPU is reset, the operation parameters stored in the ROM are transferred to the corresponding function register RTi (SS1). As described above, the operation parameter includes setting value data that defines the waiting time until the control program starts to function, and this setting value data is stored in the waiting time setting register 60 (see FIG. 5 (c)).

  Further, 50 is written in the frequency division ratio setting register 52 as a frequency division ratio default value, and the default value 0 is maintained as control data for stopping the function of the watchdog timer 54. Therefore, no matter how long the subsequent waiting process (SS3) is prolonged, there is no possibility that the CPU core is reset by the overflow signal OV of the watchdog timer 54.

  Next, a self-diagnosis process for confirming the normal operation of the one-chip microcomputer including a determination process for determining the validity of the security key is executed (SS2). Thereafter, the control program waits for the operation start of the control program until the operation start timing defined by the operation parameter (standby time) transferred to the setting register 60 in the process of step SS1 (SS3). The operation of the control program after the address is started.

  Therefore, according to the present embodiment, it is not necessary to implement standby processing that waits for several seconds to several tens of seconds until the initial operation of the sub-control unit is completed, and a limited memory area is effectively created. Can be used. For example, in a CPU core that operates with a system clock of 20 MHz, in order to realize standby processing that consumes several tens of seconds, a certain amount of program capacity is consumed. Therefore, the effect of this embodiment that can eliminate this standby processing is required. Is big.

  FIG. 5C is a circuit block diagram showing the circuit configuration of the operation start circuit START and the abnormality handling circuit REV that realize the above operation. In this embodiment, a 20 MHz system clock Φ is supplied to the prescaler 50, and the reception circuit 53 and the WDT clear circuit are configured to be directly accessible from the CPU core (see FIG. 6A). The output of the reset circuit 56 is supplied to the reset terminal of the CPU core and the control register 57 as the function register RTi. The control register 57 is specifically realized by the RS flip-flop 57 of FIG.

  Continuing the description based on the above, the abnormality handling circuit REV sets the prescaler 50 that divides the pulse period of the system clock Φ to a fixed number (N) times, and the output pulse period of the prescaler 50 to an arbitrary multiple (X). A programmable postscaler 51 that divides the frequency, a setting register 52 that stores a division ratio of the postscaler 51 and other operation parameters, a reception circuit 53 that receives an operation parameter to be set in the setting register 52 from the CPU core, A watchdog timer 54 that counts the output of the scaler 51 within a predetermined numerical range, a WDT clear circuit 55 that forcibly returns the counter value of the watchdog timer 54 to an initial value, and the count value of the watchdog timer 54 is a predetermined numerical value. Upon receiving the overflow signal OV indicating that the range has been completed, the CPU reset It is configured to include a reset circuit 56 for outputting a signal.

  As described above, in the setting register 52 as the function register RTi, the division ratio 50 is written as a default value at the timing of step SS1, and thereafter, an arbitrary division ratio of 10 to 1270 is set by the control program. It is configured to be configurable. Therefore, the cycle of the count clock supplied to the watchdog timer 54 can be arbitrarily set by the gaming machine manufacturer, and the output cycle of the overflow signal OV can be set appropriately.

  In the setting register 52, operation parameters (control data) that define whether or not the reset circuit 56 is to be functioned can be arbitrarily set by a control program. Therefore, it is possible for the gaming machine manufacturer to prohibit the operation of the abnormality handling circuit REV. Even if the operation of the abnormality handling circuit REV is prohibited, the operation of the operation start circuit START is not affected.

  By the way, the output of the reset circuit 56 is supplied to the reset terminal of the CPU core, so that the CPU core is forcibly reset. Further, the output of the reset circuit 56 is stored in the control register 57, so that access to the RAM is partially prohibited after the CPU core is forcibly reset. The prohibition state is set as appropriate. In this embodiment, the RAM read operation is permitted, but the write operation is prohibited.

  The system clock Φ is 20 MHz in this embodiment, and the frequency division ratio of the prescaler 50 is 2000. Therefore, the pulse period of the output pulse of the prescaler 50 is 100 μS. The frequency division ratio set in the setting register 52 via the reception circuit 53 is in the numerical range of 10 to 1270, but the default frequency division ratio after power-on is 50 (SS1).

  Therefore, the pulse period of the output pulse of the postscaler 51 is 5 mS (= 50 × 100 μS) as a default value. Based on the setting value (10 to 1270) by the subsequent control program, the pulse period in the range of 1 mS to 127 mS Become.

  In this embodiment, the watchdog timer 54 is a decimal counter, and is configured to output an overflow signal OV every time a numerical value range of 0 to 99 is made. The pulse width of the output pulse of the postscaler 51 has a default value of 5 mS, and thereafter becomes any value from 1 mS to 127 mS based on the setting by the control program. Therefore, the output cycle T of the overflow signal OV output from the watchdog timer 54 has a default value T0 of 500 mS (= 5 mS × 100), and thereafter becomes a set value Ts within a range of 100 mS to 12.7 S. .

  Since the overflow signal OV becomes a CPU reset signal via the reset circuit 56, the CPU core is repeatedly reset at the output cycle Ts of the overflow signal OV unless the WDT clear circuit 55 functions. . Although the operation of the reset circuit 56 can be prohibited based on the initial setting value of the setting register 52, the watchdog timer function once permitted cannot be prohibited during the game operation. Therefore, for example, in order to operate an illegal program intermittently, an illegal operation that appropriately prohibits the watchdog timer function is impossible.

  Next, the circuit configuration of the operation start circuit START will be described with reference to FIG. In the illustrated operation start circuit START, the setting register 60 is transferred with the set value data (standby time) registered in the parameter area of the ROM by the process of step SS1, and the determination register 63 is directly accessible from the CPU. It is configured.

  To explain the above, the operation start circuit START sets the setting register 60 that receives the waiting time stored in the ROM, the counter 61 that receives the overflow signal OV of the watchdog timer 54, and the counter value of the counter 61. The comparison circuit 62 is configured to determine whether or not they match with the set value of the register 60, and the determination register 63 that stores a match signal output from the comparison circuit 62.

  The coincidence signal output from the comparison circuit 62 is ON level when coincidence is determined, and is OFF level otherwise. Then, the output value (match signal) of the determination register 63 is repeatedly determined in the process of step SS3 of the management program (see FIG. 5B), and the standby process is repeated until the output value becomes ON level.

  On the other hand, since the output period T0 of the overflow signal OV is the default value of 500 mS at this timing, according to the present embodiment, the setting value of the setting register 60 is set to 2, 4, 6,. By setting 50 and 60, it is possible to secure a waiting time of 1 second, 2 seconds, 3 seconds,..., 25 seconds, and 30 seconds.

  In this way, in this embodiment, by registering appropriate set value data (standby time) in the parameter area of the ROM, the optimum standby time until the sub-control unit starts up reliably after the CPU reset is set. Can be secured. The advantage of not consuming the control program area for this standby process is as described above.

  FIG. 6A is a circuit block diagram showing a specific circuit configuration of the abnormality handling circuit REV. As shown in the figure, the receiving circuit 53 includes an input register 70 into which the CPU core writes setting value data, a frequency division ratio control register 71 for storing the output value of the input register 70, and a frequency division ratio control register 71. A coincidence determination circuit 72 that compares an output value with an input value to the input register 70 and an RS flip-flop 73 that receives the output value of the coincidence determination circuit 72 at an S input terminal are configured.

  Here, like the frequency division ratio setting register 52 and the input register 91, the input register 70 and the frequency division ratio control register 71 are reset when the power is turned on, and their output values are cleared. The frequency division ratio setting register 52 is set to the default value (= frequency division ratio 50) immediately after resetting the power supply, but the circuit configuration related to this is not shown.

  When the output value of the frequency division ratio control register 71 matches the input value of the input register 70, the coincidence determination circuit 72 sets the L level on condition that the control terminal OE (output enable) is at the H level. The determination value is output at other times, and the determination value at the H level is output at other timings. The circuit configuration of the coincidence determination circuit 72 is basically the same as that of the subtraction circuit and gate circuit shown in FIG. The determination output of the coincidence determination circuit 72 is supplied to the clock terminal CK of the frequency division ratio setting register 52.

  The output of the division ratio control register 71 is commonly supplied to the input terminals of the coincidence determination circuit 72 and the division ratio setting register 52. Here, the frequency division ratio setting register 52 is configured to latch the signal at the input terminal when an L level signal is received at the clock terminal CK. Therefore, the output value of the frequency division ratio control register 71 is stored in the frequency division ratio setting register 52 at the timing when the output value of the frequency division ratio control register 71 matches the input value of the input register 70. .

  By the way, the R input terminal of the RS flip-flop 73 that receives the output of the coincidence determination circuit 72 is fixed at the H level. The Q bar output terminal is supplied to the input terminal of the AND gate 74 via a delay circuit using a NOT gate. When the power is turned on, the RS flip-flop 73 receives the power reset signal from the clear terminal CLR and resets the power, so that the subsequent Q bar output terminal is at the H level.

  The input register 70 and the division ratio control register 71 latch data (setting value data) on the data bus based on a chip select signal CS (L active) generated based on an address signal output from the CPU core. It is configured to However, the input register 70 latches the set value data at the falling edge of the chip select signal CS, and the frequency division ratio control register 71 sets the set value data at the rising edge of the chip select signal CS "appropriately delayed. Is configured to latch.

  On the other hand, the logically inverted chip select signal CS ′ is supplied to the input terminal of the AND gate 74. As described above, the input terminal on the other side of the AND gate 74 maintains the H level after the power reset, so that the logic-inverted chip select signal CS ′ remains at that level and controls the coincidence determination circuit 74. It is supplied to the terminal OE.

  Here, the control terminal OE (output enable) has a function of controlling the output operation of the coincidence determination circuit 72, and at the timing when the chip select signal CS returns to the steady level (H), the inverted chip select signal CS. As a result, the output of the coincidence determination circuit 72 returns to the steady level (H) in response to the change of the inverted chip select signal CS ′.

  After that, even if the data value of the data bus of the CPU core happens to coincide with the output value of the frequency division ratio control register 71, the output value of the coincidence determination circuit 72 does not change to the L level. For this reason, the setting value once set in the frequency division ratio setting register 52 does not change thereafter, and therefore the operating condition of the watchdog timer 54 such as the output cycle Ts of the overflow signal OV does not change. Further, in order to operate the illegal program as intended, such an operation is impossible even if the output period Ts of the overflow signal OV is set to be longer or an attempt is made to prohibit the watchdog timer function afterwards.

  Based on the above circuit operation, the setting value data write operation by the CPU core will be described with reference to FIG. Here, the set value data X is configured to include frequency division ratio data of the postscaler circuit 51 and control data defining whether or not the watchdog timer 54 is operable.

  As shown in FIG. 6B, the CPU core writes the set value data X to the input register 70 (ST30), and then writes the same set value data X to the input register 70 again (ST31). The set value data X is latched (stored) in the input register 70 at the falling edge of the chip select signal CS in the first write operation, and the set value data X latched in the input register 70 is in a delayed state. It is latched in the frequency division ratio control register 71 at the rising edge of the chip select signal CS ″.

  At the timing of step ST30, since the Q bar output of the RS flip-flop 73 is at the H level, the logically inverted active level chip select signal CS 'is applied to the control terminal OE of the coincidence determination circuit 72. However, at the timing when the chip select signal CS ′ is maintained at the active level, the set value data X supplied from the CPU core does not match the output value of the frequency division ratio control register 71 that is cleared after the power is turned on. Therefore, the output of the coincidence determination circuit 72 remains at the H level without changing.

  Thereafter, when the same set value data X is written to the input register 70 again (ST31), the two types of data supplied to the coincidence determination circuit 72 coincide with each other at the falling timing of the chip select signal CS at that time. Become. That is, the set value data X output for the first time is output from the frequency division ratio control register 71, and the second set value data X is output from the CPU core.

  Thus, in this embodiment, as long as the normal setting process (ST30, ST31) is executed, the two types of data match in the second write process (ST31), so the output of the match determination circuit 72 is L level. In synchronization with the falling edge, the frequency division ratio setting register 52 stores the set value data X output for the first time. Based on this set value data X, the frequency division ratio of the postscaler circuit 51 is set.

  When the output of the coincidence determination circuit 72 changes to the L level, the RS flip-flop 73 performs a setting operation based on the S terminal input at the L level (see FIG. 6C). As a result, the Q bar output of the RS flip-flop 73 changes to the L level, and this change is transmitted to the AND gate 74 after a predetermined delay time, so that the control terminal OE of the coincidence determination circuit 72 is thereafter set to the L level. Thus, the output of the coincidence determination circuit 72 also returns to the steady H level.

  Therefore, the Q bar output of the RS flip-flop 73 is maintained at the L level thereafter (see FIG. 6C), and the coincidence determination circuit 72 does not function thereafter. That is, in the present embodiment, the setting process of the frequency division ratio of the postscaler 51 is limited to one time and cannot be reset after that, which is also significant in terms of security. This point is as described above.

  By the way, the set value data X includes not only the frequency division ratio data of the postscaler circuit 51 but also control data defining whether or not the watchdog timer 54 is operable. The control data is set at the H level when the function of the watchdog timer 54 is used, and is set at the L level when the function is not used. However, it is confirmed from the circuit configuration of FIG. 6 described above that the watchdog timer function that has started the operation based on the H level control data cannot be prohibited thereafter. It is also effective for security.

  As shown in the figure, since the control data stored in the frequency division ratio setting register 52 is supplied to the input terminal of the NAND gate 56 as it is, the overflow signal output from the watchdog timer 54 when the control data = L. Without the OV being supplied to the CPU, the watchdog timer 54 is effectively disabled.

  On the other hand, when the control data = H, the overflow signal OV output from the watchdog timer 54 is supplied to the CPU to reset the CPU core. The overflow signal OV is also supplied to the S input terminal of the RS flip-flop 57. Since the R input terminal is fixed at the H level, after the overflow state occurs in the watchdog timer 54 and the CPU core is abnormally reset, the Q bar output of the RS flip-flop 57 maintains the L level. It will be.

  As shown, the Q bar output of the RS flip-flop 57 is supplied to the input terminal of the AND gate 58. The other input terminal of the AND gate 58 is supplied with a memory WR signal output to the control bus of the CPU core. Here, the memory WR signal is a signal supplied to the RAM at the time of the RAM read operation, and the supply of the memory WR signal to the memory is blocked by the AND gate 58, so that the CPU core After the abnormal reset, the RAM write operation is prohibited.

  This operation is also effective in terms of security. For example, if the CPU is intentionally reset, then the RAM cannot be rewritten, and subsequent illegal actions are impossible.

  Next, the circuit configuration of the WDT clear circuit 55 located in the upper part of FIG. 6 will be described. As shown in the figure, the WDT clear circuit 55 controls the operation order of the input register 91 for receiving and storing clear data from the CPU core, the keyword register 92 for permanently storing the clear processing keyword, the input register 91, and the like. And a match determination circuit 90 that determines whether or not the stored values of the input register 91 and the keyword register 92 match. The input register 91 and the keyword register 92 constitute a part of the function register RTi, and each is assigned a unique address number (see FIG. 5A).

  Further, when the stored value of the input register 91 and the stored value of the keyword register 92 match, an L level clear signal is output from the match determination circuit 90 and is supplied to the watchdog timer 54. The counter value of the watchdog timer 54 is cleared to zero to prevent the overflow signal OV from being output.

  FIG. 7 shows the circuit configuration of the input register 91, the keyword register 92, the operation sequence circuit 93, and the coincidence determination circuit 90 in more detail. As shown, the input register 91 is actually composed of four 8-bit length registers R0 to R3, and addresses (port numbers) N0 to N3 are assigned to the registers. The keyword register 92 is also composed of four 8-bit length registers R0 ′ to R3 ′, and each has the same address (port number) N0 to N3 as the corresponding input registers R0 to R3. .

  Here, the input terminals of the 8-bit length registers R0 to R3 are connected to the data bus of the CPU core, and clear data output from the CPU core on condition that the chip select signals CS0 to CS3 for selecting itself are received. Is stored and output. Of course, the chip select signals CS0 to CS3 are unique signals generated based on the port numbers N0 to N3.

  The input terminals of the 8-bit keyword registers R0 'to R3' are fixedly set to H level or L level, and each of the registers R0 'to R3' has a chip select signal CS0 to CS0 for selecting itself. It is configured to store and output a unique keyword on condition that CS3 is received. Although not limited in any way, the register R0 'stores 10H, the register R1' stores 22H, the register R2 'stores 33H, and the register R3' stores 44H.

  In this embodiment, the four input registers R0 to R3 and the four keyword registers R0 ′ to R3 ′ have a one-to-one correspondence, and the pair of registers Ri and Ri ′ are selected by the same chip select signal CSi. It is configured to be. Therefore, for example, when clear data is output from the CPU core to the address N0 (input register R0), the clear data is acquired and output to the input register R0, while the fixed keyword 10H is output from the register R0 ′. Will be.

  In this embodiment, a basic operation mode in which the watchdog timer 54 is cleared using a pair of registers R0 and R0 ′, and a watchdog using three pairs of registers R1, R1 ′ to R3 and R3 ′ in a cyclic manner. A circulation operation mode for clearing the timer 54 can be selected. The operation sequence circuit 93 functions in the case of adopting a cyclic operation mode, and controls the operation sequence of the three pairs of registers R1, R1 'to R3, R3'.

  Specifically, based on a start pulse output on the condition that a predetermined function register RTi is instructed to adopt a cyclic operation mode, first, the first register pair R1, R1 ′ becomes operable, The second register pair R2, R2 ′ is operable on the condition that one register pair R1, R1 ′ is operated, and the third register pair R3, R3 ′ is operated on the condition that the second register pair R2, R2 ′ is operated. On the condition that R3 ′ is operable and the third register pair R3, R3 ′ is operated, a circular operation is realized such that the first register pair R1, R1 ′ is operable.

  A specific circuit configuration is as shown in FIG. 7, and a positive logic AND receiving three negative logic AND gates G1 to G3, three RS flip-flops F1 to F3, a start pulse and a chip select signal CS3. And a gate G0. Here, the RS flip-flops F1 to F3 are configured to perform a reset operation or a set operation at the rising edge of the chip select signal supplied to the reset terminal R or the set terminal S.

  The chip select signals CS1 to CS3 are constantly at the H level, and become the L level only at the timing of writing the clear data to the input registers R1 to R3 (port numbers N1 to N3). In addition, the RS flip-flops F1 to F3 are reset when the power is turned on, and each Q bar output becomes H level.

  As shown in the figure, the AND gate G1 receives the chip select signal CS1 and the Q bar output of the flip-flop F3 at its input terminals. The AND output that has been subjected to negative logic operation is supplied to the chip enable terminals of the first register pair R1, R1 '. The same applies to the AND gate G2, and the chip select signal CS2 and the Q-bar output of the flip-flop F1 are received at the input terminal, and the AND output subjected to the negative logic operation is applied to the chip enable terminals of the second register pair R2, R2 ′. Supply. The AND gate G3 receives the chip select signal CS3 and the Q-bar output of the flip-flop F2 at its input terminals, and supplies an AND output that has been subjected to negative logic operation to the chip enable terminals of the third register pair R3, R3 ′. doing.

  On the other hand, the flip-flop F1 operates by receiving the chip select signal CS1 at the set terminal S and the chip select signal CS2 at the reset terminal R. Therefore, the Q bar output of the flip-flop F1 becomes H level after the power is reset, then becomes L level based on the chip select signal CS1, and returns to H level based on the chip select signal CS2.

  The other flip-flops are substantially the same, and the flip-flop F2 receives the chip select signal CS2 at the set terminal S and receives the chip select signal CS3 at the reset terminal R. After that, it becomes L level based on the chip select signal CS2, and returns to H level based on the chip select signal CS3.

  On the other hand, the flip-flop F3 is configured to receive the output of the AND gate G0 at the set terminal S and the chip select signal CS1 at the reset terminal R. The AND gate G0 receives the chip select signal CS3 and the start pulse at the input terminals. For this reason, the Q bar output of the flip-flop F3 becomes H level after the power is reset and then becomes L level based on the start pulse or the chip select signal CS3, and returns to H level based on the chip select signal CS1. Become.

  Since the operation sequence circuit 93 of the embodiment is configured as described above, it operates as follows. First, since the flip-flops F1 to F3 are in a reset state after the power is turned on, all the Q bar outputs are at the H level and the input terminals on one side of the AND gates G1 to G3 are at the H level. Therefore, even if the CPU core designates predetermined port numbers N1 to N3 and outputs clear data, the chip select signal CSi is not transmitted and all data output operations are ignored.

  On the other hand, when a start pulse is output in such a state, the flip-flop F3 is set, and the input terminal on one side of the AND gate G1 changes to L level. Therefore, thereafter, only when the port number N1 is specified and the clear data is output to the input register R1, the clear data is acquired by the input register R1 based on the chip select signal CS1.

  At the rising timing of the chip select signal CS1, the flip-flop F3 is reset while the flip-flop F1 is set. When the flip-flop F3 is reset, one of the input terminals of the AND gate G1 becomes H level, and thereafter the chip select signal CS1 cannot pass through the AND gate G1, in other words, to the subsequent register R1. Writing is prohibited.

  On the other hand, since the flip-flop F1 is set at the rising timing of the chip select signal CS1, one of the input terminals of the AND gate G2 changes to L level at that timing, and thereafter, the chip select signal CS2 is changed to the AND gate G2. Will be able to pass through. That is, thereafter, only writing to the register R2 is permitted.

  Therefore, after that, when the port number N2 is designated and clear data is output to the input register R2, the clear data is acquired in the input register R2 based on the chip select signal CS2. In response to this operation, the flip-flop F1 is reset and the flip-flop F2 is set. Therefore, thereafter, the chip select signal CS2 cannot pass through the AND gate G2, and writing to the register R2 is prohibited, while the chip select signal CS3 can pass through the AND gate G3.

  The same applies to the following, and thereafter, when the port number N3 is designated and clear data is output to the input register R3, the clear data is acquired in the input register R3 based on the chip select signal CS3. In response to this operation, the flip-flop F2 is reset and the flip-flop F3 is set. Therefore, thereafter, writing to the register R3 is prohibited, while the chip select signal CS1 can pass through the AND gate G1, and only writing to the register R1 is permitted.

  As described above, in this embodiment, the operation sequence circuit 93 functions so that after the start pulse is output, the input register R1, the input register R2, the input register R3, the input register R1, and so on in this order. Only when clear data can be output, the WDT clear circuit 55 cannot generate a clear signal, and the CPU core is reset. Even if the operation order is correct, as described below, if the clear data is incorrect, the CPU core is reset.

  The coincidence determination circuit 90 receives an output value from the pair of registers Ri and Ri ′ and executes a subtraction process, and receives an output bit (8 bits in the embodiment) of the subtraction circuit and executes an OR operation. A NOR gate 82, a NAND gate 81 that receives four chip select signals CS0 to CS3 and executes an AND operation, and a NAND gate 83 that receives the outputs of the NAND gate 81 and the NOR gate 82 and executes an AND operation. It is configured. Note that the output of the NAND gate 83 becomes an L active clear signal CLR supplied to the watchdog timer 54.

  Here, when the output values from the pair of registers Ri and Ri 'match, the subtraction circuit 80 outputs an 8-bit length zero as the subtraction result. Since the output value of the NOR gate 82 is H level only when all the input values are zero, the NOR gate 82 is finally only when the output values from the pair of registers Ri and Ri ′ match. The output value of the gate 82 becomes H level.

  The NAND gate 81 outputs an H level when any of the four chip select signals CS0 to CS3 is at an L level, and maintains the L level otherwise. Therefore, the output of the NAND gate 83 is at the L level only when the output values from the pair of registers Ri and Ri ′ match and the corresponding chip select signal CSi is at the L level. Becomes a clear signal CLR for clearing the watchdog timer 54 to zero.

  By the way, in this embodiment, in order to clear the watchdog timer 54, it is possible to select whether to always use the same clear data or to use different (three) different clear data. Here, the same clear data is specifically 10H, and the different clear data is, for example, 22H, 33H, and 44H.

  When different clear data is used, 22H is output to the input register R1 to clear the watchdog timer 54, and after a predetermined time, 33H is output to the input register R2 to output the watchdog. The second clearing process for clearing the timer 54 and the third clearing process for outputting 44H to the input register R3 and clearing the watchdog timer 54 after a predetermined time are cyclically repeated. Therefore, the address data of the input register Ri and the keyword to be written to the input register Ri are stored in the fixed data area of the ROM (see FIG. 7B). Note that these clear processes will be further described with reference to FIG.

  FIGS. 8 and 9 are flowcharts showing the control program of the main control unit 21. The system reset process (FIG. 8) is started based on the restoration or turning on of the power supply voltage, and is started every predetermined time (2 mS). And maskable timer interrupt processing (FIG. 9).

  Hereinafter, the system reset processing program (main processing) will be described with reference to FIG. The main process is started when the initialization switch SWT is OFF and the power is turned ON, such as when recovering from a power failure, and when the game hall is opened, the initialization switch SWT is ON. There is a case where the power source is turned on by being operated. Note that the abnormality handling circuit REV may be activated to forcibly reset the CPU.

  In any case, when the CPU core is reset, the management program shown in FIG. 5B starts operating (ST1). Then, the operation parameter registered in the parameter area of the ROM is transferred to the corresponding function register RTi (SS1). As described above, the function register RTi includes the standby time setting register 60 shown in FIG. 5, but in this embodiment, a sufficient standby time (for example, 10 seconds) is required until all the sub-control units start up. In order to ensure this, an operation parameter having a predetermined value (for example, 20) is registered in the parameter area of the ROM, and this operation parameter is set in the setting register 60 in the process of step SS1.

  Next, when the self-diagnosis process and the security process are finished (SS2), the value of the determination register 63 is repeatedly checked by the process of the management program (SS3). As described with reference to FIG. 5C, at this timing, the pulse period of the overflow signal OV is 500 ms, so the counter 61 increments and updates the counter value every 500 ms.

  The counter value of the counter 61 is compared with the stored value (20) of the setting register 60 in the comparison circuit 62. Then, at the timing when the counter value reaches 20 after 10 seconds have elapsed since the power of the counter 61 is reset, the value of the determination register 63 is first turned to the ON level. Will be secured.

  In this way, in this embodiment, standby processing that consumes a desired time can be executed without using any control program (user program), and therefore, waste of the storage area of the ROM can be prevented. This point is as described above.

  In this way, when the necessary standby processing is completed, the user program after address 8000H is started, and the Z80 CPU first initializes the value of the stack pointer SP in the CPU corresponding to the final address of the stack area. (ST2).

  Next, the values of various function registers RTi including the input register 70 of FIG. 6 are initialized (ST3). As described with reference to FIG. 6, the same set value data X needs to be set twice in the input register 70 (ST30 + ST31). Here, the set value data X includes the frequency division ratio data of the post-scaler circuit 51 and control data defining whether or not the watchdog timer 54 is operable. In this embodiment, the control data = 1. Utilize the watchdog timer function.

  Further, the frequency division ratio N of the postscaler circuit 51 is determined based on the standard processing time T0 (see FIG. 8) from the process of step ST4 to step ST16 in which the interrupt is permitted, and the WDT clear process (ST21) in the timer interrupt process. Is defined on the basis of the total (T0 + T1) with the elapsed time T1 (see FIG. 9).

  That is, in this embodiment, the output pulse period of the postscaler 51 has a relationship of 100 μS × frequency division ratio (N), and the output period T of the overflow signal OV output from the watchdog timer 54 is the output of the postscaler 51. Since it is 100 times the pulse period, the frequency division ratio N is defined by the condition of 100 μS × N × 100> T0 + T1.

  In the above equation, 100 μS is determined by the frequency (20 MHz) of the system clock Φ and the frequency division ratio (2000) of the prescaler 50, and the magnification 100 is determined based on the fact that the watchdog timer 54 is composed of a decimal counter. Therefore, it goes without saying that the frequency division ratio changes if the configuration of each circuit changes. However, in any case, the output period T of the overflow signal OV, in other words, the timeout time T until the watchdog timer 54 times out is set to T> T0 + T1.

  Here, the standard processing time T0 from the processing in step ST4 to step ST16 in which the interrupt is permitted becomes a problem, but the processing for determining the voltage drop signal ABN (ST4 to ST5) is usually completed at once. In this embodiment, the standard processing time T0 is calculated with reference to the case where the processing of steps ST4 to ST5 is executed twice with a margin.

  When the initial setting process (ST3) as described above is completed, the voltage drop signal ABN is acquired from the input port INP (ST4), and after confirming that this is a normal level (ST5), the RAM is cleared from the input port INP. The signal DEL is acquired (ST6). The RAM clear signal DEL is a signal for determining whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer 21A, and has a value corresponding to the ON / OFF state of the initialization switch SWT operated by the staff. Have.

  Next, the level of the RAM clear signal DEL is determined (ST7). If it is assumed that the RAM clear signal DEL is in the ON state, the entire area of the built-in RAM is cleared to zero (ST11). Next, a power-on command for notifying that the RAM area has been cleared to zero is output (ST12).

  Next, the CTC that outputs the interrupt signal INT for starting the timer interrupt operation (FIG. 9) is initialized (ST13). Then, with the CPU set to the interrupt disabled state (ST14), update processing is executed for various counters (ST15), and then the CPU is returned to the interrupt enabled state (ST16) and the process returns to step ST14. The counter updated in step ST15 is used, for example, for lottery of a stop symbol.

  Returning to the determination processing in step ST7, the RAM clear signal DEL is in the OFF state when the CPU core is forcibly reset by the abnormality handling circuit REV or when the CPU core is restored from the power failure state. In such a case, following the determination in step ST7, the content of the backup flag BFL is determined (ST8). The backup flag BFL is data indicating that the backup process has been executed in the power supply monitoring process (ST20). In this embodiment, the backup flag BFL is set to 5AH when the power is shut off, and the process of step ST20 after the power is restored. Is cleared to zero.

  Therefore, when the power is turned on or when recovering from the power failure state, the content of the backup flag BFL is 5AH. However, if the program goes out of control for some reason and a CPU reset operation occurs due to the operation of the abnormality handling circuit REV, the backup flag BFL = 00H. Therefore, when BFL ≠ 5AH (normally BFL = 00H), the process proceeds from step ST8 to step ST11 to return the operation of the gaming machine to the initial state.

  On the other hand, if backup flag BFL = 5AH, checksum calculation for calculating the checksum value is executed (ST9). Here, the checksum operation is an 8-bit addition operation for the work area of the built-in RAM. When the checksum value is calculated, the calculation result is compared with the stored value at the SUM address in the RAM (ST10).

  In the SUM address, a checksum value obtained by the same checksum calculation is stored in the power supply monitoring process (ST20) executed when the voltage drops. The stored calculation result is maintained by a backup power source together with other data of the built-in RAM. Therefore, the two should be matched by the determination in step ST7.

  However, if the checksum calculation cannot be executed when the power is turned off, or if the data in the work area is damaged after the execution of the checksum calculation (ST9) of the main process, even if it can be executed In such a case, the determination result in step ST10 is inconsistent.

  Therefore, if data corruption is detected due to a discrepancy in the determination results, the process proceeds to step ST11, RAM clear processing is executed, and the operation of the gaming machine is returned to the initial state. On the other hand, if it is determined in step ST10 that the checksum value obtained by the checksum calculation (ST9) matches the stored value at the SUM address, the process proceeds to step ST13 described above.

  Next, a timer interrupt processing program (FIG. 9) started every 2 mS with the main processing described above being interrupted will be described. When the timer interrupt occurs, the power supply monitoring process is immediately executed without saving the CPU register (ST20). This is because the timing at which the timer interrupt process is started is fixed immediately after step ST16.

  In the power supply monitoring process (ST20), the level of the voltage drop signal ABN supplied from the power supply board 20 is determined. If the level is abnormal, the backup flag BFL is set to 5AH, the checksum value is calculated, and the SUM After memorizing the address, wait for the power to be cut off.

  When such a power supply monitoring process (ST20) is completed, a WDT clear process for clearing the watchdog timer 54 of the abnormality handling circuit REV built in the one-chip microcomputer is executed (ST21). There are two types of WDT clear processing (ST21), one of which is executed.

  First, the WDT clear process with a simple configuration is as shown in FIG. 9B. Of the input register 91 shown in FIG. 7, in particular, the clear data 10H which is a prescribed value is input to the input register R0 of the port number N0. Write (ST40). As a result, zero, which is coincidence data, is output from the subtraction circuit 80 (FIG. 7), and an active level clear signal CLR signal is output from the NAND gate 83. Since the watchdog timer 54 is cleared to zero by the clear signal CLR, the overflow signal OV is prevented from being output and the CPU core is prevented from being reset.

  Although the WDT clear process as described above is sufficient, it is preferable to adopt the configuration of FIG. 9C in order to increase the security level. When this high-level configuration is adopted, it is preferable to store a port number and a keyword in advance in the fixed value data area of the ROM and to use a pointer PT that performs a cyclic operation. Note that FIG. 9C generally describes the same items as FIG. 7B.

  The processing content of FIG. 9C will be described. First, register address information is acquired from the ROM address indicated by the pointer PT (ST41). In this embodiment, the acquired register address information is one of the port numbers N1 to N3 (see FIG. 7B).

  Next, after updating the pointer PT, clear data is acquired from the address indicated by the pointer PT (ST42). The acquired clear data is any one of 22H to 44H corresponding to the port numbers N1 to N3 (see FIG. 7B).

  And the clear data acquired by the process of step ST42 is written in the predetermined register Ri specified by the process of step ST41 (ST43). As a result of this processing, an active level clear signal CLR signal is output from the NAND gate 83 shown in FIG. 7, the watchdog timer 54 is cleared to zero, and the reset operation of the CPU core is prevented beforehand.

  In this high-level configuration, the clear data changes cyclically for each interrupt process. For example, an illegal player tries to execute an illegal program instead of a regular control program triggered by a predetermined game operation. However, since the clear data to be output when the illegal program is executed is unknown, the illegal operation cannot be easily succeeded.

  In this embodiment, as shown in the circuit configuration of FIG. 6, if the WDT clear process (ST21) fails even once, the RAM rewrite operation (memory write) is not executed thereafter.

  When the WDT clear process (ST21) is completed as described above, next, a timer subtraction process is executed for the timer that manages the time of each game operation (ST22). The timer to be subtracted here is mainly used for managing the opening time of the electric tulip and the special winning opening and other game effect times.

  Subsequently, the value of the winning counter used in the winning lottery is updated (ST23). However, since the random number value RND used for the big hit lottery is automatically generated by the random number generation circuit GNR, there is no update processing of the random number value RND by program processing.

  Subsequently, ON / OFF signals of various switches including a winning detection switch of the symbol start opening 15 and the big winning opening 16 are inputted, and the ON / OFF signal level and edge information thereof are stored in the work area (ST24).

  Subsequently, an error management process is executed (ST25). The error management process includes a determination as to whether an abnormality has occurred inside the device, such as whether or not the supply of game balls has stopped or the game balls are clogged. Next, a management process based on the winning ball count signal received from the payout control unit 24 is executed (ST26).

  Subsequently, normal symbol processing is performed (ST27). The normal symbol processing means determination as to whether or not to operate an ordinary electric accessory such as an electric tulip. Specifically, if it is determined that the game ball has passed through the gate based on the switch input result in step ST24, the winning / not determining lottery is executed based on the value of the winning counter. Change to the middle operating mode. In addition, if it is a hit, processing for the operation of a normal electric accessory such as an electric tulip is performed.

  Subsequently, special symbol processing is performed (ST27). The special symbol process is a determination as to whether or not to operate a special electric accessory such as the special winning opening 16. Specifically, when it is determined that the winning switch signal SG has risen from the switch input result in step ST24, the random number value RND is acquired from the latch circuit LT, the big hit lottery process is executed, and the winning state is stored. If it is a value, the operation mode is changed to a big hit. In addition, if it is a big hit, processing for the operation of special electric accessories such as a big prize opening is performed.

  After such special symbol processing (ST28), the lighting operation of the LEDs managed by the main control unit 21 is advanced (ST29), and the solenoid driving processing for realizing the opening / closing operation of the electric tulip or the big prize opening is executed. After (ST30), the CPU is returned to the interrupt permission state EI and the timer interrupt is finished (ST31). As a result, the process returns from the interrupt process routine to the infinite loop process (FIG. 7) of the main process, and the process of step ST15 is executed.

  Although the embodiments of the present invention have been described in detail above, specific circuit configurations can be changed as appropriate.

GM gaming machine 21 main control means 22 effect control means REV abnormality handling means 21A electronic element SS3 standby means ST3 start means, initial processing 70 function register

In order to achieve the above object, the present invention executes a lottery process caused by a predetermined switch signal and outputs a control command for specifying the lottery result, and a lottery result specified by the control command. The main control means includes a CPU that executes a control operation including a lottery process, a RAM that is appropriately accessed during the control operation, and a control unit. Control program that regulates operation, ROM that stores operation parameters including set value data necessary for control operation, and CPU is reset if clear data is not received before the specified monitoring time anomaly and corresponding means, is configured to have a single electronic device having a built-in, and function register capable of setting a data defining the operation of the internal element, CPU reset to state Thereafter, a self-diagnosis means realized without the program processing of the control program and a predetermined start timing set based on the predetermined set value data stored in the ROM, realized without the program processing of the control program And a standby unit that waits until it reaches the position.

Claims (6)

A main control means for executing a lottery process caused by a predetermined switch signal and outputting a control command for specifying the lottery result; an effect control means for executing an effect operation corresponding to the lottery result specified by the control command; Comprising
The main control means is configured to fix a CPU that executes a control operation including a lottery process, a RAM that is appropriately accessed during the control operation, a control program that defines the control operation, and an operation parameter necessary for the control operation. Built-in ROM that stores data, an error handling means for resetting the CPU when clear data is not received by the predetermined monitoring time, and a function register that can set data defining the internal operation of the element Configured with a single electronic element
The function designation as to whether or not to operate the abnormality handling means and / or the monitoring time of the abnormality handling means are configured to be set by setting data written in a predetermined function register based on a control program. Gaming machines.   The gaming machine according to claim 1, wherein the function designation and the monitoring time are defined by setting data written in the same function register.   The gaming machine according to claim 1, wherein the predetermined function register is configured to be set by writing the same setting data multiple times.   The gaming machine according to any one of claims 1 to 3, wherein the predetermined function register is configured such that a data write operation is disabled after data is once written.   The gaming machine according to any one of claims 1 to 4, further comprising a configuration in which a write operation to the RAM can be prohibited after the CPU is reset based on the abnormality handling means. A main control means for executing a lottery process caused by a predetermined switch signal and outputting a control command for specifying the lottery result; an effect control means for executing an effect operation corresponding to the lottery result specified by the control command; Comprising
The main control means is configured to fix a CPU that executes a control operation including a lottery process, a RAM that is appropriately accessed during the control operation, a control program that defines the control operation, and an operation parameter necessary for the control operation. Built-in ROM that stores data, an error handling means for resetting the CPU when clear data is not received by the predetermined monitoring time, and a function register that can set data defining the internal operation of the element The specified clear data is repeatedly written to a specific single function register until a predetermined monitoring time is reached, or a specific multiple function register is set to a predetermined A gaming machine configured to avoid a CPU reset by cyclically writing clear data.

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