JP6192393B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine that generates a big hit state by a lottery process caused by a gaming operation, and more particularly to a gaming machine that can reduce a gaming control burden of a CPU and realize a desired security operation.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passing of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display time is changed in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7-7-7, a big hit state is established, and the big winning opening is repeatedly opened to generate a gaming state advantageous to the player.

  Whether or not to generate such a game state is determined by a jackpot lottery executed on the condition that a game ball has won at the symbol start opening, and the above symbol variation operation is based on this lottery result. It has become a thing.

  In this jackpot lottery process, the random number value RND acquired in response to the change of the switch signal indicating the winning of the game ball is compared with a predetermined lottery value Hit to determine whether or not the game is successful. Note that the random number value RND is not limited to determining whether or not the random number value RND is compared with a single numerical value Hit, but has a plurality of lottery values Hit1... Hitn, or an upper limit determination value HitH and a lower limit determination value HitL. In some cases, the winning range may be specified. For example, when the random value RND is equal to or higher than the lower limit determination value HitL and lower than the upper limit determination value HitH (HitL ≦ RND <HitH), it is determined that the winning state is established.

JP 2010-207288 A

  However, in this type of gaming machine, since the lottery value used for the determination of success / failure is stored in the ROM together with the control program, there is a problem that it can be easily grasped if the gaming machine is acquired. Thus, various illegal countermeasures have been proposed in the past (for example, Patent Document 1 and Patent Document 2). However, if the security level is increased, it is effective as an illegal countermeasure, but the original game operation is hindered for security processing. Will give.

  In other words, major control operations such as jackpot lottery processing are obliged to be executed by an 8-bit CPU, and the memory space for this control operation is also limited. Since the original game operation is hindered, complex and advanced game control cannot be realized. In addition, a configuration that can execute various lottery processes using a large number of random values without increasing the game control burden of the CPU is desired.

  The present invention has been made in view of the above-described problems, and can achieve a desired security operation without increasing the game control burden of the CPU. Various lottery processes can be performed with the game control burden of the CPU. An object of the present invention is to provide a gaming machine that can be executed without increasing the number.

In order to achieve the above object, the present invention is a gaming machine that executes a lottery process based on a predetermined switch signal and executes a game control operation corresponding to a lottery result, the game including the lottery process The main control means for executing the control operation includes a ROM for storing control programs and fixed data in a nonvolatile manner, a RAM for storing work data in a volatile manner, a random number generation means for generating random values for lottery processing, and a system A CPU that operates in response to a clock and a built-in one-chip microcomputer, and the random number generation means repeats an updating operation based on a system clock or other external clock to update a numerical value And a random number acquisition means capable of acquiring the numerical value of the numerical value update means when the switch signal is in the ON state, and the signal acquisition means for receiving the switch signal Of when the switch signal is in the ON state, it is configured to obtain the number from the random number acquisition means or numerical updating means, the numerical updating means receives the update clock generated based on the system clock or other external clock Te receives a first circuit for updating the number in the numerical range of 0 to 2 n ^-1, the update clock generated based on the system clock, be in the value range of 0 to 2 n ^-1, in advance A second circuit that updates a numerical value within a numerical value range of 0 to MAX that does not exceed a set maximum value MAX, and a determination unit that repeatedly determines a switch signal received by the signal acquisition unit every predetermined time And a lottery means for executing the lottery process based on the determination means determining the ON state of the switch signal. The lottery process is based on a generated value of the first circuit. And a special game state based on a result of the first process and a result of the second process. The second circuit is configured to start the update operation on condition that the maximum value MAX is set .

  The one-chip microcomputer of the present invention means a single electronic element that exhibits a computer function, and does not have any more limited meaning. The special game state includes at least the game state when the lottery process in the special symbol process or the normal symbol process of the embodiment is won.

The lottery process of the present invention includes a first process executed based on a generated value of the first circuit and a second process executed based on a generated value of the second circuit. Since the control operation in the special game state is executed based on the result and the result of the second process, complex and sophisticated game control can be realized. Further, since the second circuit starts the update operation on condition that the maximum value MAX is set, the security level can be increased.

  As described above, according to the present invention, a desired security operation can be realized without increasing the game control burden of the CPU, and various lottery processes can be executed without increasing the game control burden of the CPU.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a circuit diagram which shows the internal circuit of a one-chip microcomputer. It is a block diagram which shows the circuit structure of a random number generation circuit. It is the time chart etc. which show the operation | movement content of a random number generation circuit. It is a time chart which shows the operation content of CPU. It is another time chart which shows the operation content of CPU. It is a flowchart explaining the main process of a main control part. It is a flowchart explaining the timer interruption process of a main control part. It is drawing explaining another Example.

  Examples of the present invention will be described in detail below. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side rather than from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. An upper plate 8 for storing game balls for launch is mounted on the front plate 7, and a lower plate 9 for storing game balls overflowing from or extracted from the upper plate 8 and a launch handle 10 are mounted at the bottom of the front frame 3. And are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, the game board 5 is provided with a guide rail 13 formed of a metal outer rail and an inner rail in an annular shape, and a liquid crystal color display DISP is provided at the approximate center of the game area 5a inside. Is arranged. In addition, at a suitable place in the game area 5a, a symbol start opening 15, a big winning opening 16, a plurality of normal winning openings 17 (four on the right and left of the large winning opening 16), and a gate 18 serving as a passing opening are arranged. Yes. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  The liquid crystal display DISP is a device that variably displays a specific symbol related to a big hit state and displays a background image and various characters in an animated manner. This liquid crystal display DISP has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. And, in the special symbol display parts Da to Dc, a reach effect is executed that expects a big hit state to be invited, or in the special symbol display parts Da to Dc and the surroundings, a notice effect that informs the result of the success / failure is executed. Is done.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time, and the lottery extracted at the time when the game ball passes through the gate 18 is extracted. The stop symbol determined by the random number for use is displayed and stopped.

  For example, the symbol start opening 15 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws 15a. When the stop symbol after the fluctuation of the normal symbol display unit 19 displays a winning symbol, the symbol start port 15 is opened and closed. The claw 15a is opened only for a predetermined time or until a predetermined number of game balls are detected.

  When a game ball wins the symbol start port 15, the display symbols of the special symbol display portions Da to Dc change for a predetermined time and are determined based on the lottery result corresponding to the winning timing of the game ball to the symbol start port 15. Stop at the stop symbol. In addition, in special symbol display parts Da-Dc and its circumference, a notice effect may be performed between a series of symbol effects.

  The big winning opening 16 is controlled to open and close by, for example, an opening / closing plate 16a that can be opened forward, but when the stop symbol after the symbol change of the special symbol display portions Da to Dc is a big hit symbol such as “777”, the “big hit game” Is started, and the opening / closing plate 16a is opened. Various game modes such as 8 rounds and 16 rounds are provided as the number of special game rounds. Here, the larger the prescribed number of rounds, the more advantageous to the player.

  After the opening / closing plate 16a of the big prize opening 16 is opened, the opening / closing plate 16a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. In such an operation, the special game of the prescribed number of rounds as described above is continued and controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol of the special symbols, the game after the end of the special game is in a high probability state (hereinafter referred to as a probability variation state). The privilege is granted.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations. A dashed line in the figure mainly indicates a DC voltage line.

  As shown in the figure, this pachinko machine GM is provided with a power supply board 20 that receives AC 24V and outputs various DC voltages, system reset signals (power reset signals) SYS, and the like, and a main control board 21 that plays a central role in game control operations. And an effect control board 22 that executes a lamp effect and a sound effect based on the control command CMD received from the main control board 21, and a liquid crystal that drives the liquid crystal display DISP based on the control command CMD ′ received from the effect control board 22. The control board 23, the payout control board 24 for controlling the payout motor M based on the control command CMD "received from the main control board 21 and paying out the game ball, and the game ball is fired in response to the player's operation. The launch control board 25 is mainly configured.

  However, in this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the command relay board 26 and the effect interface board 27. The control command CMD ′ output from the effect control board 22 is transmitted to the liquid crystal control board 23 via the effect interface board 27, and the control command CMD ″ output from the main control board 21 is the main board relay board. It is transmitted to the payout control board 24 via 28.

  The main control board 21, the effect control board 22, the liquid crystal control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer. Accordingly, the circuits mounted on the control boards 21 to 24 and the operations realized by the circuits are collectively referred to as a function. In this specification, the main control unit 21, the effect control unit 22, and the liquid crystal control unit 23 are used. , And the payout control unit 24. All or part of the effect control unit 22, the liquid crystal control unit 23, and the payout control unit 24 is a sub-control unit.

  By the way, the pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and the new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame-side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, and a frame relay board 32, and these circuit boards are Each is fixed in place on the front frame 3. On the other hand, on the back of the game board 5, a main control board 21, an effect control board 22, and a liquid crystal control board 23 are fixed together with a liquid crystal display DISP and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place.

  The power supply board 20 is connected to the main board relay board 28 through the connection connector C2, and is connected to the power supply relay board 30 through the connection connector C3. The main board relay board 28 outputs the system reset signal SYS, the RAM clear signal DEL, the voltage drop signal, the backup power supplies BAK, DC12V, and DC32V received from the power board 20 to the main controller 21 as they are. Similarly, the power relay board 30 also outputs the system reset signal SYS received from the power board 20 and the AC and DC power supply voltages to the effect interface board 27 as they are. The production interface board 27 outputs the received system reset signal SYS to the production control unit 22 and the liquid crystal control unit 23 as they are.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and the system reset signal SYS, the RAM clear signal DEL, the voltage drop signal, the backup power supply, which are received by the main control unit 21. BAK is received directly along with other power supply voltages.

  Here, the system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V is turned on to the power supply board 20, and the one-chip microcomputers of the respective control units 21 to 24 by this power supply reset signal. The other IC elements are reset in power supply.

  The RAM clear signal DEL received from the power supply board 20 by the main control unit 21 and the payout control unit 24 is a signal that determines whether or not to initialize all areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. Therefore, it has a value corresponding to the ON / OFF state of the initialization switch SWT operated by the attendant.

  The voltage drop signal received from the power supply board 20 by the main control unit 21 and the payout control unit 24 is a signal indicating that the AC power supply 24V has started to drop. By receiving this voltage drop signal, each control unit 21, In 24, a necessary termination process is started prior to a power failure or business termination. The backup power supply BAK is a DC5V DC power source that retains data in the RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 25 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  On the other hand, the effect control unit 22 and the liquid crystal control unit 23 are not provided with the power supply backup function described above. However, as described above, the system reset signal SYS is commonly supplied to the effect control unit 22 and the liquid crystal control unit 23 via the power relay board 30 and the effect interface board 27. A power supply reset operation is realized at a timing substantially synchronized with the control units 21 and 24.

  As illustrated, the main control unit 21 transmits a control command CMD "to the payout control unit 25 via the main board relay board 28, while the payout control unit 25 receives a prize ball indicating a payout operation of the game ball. A count signal and a status signal CON relating to an abnormality in the payout operation are received, and the status signal CON includes, for example, a replenishment out signal, a payout shortage error signal, and a lower plate full signal.

  Further, the main control unit 21 is connected to each game component of the game board 5 directly or via the game board relay board 29. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. As shown in the figure, the winning switch signal SG is directly transmitted to the main control unit 21, and the other switch signals are transmitted to the main control unit 21 via the game board relay board 29.

  FIG. 4 illustrates a part of the internal configuration of the one-chip microcomputer 21 </ b> A of the main control unit 21. Here, the portion including the winning switch signal SG received from the detection switch SW of the symbol start port 15 is also shown. As shown in the figure, the one-chip microcomputer 21A includes a CPU core (hereinafter referred to as CPU) equivalent to Z80CPU (Zilog), a counter / timer circuit CTC equivalent to Z80CTC (counter timer circuit), a ROM and RAM memory circuit, a watch A dog timer WDT, a random number generation circuit GNR, and an input port INP are built in.

  As shown in FIG. 4, the winning switch signal SG from the detection switch SW is supplied to the random number generation circuit GNR of the one-chip microcomputer 21A via the buffer circuit BUF. The input port INP is supplied with a switch signal from a detection switch such as the big winning opening 16, the normal winning opening 17, or the gate 18.

  By the way, the buffer circuit BUF has an open collector type output section, and the input side is pulled up to 12V and the output side is pulled up to 5V. When the game ball passes through the symbol start port 15 and the detection switch SW enters a winning state (ON state), the buffer circuit BUF outputs a winning switch signal SG as a positive logic ON signal.

Here, the pulse width of the winning switch signal SG (game ball passing time T) is defined by the passing speed of the game ball and the detection range of the detection switch SW for detecting the game ball. For example, assuming that the detection range of a game ball by the detection switch SW is h, and assuming that a game ball with an initial velocity of 0 naturally falls from t = 0, the fall velocity V at the timing of t = T becomes V = gT. (G: Gravity acceleration) and 1/2 mV ² = mgh, the pulse width T = SQR (2h / g). If h = 3 mm, the pulse width should be T≈24.7 mS, h = 5 mm. T≈31.9 mS.

  As shown in FIGS. 4 and 5A, the random number generation circuit GNR receives a switch signal such as a winning switch signal SG and outputs a latch pulse LT, a system clock CLK, and an external clock XCLK. A frequency dividing circuit 31 that divides the frequency, a selection circuit 32 that selects one of the two types of clock signals divided by 2 as the update clock Φ, and N number sequence generators 33 that operate based on the update clock Φ. A sequence group generating group 33G, a latch group 34G including a plurality of latch circuits 34 that obtains a generation value of the sequence generator 33 based on a latch pulse LT received from the latch control circuit 30, and control parameters that define the operation of each unit Control register group 35G that holds an operation status indicating the operation status of each unit and abnormality detection for detecting an operation abnormality of the sequence generator 33 And a circuit 36.

  Although not shown in FIG. 5 in FIG. 4, the operation of each part of the random number generation circuit GNR is controlled by a dedicated processor different from the CPU core of the one-chip microcomputer 21A. However, in the present specification, the term “CPU” means the CPU core of the one-chip microcomputer 21A, and does not mean a dedicated processor.

  The latch control circuit 30 is configured to be able to supply a plurality of M switch signals, and is configured to be capable of independently outputting M types of latch pulses LT. Corresponding to the configuration of the latch control circuit 30, the number of latch circuits 34 constituting the latch group 34G is N × M, which is M times the number of the sequence generator 33. Corresponding to the N × M latch circuits 34, there are a total of N × M latch registers 35 (see 35b and 35d in FIG. 5A) that receive latch data from the latch circuit 34.

  Therefore, according to the random number generation circuit GNR of this embodiment, M × N random number values are generated based on a total of M types of switch signals including the switch signals of the symbol start port 15 and the normal winning port 17. The game contents can be enriched by enriching the lottery process. However, in this embodiment, for the sake of convenience, it is simplified that the switch signal supplied to the latch control circuit 30 is only the winning switch signal SG.

  As described above, the N × M latch circuits 34 constituting the latch group 34G correspond to the N number sequence generation units 33 constituting the number sequence generation group 33G and the M types of switch signals. The control register group 35G is provided with N × M latch registers (35b, 35d, etc.) corresponding to the N × M latch circuits 34, and corresponding to the N number sequence generators 33. N random number registers (35a, 35c, etc.) are provided.

  For example, the random number register 35a and the random number register 35c illustrated in FIG. 5A are a part of a total of N random number registers, and the latch register 35b and the latch register 35d illustrated in FIG. A part of × M latch registers.

  The CPU is configured to obtain the generated value of the sequence generator 33 latched in the latch circuit 34 by accessing a desired latch register such as the latch register 35b or the latch register 35d. In this embodiment, when the stored value of the latch register (35b, 35d, etc.) is read out to the CPU, the stored value of the latch register (35b, 35d, etc.) is automatically cleared to zero.

  In addition, since the control register group 35G of this embodiment includes N random number registers (35a, 35c, etc.), the CPU accesses the random number registers such as the random number register 35a, the random number register 35c, and so on. The instantaneous value of the numerical sequence generated by the sequence generator 33 can be grasped at any time. Therefore, according to the present embodiment, not only can a random number for lottery be specified by accessing a latch register (35b, 35d, etc.), but a random number for lottery can be specified by accessing a random number register (35a, 35c, etc.). You can also

  Further, the CPU can control the operation content of the random number generation circuit GNR by writing an appropriate control parameter to the control register group 35G. Further, the internal operation state of the random number generation circuit GNR, such as the operation state of the abnormality detection circuit 36 and the latch control circuit 30, can be grasped by the CPU reading the status value of the status register 35e which is a part of the control register group 35G. It is configured.

  Here, the status value of the status register 35 e includes N-bit error information for the N number sequence generators 33. Therefore, the CPU can confirm the presence / absence of abnormality of all the sequence generators 33 by reading the status value (error information) of the status register 35e.

  The N-bit status value (error information) is cleared to zero and changed to a value (= 0) indicating a normal state in response to a CPU read operation. Therefore, the CPU, for example, periodically reads out the status value (error information) of the status register 35e to determine whether the abnormal situation has returned to the natural state or is a fatal abnormal state that does not return spontaneously. can do. Note that the abnormality of the sequence generator 33 detected by the abnormality detection circuit 36 includes not only a serious error such as an operation stop but also a minor error such as a frequency shift of the update clock Φ.

  The status value of the status register 35e includes latch information indicating whether or not N × M latch registers (35b, 35d, etc.) hold latch data. In this latch information, the presence or absence of latch data is defined by 1 bit (0/1) for each of N × M latch registers, and the total is N × M bits.

  The status value (latch information) is configured to be readable and writable. The CPU reads the latch information for a predetermined latch register (35b, 35d, etc.) from the status register 35e, so that the latch register is significant. It can be determined whether or not data is held.

  When the CPU reads the latch data from a latch register (such as 35b or 35d) that holds significant data, the CPU can acquire a random value for the lottery process. As described above, when latch data is read from a latch register (35b, 35d, etc.), the data in the latch register is automatically cleared to zero.

  By the way, the status value for latch information is configured to be writable, and by writing zero as the status value (latch information) for a predetermined latch register, the latch data of the latch register is intentionally written. It is configured so that it can be cleared to zero.

  This configuration is particularly significant when a random number value for lottery is acquired from a latch register (35b, 35d, etc.), and when the latch register functions in the overwrite prohibition mode (FIG. 6 (f)). Have. In the overwrite prohibition mode, as will be described later, unless the latch register (35b, 35d, etc.) is cleared to zero, latch data cannot be acquired regardless of the subsequent latch pulse LT. On the other hand, when the random number for lottery is read, the latch register is automatically cleared to zero, and thereafter, the latch data is acquired only once in synchronization with the next latch pulse LT.

  For this reason, when the winning switch signal SG is maintained at the ON level even after the random number value for the lottery is read, the next latch data for the same winning switch signal SG is written in the latch register. Overwriting is prohibited. Assuming that the pulse width of the winning switch signal SG is 20 to 30 mS, such a situation naturally occurs. Even after the current winning switch signal SG returns to the OFF level, the latch register is in an overwrite-inhibited state. Will continue. In this overwriting prohibition state, the status value (latch information) of the status register 35e for the latch register is in the ON state (= 1).

  Therefore, for example, when the winning switch signal SG of this time transitions to the OFF state, the CPU writes zero as the status value (latch information) of the status register 35e for the latch register, so that the data of the latch register If zero is cleared to zero, the subsequent latch operation can be performed, and the above-described adverse effects can be solved.

  Returning to FIG. 5 and continuing the description, as shown in FIG. 5A, the winning switch signal SG is supplied not only to the latch control circuit 30 but also to the signal input register 35f constituting the control register group 35G. The CPU can grasp the level of the winning switch signal SG at any time by accessing the signal input register 35f. In this embodiment, the signal input register 35f is composed of an RS flip-flop that stores the ON / OFF state of the winning switch signal SG (see FIGS. 6B and 6C).

Next, the N number sequence generation units 33 constituting the sequence generation group 33G are divided into X number sequence generation units CT8 having an 8-bit length and Y number sequence generation units CT16 having a 16-bit length in detail. (N = X + Y), and the numerical sequence is updated in synchronization with the rising edge of the update clock Φ. The N number sequence generators 33 include a variable length sequence generator VCT that generates a numeric sequence in an arbitrarily set numerical range, and a numeric sequence in a specified numerical range (0 to 2 ⁿ −1). Each is subdivided into a fixed-length sequence generator FCT to be generated.

Here, the 8-bit fixed length sequence generator FCT ₈ generates a numeric sequence in the numerical range of 0-255, and the 16-bit fixed length sequence generator FCT ₁₆ generates a numerical sequence in the numerical range of 0-65535. while generating, starting from a random initial value, based on a predetermined occurrence pattern, while adopting a number of discrete, it is the appearance of two ⁸ or 2 ¹⁶ numbers to cycle the numerical range of fixed. Then, after that, starting from another initial value, the same operation is repeated based on another appearance pattern.

  Such a fixed-length sequence generator FCT starts an update operation from a random initial value as soon as the power supply of the one-chip microcomputer 21A is reset. Even if the CPU is abnormally reset based on WDT or the like, the update operation is not stopped and the above random update operation is repeated, so that it is practically impossible to estimate the numerical sequence. In other words, if it is possible to know the appearance pattern and initial value of the numerical string by some method and know the lottery value Hit of the big hit lottery, it is useless to intentionally reset the CPU abnormally. Even if the power of the one-chip microcomputer 21A is reset, the time from when the power is reset until the CPU obtains the numerical value of the sequence generator 33 is not exactly fixed. Is impossible.

  Although the fixed-length sequence generator FCT has been described above, the variable-length sequence generator VCT has a maximum value arbitrarily set in the prescribed control register 35 as an upper limit value, in an arbitrary numerical range of 0 to the maximum value. Generate numeric columns. The generation operation of the numeric sequence is the same as that of the fixed-length sequence generation unit FCT, and the variable-length sequence generation unit VCT starts from a random initial value and takes a jumping numerical value based on a predetermined appearance pattern. Cycle through the set numerical range. Then, after that, starting from another initial value, the same operation is repeated based on another appearance pattern.

  The variable-length sequence generator VCT repeats the above random update operation without stopping the update operation even when the CPU is abnormally reset, unless the one-chip microcomputer 21A is reset. This is the same as the operation of the fixed-length sequence generator FCT. However, when the power supply of the one-chip microcomputer 21A is reset, the variable-length sequence generator VCT starts the update operation after setting the maximum value in the prescribed control register 35, so that the fixed-length sequence generator Slightly lower security level than FCT.

  However, the variable-length sequence generator VCT has an advantage that the winning probability in the lottery process can be accurately defined by appropriately setting the numerical range of the numerical sequence to be generated. According to the variable-length sequence generator VCT, the winning probability can be accurately reduced to 1/200 simply by setting the maximum value in the numerical range of the generated numerical sequence to, for example, 199. Each time the fixed-length sequence generator FCT receives the update clock Φ, the numeric sequence is updated in synchronization with the rising edge. However, the variable-length sequence generator VCT has a specified number (specified by an appropriate prime number). Until the update clock is received, the numerical value up to that time is maintained, and the numerical value sequence is updated in synchronization with the rising edge of the last update clock Φ. Therefore, the randomness in this sense increases.

Therefore, in the present embodiment, in consideration of these characteristics of the variable-length sequence generator VCT and the fixed-length sequence generator FCT, the random number RND for the big hit lottery has a 16-bit fixed-length sequence generator FCT. ₁₆ is used for the lottery determination of details such as the number of rounds of special games and the symbol lottery that specifies whether the odd hit or the odd hit in the big hit state, and the 8-bit variable length sequence generator VCT ₈ ing. Although not limited in any way, in this embodiment, the 8-bit variable-length sequence generator VCT ₈ sets the maximum value to 199, thereby setting the numerical value range from 0 to 199.

As described above, the variable-length sequence generator VCT has a slightly lower security level than the fixed-length sequence generator FCT, but the 8-bit variable-length sequence generator VCT ₈ is a detail after winning the big hit lottery. According to the present embodiment, even if the 8-bit variable length sequence generator VCT ₈ is used, an extremely high security level is ensured by the 16-bit fixed length sequence generator FCT _16. Maintained.

As shown in FIG. 5C, the fixed-length sequence generator FCT ₁₆ / FCT ₈ includes an update register R1, a plurality of addition value registers R2... R2, each holding an appropriate addition value, and a plurality of additions. A counter CT for generating address information for selecting any one of the value registers R2... R2, and an adder AD for adding the respective added values of the selected addition value register R2 and the update register R1. Has been. Here, the number of additional value register R2 · · · R2 is ^{2 X} number, among the Y output bits of the counter CT, arbitrarily chosen X bits (Y> X) is, the additional value register R2 · .. Used as address information for selecting R2.

In FIG. 5C, for convenience of description, it is described that there are an adder AD and 2 ^X addition value registers R2... R2 as hardware. The function is realized by a dedicated processor. Further, the actual addition value register R2 is substituted with an addition value stored in a memory (not shown) of the random number generation circuit GNR.

  The addition result of the adder AD is stored in the update register R1, and the selected addition value register R2 is changed in synchronization with the update clock Φ. The adder AD is a 16-bit or 8-bit adder and functions in synchronization with the update clock Φ. Therefore, when the value of the update register R1 is DA1 and the value of the addition value register R2 selected at that time is DA2, the operation of R1 ← DA1 + DA2 is executed as an addition operation of 16-bit length or 8-bit length. The

In this embodiment, by setting the retention value of the addition value register R2 · · · R2 suitably, 2 ⁸ or 2 when ¹⁶ receives the update clock [Phi, numerical numerical sequence generated so far The range (0 to 2 ¹⁶ −1 or 2 ⁸ −1) is configured to make a round. Then, the update registers R1 is and when the power is turned on, after receiving the 2 ⁸ or 2 ¹⁶ update clocks [Phi, by being changed to an appropriate initial value, starting from "a random initial value, a predetermined Based on the appearance pattern of, the operation to go around the set numerical range while taking the jumping numerical value is realized. Further, after receiving 2 ⁸ or 2 ¹⁶ update clocks [Phi, of Y output bits of the counter CT (Y> X), by X bits selected is changed as appropriate, the additional value The selection order of the registers R2... R2 changes, and the appearance pattern is changed.

The basic structure of the variable-length sequence generators VCT ₁₆ / VCT ₈ is the same, but a counter CT ′ that defines the update timing is added (see the broken line part). The counter CT operates the adder AD with the carry signal CY on condition that the update clock Φ is received a specified number of times (set to an appropriate prime number), and as a result, until the specified number of update clocks Φ is received. An anomalous operation that maintains the previous values is realized.

Further, the variable length sequence generator VCT ₁₆ / VCT ₈ is provided with a correction unit AM (see the broken line portion) so that the addition result is included in the set numerical range (0 to MAX), and the output of the adder AD Of the bits, only the necessary bit portion that does not exceed the upper limit value MAX is used. When the addition result SUM exceeds the upper limit value MAX, a correction calculation of SUM ← SUM-MAX is executed.

  As described above, the example of the internal configuration of the sequence generator 33 has been described in a very simplified manner, but actually, the sequence generator 33 has a more complicated configuration to increase the security level.

  As shown in FIG. 5A, the 16-bit fixed length sequence generator 41a is connected to a transposition circuit 42 that is controlled by a dedicated processor and appropriately replaces the bit arrangement of 16-bit numeric values. The fixed-length sequence generator FCT 41a and the transposition circuit 42 operate under the control of the count control unit 40a that gives a 16-bit transposition pattern or a random initial value. The count control unit 40a operates based on the control parameter set in a predetermined control register of the control register group 35G, and the abnormal state of the sequence generator 41a is stored as a status value (error information) of the status register 35e. Is done.

  As shown in FIG. 5A, the output of the transposition circuit 42 is supplied to the random number register 35a of the control register group 35G together with the 16-bit latch circuit 34, and the CPU always stores the 16-bit value of the random number register 35a. It can be acquired.

The same applies to the 8-bit variable-length sequence generation unit 41b (VCT _8), 8-bit variable-length sequence generation unit 41b (VCT ₈₎ is controlled by the counting control unit 40b, a predetermined numerical range (0 199), a numerical sequence is generated, and the updating operation is repeated for each round based on a random initial value. The count control unit 40b also controls the update operation of the sequence generator 41b based on a control parameter (such as a maximum value) set in a predetermined control register of the control register group 35G, and the abnormal state of the sequence generator 41b is It is stored as a status value (error information) in the status register 35e.

  The output of the 8-bit length sequence generator 41b is also supplied to the random number register 35c of the control register group 35G together with the 8-bit latch circuit 34 so that the CPU can obtain the value of the random number register 35c at any time. It has become.

As shown in FIG. 4, the frequency dividing circuit 31 is configured to be able to supply not only the system clock CLK that defines the operation of the CPU but also an external clock XCLK that operates independently of the system clock CLK. The two clock signals CLK and XCLK are both divided by the frequency dividing circuit 31 and supplied to the selection circuit 32, and one of the clock signals is fixed to 16 bits based on the set value in the control register 35. It is selected as the update clock Φ for the long sequence generator 41a (FCT ₁₆ ). Note that the system clock CLK is used as the update clock Φ for the 16-bit variable length sequence generator VCT ₁₆ and the 8-bit length sequence generator FCT ₈ / VCT ₈ .

By the way, in the present embodiment, when the 16-bit fixed length sequence generator 41a (FCT ₁₆ ) is using the external clock XCLK and the abnormality detection circuit 36 detects an abnormal operation of the sequence generator FCT ₁₆ , Instead of the external clock XCLK, the system clock CLK is automatically used. Therefore, even if an abnormality occurs in the external clock XCLK, the sequence generator FCT ₁₆ can not only continue the update operation, but also prevent illegal acts that abuse the external clock XCLK. As described above, the abnormal operation of the sequence generator FCT ₁₆ includes not only the stop of the update clock Φ but also an abnormal decrease in the frequency of the external clock XCLK, for example.

  In any case, the external clock XCLK should be asynchronous with the system clock CLK, but its frequency should be the same as that of the system clock CLK from the viewpoint of stabilization of the internal operation. Is set to a frequency of about 0.8 to 1.6 times the frequency of the system clock CLK. Although not particularly limited, in the case of the embodiment, the frequency of the system clock CLK is about 20 MHz.

In this embodiment, as described above, the external clock XCLK can be used. However, from the viewpoint of security, the update operation of the sequence generator FCT ₁₆ is not synchronized with the system clock CLK, so the external clock XCLK is used as the update clock Φ. It is preferable to do this. On the other hand, it is preferable to use the system clock CLK as the update clock Φ from the viewpoint of adopting a simple configuration that omits the oscillation circuit of the external clock XCLK.

  Therefore, in the present embodiment, jumper wires J1 and J2 are provided so as to be able to arbitrarily select which operation mode to use for each model of gaming machine (see FIG. 4), and the following three operation modes (a) to (a) to (C) can be arbitrarily selected.

For example, in the model (a) that cuts the jumper line J2, the external clock XCLK is selected as the update clock Φ for the sequence generator FCT ₁₆ , and in the model (b) that cuts the jumper line J1, the system clock CLK is the update clock. A control parameter is set in the control register 35 so that Φ is selected. Further, in the model (c) in which the input terminal IN is pulled down without supplying the external clock XCLK while the jumper lines J1 and J2 are maintained (see the broken line portion), the external clock XCLK is used for the sequence generator FCT ₁₆ . A control parameter is set in the control register 35 so that the update clock Φ is selected. In the third model (c), since the external clock XCLK is not supplied, the system clock CLK that has passed through the bypass path Bypass is actually used.

In the third model (c), even if an abnormality occurs in the wiring pattern on the bypass path Bypass, the normal path is automatically automatically detected by the abnormality detection circuit 36 that detects the abnormal operation of the sequence generator FCT _16. Since the normal system clock CLK is used, the sequence generator FCT ₁₆ can continue to operate normally. In this case, since there is no frequency change at the time of operation transition, a very natural transition operation can be realized. Therefore, this embodiment is configured as a third model (c). Therefore, the update clock Φ of all the sequence generators 33 is obtained by dividing the system clock CLK by two.

  Next, the operation of the latch control circuit 30 and the latch register (35b, 35d, etc.) will be described with reference to FIGS. The latch control circuit 30 can be supplied with a plurality of switch signals. However, as described above, it is assumed that only the winning switch signal SG is supplied (M = 1). However, even when other switch signals are supplied (M ≠ 1), the same operation as described below is realized.

  As shown in FIG. 6A, in this embodiment, the ON / OFF level of the winning switch signal SG is determined at the falling edge of the update clock Φ (see FIG. 6A (b)). The generation values of the N number sequence generation units 33 are updated based on the appearance patterns (see FIG. 6A (c)). Note that not only the numerical range of the numerical sequence and the update timing are different for each type of the numerical sequence generation unit 33, but also the appearance pattern of the numerical sequence that appears and the initial value of the appearance pattern are different, so that N number sequences are generated. As a general rule, the numerical sequence of the part 33 is different.

  In parallel with the updating operation of the sequence generator 33, the latch control circuit 30 determines whether or not the winning switch signal SG is continuously maintained at the ON level for a predetermined time. For example, the update clock Φ The latch pulse LT is output on condition that the ON level is continuously maintained 128 times as measured in (see FIG. 6A (d)). In the present embodiment, since such a determination operation is provided, there is no possibility of misidentifying spike-like noise as the winning switch signal SG.

In the case of the present embodiment, the system clock CLK of about 20 MHz passing through the bypass path Bypass shown in FIG. 4 is divided by two to become the update clock Φ, so the update clock Φ is about 10 MHz. Therefore, when the latch pulse LT is output, it is ensured that at least the winning switch signal SG continuously maintains the ON level for about 128/10 ⁶ = 128 μS, and the influence of noise is eliminated. It is also possible to eliminate fraudulent games that abuse noise.

  The latch pulse LT generated in this way by the latch control circuit 30 is supplied to N × M latch circuits 34 constituting the latch group 34G, and each latch circuit 34 has a sequence generator 33 corresponding to itself. The generated value is acquired and held in synchronization with the latch pulse LT, and is output as it is to N × M latch registers (35b, 35d, etc. in FIG. 5) (see FIGS. 6A (e) (f)).

  However, in this embodiment, the update clock Φ is about 10 MHz, and the pulse width T of the winning switch signal SG is about 30 mS, so that the generated value of the sequence generator 33 is latched by the latch circuit 34. However, the winning switch signal SG is maintained in the ON state. Therefore, thereafter, the latch pulse LT is repeatedly output to the latch circuit at a time interval of about 128 μS.

  In consideration of such an operation, in this embodiment, the latch registers (35b and 35d) are used in the overwrite prohibition mode (FIG. 6A (e)) or in the overwrite permission mode (FIG. 6A (f)). These can be arbitrarily selected. The overwrite prohibition mode means an operation mode in which the output data of the latch circuit 34 is not accepted until the latch data of the latch register (35b, 35d, etc.) is read and cleared by the CPU. In the case of adopting such an operation mode, there is a significance that the generated value of the sequence generator 33 at the timing close to the ON edge of the winning switch signal SG can be acquired even when the numerical value acquisition timing of the latch register by the CPU is delayed. . FIG. 6A (e) shows that the numerical value X acquired first is used for the random number for lottery. When the numerical value X is acquired, the latch registers (35b and 35d) are cleared to zero, and the status value of the status register 35e is also zero (FIG. 6A (g)).

  On the other hand, the overwrite permission mode is an operation mode in which the output data of the latch circuit 34 is always accepted, and each time the latch circuit 34 receives the latch pulse LT, the latch register (35b, 35d, etc.) This means the operation mode for re-acquiring. In the case of adopting such an operation mode, if the acquisition timing of the CPU is delayed, a numerical value at a timing far from the ON edge of the winning switch signal SG (for example, about several tens of milliseconds) is acquired.

  In this case, for example, even if the illegal player turns on the winning switch signal SG for the optimal timing, the actually acquired numerical value cannot be brought close to the value intended by the illegal player. Is an advantage. In FIG. 6A (f), the numerical value X acquired first is then replaced with the numerical value Y, and then changes one after another, and the finally latched numerical value is used as the random number for lottery. Which indicates that. In the illustrated example, when the numerical value Y is acquired, the latch registers (35b and 35d) are cleared to zero, and the status value of the status register 35e is also zero (FIG. 6A (g)).

  Both the overwrite prohibition mode and the overwrite permission mode are sufficiently significant, but in this embodiment, the 16-bit random number register 35a is used without using a latch register (35b and 35d in FIG. 5). Based on the 8-bit random number register 35c, the random number for lottery is specified. This is because the status value of the status register 35e is set in response to the latch data being stored in the latch register based on the latch pulse LT even after the latch register (35b, 35d in FIG. 5) is cleared to zero. This is because the status value may be mistaken for the new winning switch signal SG.

  However, since this problem can be sufficiently solved by simply monitoring the ON edge of the winning switch signal SG, the significance of the latch register functioning in the overwrite mode or the overwrite prohibit mode is not denied, There is no change in demonstrating.

  After confirming the above, an embodiment for specifying the random number for lottery based on the random number registers 35a and 35c will be described. In the embodiment, the random number for lottery is specified based on the random number registers 35a and 35c, but the latch register 35b (one or more) receiving the output of the 16-bit latch circuit 34 and / or the 8-bit latch circuit. The latch register 35d (one or a plurality) receiving 34 outputs may be accessed by the CPU to identify the random number for lottery, but rather it is more typical.

  In any case, the 16-bit random number register 35a includes a 16-bit D latch 50, 8-bit bus buffers 51L and 51H, a negative logic OR gate 52, as shown in FIG. , And is configured. As described above, the random number register 35a holds a numerical value in units of 1 byte. In relation to this configuration, the random number register 35a is assigned two consecutive address values NN and NN + 1.

  These points also apply to the 16-bit length latch register 35b, which includes a 16-bit length D latch, two 8-bit length bus buffers, and a negative logic OR gate. Two consecutive address values NN ′ and NN ′ + 1 are numbered. The reason why the random number register 35a and the latch register 35b handle 2-byte data for each byte is that the data bus D0-D7 of the CPU equivalent to Z80 is 1 byte wide, and is incorporated in the CPU. This is because the general-purpose register groups W, A, B, C, D, E, H, and L each handle 1-byte data (see FIG. 5A).

  In the general-purpose register group, the data width of IX and IY is 16 bits long, and the address data output from the program counter PC to the address bus A0-A15 is also 16 bits long. The address values NN and NN ′ described above are supplied to the address decoder 37 via the address buses A0 to A15, whereby an appropriate decode signal DEC is generated, and any one of the control registers 35 receives the decode signal DEC. Will be selected. In this embodiment, the lower 8 bits A0-A7 of the address bus A0-A15 are shared with the data bus D0-D7.

  Returning to the random number register 35a shown in FIG. 5B, the bus buffers 51L and 51H assigned to the address NN and the address NN + 1 are selected by the selection signal output from the address decoder 37. One selection signal has an active level (L level) when the value of the address bus A0-A15 is NN, and the other selection signal has an active level when the value of the address bus A0-A15 is NN + 1. (L level). Since the two selection signals are supplied to the negative logic OR gate 52, the decode signal DEC output from the negative logic OR gate 52 is at the L level when either or both of the two selection signals are at the L level. It becomes.

  The D latch 50 is configured by providing 16 circuit configurations shown in FIG. The D latch 50 operates by receiving the transposed numerical values CT0 to CT15 output from the transposing circuit 42 and the decode signal DEC. Specifically, 16 MOS transistors Q1 that commonly receive the decode signal DEC, 16 MOS transistors Q2 that receive the decode signal DEC via NOT gates (16), and a source terminal of the MOS transistor Q2 And NOT gates (2 × 16) for connecting the drain terminals.

  Since the D latch 50 is configured as described above, when the decode signal DEC is at the H level, the transistor Q1 is in the ON state, the transistor Q2 is in the OFF state, and conversely, the decode signal DEC is at the L level. In this case, the transistor Q1 is turned off and the transistor Q2 is turned on.

  Therefore, when the decode signal DEC is at the H level, the 16-bit length numerical value CTi (IN) that is the output of the transposition circuit 42 passes through the transistor Q1 and the two NOT gates, and remains at that level. CTi (OUT). On the other hand, when the decode signal DEC becomes L level, the transistor Q1 is turned off, so that the output of the transposition circuit 42 is not transmitted, and the input data immediately before being stored in the stray capacitance of the MOS transistor Q1 Pass through and output.

  Therefore, according to this circuit configuration, the numerical value CTi transmitted to the bus buffers 51L and 51H can be fixed by shifting the decode signal DEC to the L level. In other words, if the CPU accesses the bus buffers 51L and 51H in the state of the decode signal DEC = L, the upper byte and lower byte of the same numerical value can be stably acquired.

  The 16-bit random number register 35a has been described above, but the circuit configuration of the 8-bit random number register 35c is basically the same as that of the random number register 35a. That is, the random number register 35c includes an 8-bit D latch, an 8-bit bus buffer, and a negative logic OR gate. However, the random number register 35c receives the value of the 8-bit length sequence generation unit 41b without going through the transposition circuit, and the random number register 35c has a single bus buffer to hold it. Are numbered with a single address value.

  Next, the main part of the latch control circuit 30 that outputs the latch pulse LT (FIG. 6A (d)) will be described. The latch control circuit 30 includes the noise removal circuit shown in FIG. 6C, and the noise removal circuit includes two 128-ary counters CT1 and CT2 and two winning switch signals SG that receive positive logic and negative logic. It is composed of AND gates G1 and G2 and a NOT gate G3. Here, the update clock Φ is supplied to each of the two AND gates G1 and G2.

  The carry output CY of the counter CT1 is supplied as a latch pulse LT to each latch circuit 34, and the carry outputs CY and CY of the counters CT1 and CT2 are supplied to the set terminal S and the reset terminal R of the signal input register 35f. Has been. As shown in FIG. 6C, in this embodiment, one bit of the signal input register 35f is composed of an RS flip-flop.

  Since the winning switch signal SG is supplied to the clear terminal CLR of the counter CT1 together with the AND gate G1, if the winning switch signal SG is at the L level, the count value of the counter CT1 is maintained at the zero state. Become. On the other hand, the winning switch signal SG is supplied to the clear terminal of the counter CT2 together with the AND gate G2 via the NOT gate G3.

  Since the noise removal circuit (FIG. 6C) of the present embodiment is configured as described above, if the winning switch signal SG = H, the counter CT1 is counted up based on the update clock Φ, and the 128th When the update clock Φ is received, a carry signal CY as a latch pulse LT is output. Thereafter, every time the 128th update clock Φ is received, the latch pulse LT is repeatedly output (see FIG. 6A (d)).

  Since the carry signal CY of the counter CT1 is also supplied to the set terminal S of the signal input register 35f (RS flip-flop), the signal input register is provided on the condition that 128 update clocks Φ are continuously received. The stored value of 35f becomes H level. FIG. 6B illustrates the relationship among the winning switch signal SG, the update clock Φ, and the stored value of the signal input register 35f.

  By the way, when the winning switch signal SG = L during the counting operation of the counter CT1, the counter operation returns to the initial state, so that the winning switch signal SG continues to be H for 128 update clocks. On condition that the signal is at the level, the signal input register 35f becomes H level, and the latch pulse LT is output. Therefore, the influence of spike noise that may be mistaken for the winning switch signal SG is eliminated. FIG. 6B shows a state in which the H level noise is superimposed in the state where the winning switch signal SG = L, but the latch pulse LT is output by such H level noise or the signal input register. There is no possibility that the stored value of 35f changes.

  Next, the winning switch signal SG stored in the signal input register 35f also returns to the L level after several tens of milliseconds. Then, after the winning switch signal SG transitions to the OFF level, the counter CT2 starts the counting operation, and when the 128th update clock Φ is received, the carry signal CY is output from the counter CT2. Since the carry signal CY is supplied to the reset terminal R of the signal input register 35f (RS flip-flop), the stored value of the signal input register 35f is L level in synchronization with the output of the carry signal CY from the counter CT2. Will return.

  As described above, in this embodiment, the signal input is performed on the condition that the winning switch signal SG is not only at the H level but also at the L level on the condition that it continues for a predetermined time (128 update clocks). Since the data is acquired by the register 35f, it is possible to reliably eliminate the adverse effects due to noise.

  That is, even if spike noise is superimposed after the winning switch signal SG becomes ON level, there is no possibility that the winning switch signal SG is mistakenly assumed to be OFF level. Therefore, from the ON transition of the winning switch signal SG, Even if the signal input register 35f is accessed with considerable delay, the winning switch signal SG is not missed unless the delay is large (for example, 30 mS or more). FIG. 6B shows a state where L level noise is superimposed in the state where the winning switch signal SG = H, but the stored value of the signal input register 35f is caused by such L level noise. There is no risk of change.

  As described above, the configuration in which the level of the winning switch signal SG can be grasped while eliminating the influence of noise has been described. However, in this embodiment, it is of great value to achieve the noise removal effect without using any CPU software processing. There is.

  That is, it is possible to realize the same operation as described above by the program processing, but if such a method is adopted, the processing load on the CPU increases and the important game control is adversely affected. In addition, in this type of gaming machine, there is a problem in that the ROM storage capacity is wasted because there is a strict limit on the ROM usage capacity of the main control unit, but according to this embodiment, the ROM storage capacity The above-described excellent noise resistance performance is exhibited without consuming any of the above.

Next, a read operation in which the CPU reads the numerical value of the 16-bit random number register 35a will be described with reference to FIG. FIG. 7B shows an update clock Φ generated by dividing the system clock CLK by 2, and a sequence that is a 16-bit fixed-length sequence generator FCT ₁₆ at the rising edge of the update clock Φ. It shows that the generation unit 41a (see FIG. 5A) is updated. FIG. 7A shows the numerical values of the sequence generator 41a. For convenience of explanation, the appearance pattern is a simple increment update (+1) and is updated from M → M + 1.

  In the following description, a 16-bit data load instruction LDWA, (HL) will be described as an example. Prior to the execution of this load instruction, the HL register stores 16-bit data NN which is the head address value of the random number register 35a.

  The load instruction LD WA, (HL) acquires the storage value of the register numbered by the address value NN indicated by the HL register (lower one byte storage value of the random number register 35a) in the A register and is numbered NN + 1. This is an instruction for acquiring the stored value of the registered register (the upper one byte stored value of the random number register 35a) in the W register. This load instruction is a 2-byte instruction divided into a 1-byte length opcode and a 1-byte length operand, and is configured to finish execution using four cycles of the system clock CLK.

That is, as shown in FIG. 7C to FIG. 7E, in the first cycle (M1 cycle), the address value of the memory (1st byte of this instruction (LD WA, (HL)) is stored ( The value of the program counter PC _H / PC _L ) is output to the address bus A0-A15 and the opcode is acquired by the CPU. Then, in the second cycle, the address value of the memory in which the second byte of this instruction is stored ( the value of the program counter _PC H · _{PC L)} is the operand to be output to the address bus A0-A15 CPU is obtained.

  In the subsequent third cycle, the 16-bit address value NN is output to the address bus A0-A15, and the lower 1 byte storage value of the random number register 35a is acquired in the A register. In the fourth cycle, the address bus A0- The 16-bit address value NN + 1 is output to A15, and the upper 1-byte stored value of the random number register 35a is acquired in the W register. 7F to 7H are control signals output from the CPU to the control bus. The M1 signal (f) indicating the M1 cycle and the memory request signal MREQ (g), respectively. The memory read signal RD (h) is shown.

  FIG. 7 (i) shows the decode signal DEC output from the negative logic OR gate 52 of the random number register 35a. As described above, the decode signal DEC is an address decode value of the address value NN output to the address buses A0 to A15 and a negative logical OR value of the address decode value of the address value NN + 1. Only the third and fourth cycles during execution of the instruction are at the L level, and at other timings, the H level is set.

  Therefore, the D latch 50 of the random number register 35a is in the ON state until the second cycle during the above four-cycle operation, and transmits the numerical value CTi from the transposition circuit 42 to the bus buffers 51L and 51H. The cycle and the fourth cycle are turned off, and the numerical value CTi from the transposition circuit 42 is cut off. Therefore, the output value of the transposition circuit 42 at the end of the second cycle is maintained without change between the third cycle and the fourth cycle.

  Thus, in this embodiment, the D latch 50 is provided in the random number register 35a, and its ON / OFF state is controlled by the decode signal DEC. Therefore, the address assigned to the control register such as the 16-bit long random number register 35a. As long as information is continuously output to the address buses A0 to A15, the numerical value at that time can be obtained accurately. Therefore, for example, even if the random number register 35a is accessed at a timing when a 16-bit numeric value sequence adopting the +1 appearance pattern is updated from the state of the numerical value 01FFH to 0200H, the value acquired by the CPU is , 01FFH or 0200H is a value obtained by transposing a normal numerical value, and there is no possibility that a halfway numerical value such as 02FFH is transposed and acquired.

  This operation is similarly ensured when the update clock Φ is generated not from the system clock CLK but from the external clock XCLK. That is, as shown in FIG. 7 (j), even when an update clock Φ that is faster and not synchronized with the system clock is used, the normal value A + 1 is transposed by the open / close control of the D latch by the decode signal DEC. Value can be obtained.

  On the other hand, if a load instruction that does not continuously output the address information assigned to the control register to the address buses A0 to A15 is used, the above stable operation cannot be guaranteed. FIG. 8 illustrates a case where the load instruction LD A, (DE) and the load instruction LD W, (HL) are consecutive. Prior to these instructions, an address value NN is stored in the DE register, and an address value NN + 1 is stored in the HL register. Further, for convenience of explanation, it is assumed that a 16-bit numeric string has an appearance pattern of +1.

  In this state, even if the load instruction LD A, (DE) and the load instruction LD W, (HL) are continued, the load instruction LD W is unavoidable after the execution of the load instruction LD A, (DE). , (HL) instruction fetch cycle (M1) enters, the decode signal DEC cannot be maintained at the L level, and as a result, it is not a value obtained by transposing a normal address value such as M or M + 1. The halfway numerical value combining the lower byte of the numerical value M and the upper byte of the numerical value M + 1 is transposed and acquired by the CPU.

In such a case, an unreasonable random number value RND particularly when the numerical range (0 to MAX) of the generated numerical sequence is not the fixed range (0 to 2 ¹⁶ ) (MAX <2 ¹⁶ −1). There is also a risk of acquiring. For example, when the upper limit value MAX of the numerical sequence is MAX = 1150H, if a random number value is acquired when updating from 10FFH to 1134H, the acquired random number value becomes 11FFH and exceeds the upper limit value MAX. End up.

  The random number generation circuit GNR has been described in detail above. Next, the game operation of the main control unit 21 executed by the CPU shown in FIG. 4 will be described. FIGS. 9 and 10 are flowcharts showing the control program of the main control unit 21, which is started at a system reset process (FIG. 9) that is started based on the restoration or turning on of the power supply voltage and every predetermined time (4 mS). And maskable timer interrupt processing (FIG. 10).

  Hereinafter, the system reset processing program (main processing) will be described with reference to FIG. The main process is started when the initialization switch SWT is OFF and the power is turned ON, such as when recovering from a power failure, and when the game hall is opened, the initialization switch SWT is ON. There is a case where the power source is turned on by being operated. In some cases, the watchdog timer WDT is activated and the CPU is forcibly reset.

  In any case, the Z80 CPU first initializes the value of the stack pointer SP in the CPU corresponding to the final address of the stack area (ST1). Next, the values of various registers including the control register group 35G of the random number generation circuit GNR of the one-chip microcomputer are initialized (ST2).

  When the initial setting process in step ST2 is completed, the RAM clear signal DEL is acquired from the input port INP (ST3). The RAM clear signal DEL is a signal for determining whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer 21A, and has a value corresponding to the ON / OFF state of the initialization switch SWT operated by the staff. Have.

  Next, the level of the RAM clear signal DEL is determined (ST4). Assuming that the RAM clear signal DEL is in the ON state, the entire area of the built-in RAM is cleared to zero (ST8). Next, a control command for notifying that the RAM area has been cleared to zero is output (ST9).

  Next, the CTC that outputs the interrupt signal INT for starting the timer interrupt operation (FIG. 10) is initialized (ST10). Then, with the CPU set to the interrupt disabled state (ST11), if there is a necessary counter, update processing is executed for this (ST12), then the CPU is returned to the interrupt enabled state (ST13), and step ST11. Return to.

  However, in this embodiment, since a large number of random values can be acquired from the random number generation circuit GNR, all the processes in steps ST11 to ST13 can be eliminated. Therefore, the storage capacity of the ROM can be saved by the amount of ST11 to ST13, and other control processes can be enriched.

  Next, returning to the determination process in step ST4, the RAM clear signal DEL is in the OFF state when the CPU is forcibly reset by the watchdog timer WDT or the like, or when recovering from the power failure state. In such a case, the content of the backup flag BFL is determined following the determination in step ST4 (ST5). The backup flag BFL is data indicating that the backup process has been executed in the power supply monitoring process (ST20). In this embodiment, the backup flag BFL is set to 5AH when the power is shut off, and the process of step ST20 after the power is restored. Is cleared to zero.

  Therefore, when the power is turned on or when recovering from the power failure state, the content of the backup flag BFL is 5AH. However, if the program goes into a runaway state for some reason and a CPU reset operation is caused by the watchdog timer, the backup flag BFL = 00H. Therefore, when BFL ≠ 5AH (normally BFL = 00H), the process proceeds from step ST5 to step ST8 to return the operation of the gaming machine to the initial state.

  On the other hand, if the backup flag BFL = 5AH, a checksum calculation for calculating a checksum value is executed (ST6). Here, the checksum operation is an 8-bit addition operation for the work area of the built-in RAM. When the checksum value is calculated, the calculation result is compared with the stored value at the SUM address in the RAM (ST7).

  In the SUM address, a checksum value obtained by the same checksum calculation is stored in the power supply monitoring process (ST20) executed when the voltage drops. The stored calculation result is maintained by a backup power source together with other data of the built-in RAM. Therefore, the two should be matched by the determination in step ST7.

  However, if the checksum operation cannot be executed when the power is turned off, or if it can be executed, but the work area data is damaged before the checksum operation (ST6) of the main process is executed. In such a case, the determination result in step ST7 is inconsistent.

  Therefore, if data corruption is detected due to a discrepancy in the determination results, the process proceeds to step ST8, RAM clear processing is executed, and the operation of the gaming machine is returned to the initial state. On the other hand, if it is determined in step ST7 that the checksum value obtained by the checksum calculation (ST8) matches the stored value at the SUM address, the process proceeds to step ST10 described above.

  Next, a timer interrupt processing program (FIG. 10) started every 4 ms with the main process described above being interrupted will be described. When the timer interrupt occurs, the power supply monitoring process is immediately executed without saving the CPU register (ST20). This is because the timing at which the timer interrupt process is started is fixed immediately after step ST13.

  In the power supply monitoring process (ST20), the level of the voltage drop signal supplied from the power supply board 20 is determined. If the level is abnormal, the backup flag BAKFLG is set to 5AH, the checksum value is calculated, and the SUM address is calculated. And wait for the power to be cut off.

  Next, a random number generating process for updating the winning counter RG used in the lottery process in the normal symbol process ST28 is executed (ST21). The winning counter RG is incremented (+1) within a predetermined numerical value range, and the updated counter value is utilized in the winning / not determining lottery process as a winning determination random value. Specifically, as the value of the winning counter RG, when the game ball passes through the gate 18, the winning counter RG is used in the winning lottery process in the normal symbol process (ST18).

  By the way, since the random number RND for lottery used for the jackpot lottery process in the special symbol process (ST32) is obtained from the random number generation circuit GNR, it is not updated by software processing. Therefore, also in this sense, in this embodiment, the storage capacity of the ROM can be saved, and other control processes can be enriched.

  In this specification, for convenience of explanation regarding the random number generation circuit GNR, the winning counter RG is updated by the process of step ST21. However, the update clock Φ is shared by the random number generation circuit GNR of the present embodiment. However, since it is possible to obtain a large number of random values whose numerical values are not related at all, it is actually preferable to eliminate the processing of step ST21, and in this case, the storage capacity of the ROM can be further saved.

  In any case, next, a timer subtraction process is performed for the timer that manages the game operation time (ST22). The timer to be subtracted manages the opening time of the special winning opening 16 and other game effect times.

  When such a timer subtraction process is completed, switch signals of various switches including the symbol start port 15 and the detection switch of the gate 18 are acquired and stored (ST23). The winning switch signal SG related to the symbol start port 15 is obtained by accessing the signal input register 35f of the random number generation circuit GNR. On the other hand, switch signals from other detection switches are obtained from the input port INP of the one-chip microcomputer. However, switch signals other than the winning switch signal SG can be passed through the signal input register 35f of the random number generation circuit GNR, and as described above, it is preferable.

  Then, for any switch signal, the current acquired value and the previous acquired value are compared, and it is determined and stored whether the transition has been made to the ON state or the OFF state. In the conventional gaming machine, as a countermeasure against noise, the determination of the ON transition and the OFF transition of the switch signal requires duplication determination over a plurality of interrupt processes, but in this embodiment, the random number generation circuit GNR includes a noise removal circuit. Since (FIG. 6C) is provided, it is not necessary to make a duplicate determination for the winning switch signal SG.

  That is, in the past, it was determined repeatedly for each interrupt process, and for example, it was determined that the winning switch signal SG has made an ON transition on the condition that it has transitioned from OFF to ON to ON. If the change from OFF to ON can be confirmed by the processing in step ST23, it can be determined that the winning switch signal SG has been turned ON. If the signal input register 35f is used, the same determination is sufficient for other switch signals.

  In this way, in this embodiment, it can be determined that the switch signal has made an ON transition 2 × τ after the switch signal has made an ON transition. For example, in order to make the control content complicated and sophisticated, the interrupt cycle is significantly increased. Even if it is set (τ >> 4 mS), there is no possibility that the winning switch signal SG and other switch signals are missed. In addition, the control program can be simplified by the amount that it is not necessary to perform duplication determination, and the amount of ROM consumed can be suppressed accordingly.

  When such switch input processing (ST23) is completed, error management processing is executed (ST24). The error management process means a determination as to whether an abnormality has occurred inside the device, such as whether or not the supply of game balls has stopped or the game balls are clogged.

  Further, it means a determination as to whether an abnormality has occurred in the random number generation circuit GNR. As described above, the presence / absence of abnormality of all N number sequence generators 33... 33 is stored in the status register 35e. Therefore, the CPU can determine whether the sequence generator 33 is operating normally only by reading the status register 35e. Each time the status register 35e is read, the status value returns to the normal level. If an abnormality is recognized in the sequence generator 33 by a plurality of interrupt processes, the abnormality is notified and the control operation is stopped. (ST40).

  When the error management process (ST24) is finished, next, after creating a control command for the payout control unit 33 (ST25), the control command generated at this stage is transmitted to the corresponding sub-control unit (ST26). .

  Subsequently, the normal symbol process is executed on the condition that the current operation mode is not the hit mode (ST28). The normal symbol process means a determination as to whether or not to operate an ordinary electric accessory, and when it is determined that the game ball has passed through the gate according to the switch input result in step ST23, a random number generation process (ST21). The winning counter RG updated in step) is compared with the winning winning value. If the comparison result is a winning state, the operation mode is changed to the winning operation mode. Further, if it is hit, processing for the operation of the ordinary electric accessory is performed (ST30).

  Next, a necessary control command is transmitted to the corresponding sub-control unit (ST31), and special symbol processing is performed (ST32). The special symbol process is a determination of whether or not to operate a special electric accessory such as the big prize opening 16, and is a process including a big hit lottery process.

  Specifically, when it is determined that the winning switch signal SG has been turned ON based on the switch input result in step ST23, the numerical value of the random number register 35a of the random number generation circuit GNR is acquired, and the random winning lottery randomness is obtained. Store as numeric RND. As an acquisition process in this case, a load instruction that can acquire 2-byte data with a single instruction (single fetch cycle) is used. For example, the load instruction LD AW, (HL) described in FIG. 7 is used, and prior to this, the load instruction LD HL, NN for the register numbers NN and NN + 1 that specify the random number register 35a is used.

  Further, the numerical value of the random number register 35c is acquired and stored as a random number value RND 'for symbol lottery. As described above, in this embodiment, the random number RND for jackpot lottery is 16-bit data in the numerical range (0 to 65535), and the random value RND ′ for symbol lottery is in the numerical range (0 to 199). ) 8-bit data. Therefore, the random number register 35c is accessed using LDA, (DE), which is a 1-byte load instruction.

  At this timing, when the symbol effect processing (the symbol variation processing of the symbol display portions Da to Dc) is completed and there is no preceding winning switch signal SG in the lottery pending state, the random value RND is set. The big hit lottery process is executed based on the random number value RND ′, and the symbol lottery is executed (ST32). In the winning state of the big hit lottery process, whether or not the game is a probable change and the number of special games rounds are determined by the symbol lottery process, and in the out of the big hit lottery process, the off symbol is determined by the symbol lottery process.

  Further, in the process of step ST32, the variation pattern command is determined by lottery including the specification of the stop symbol after the variation operation. The variation pattern command is a control command for effect operation transmitted to the effect control unit 22, and defines a symbol variation operation in the image control unit 23. This variation pattern command is stored in the command buffer by specifying the total time of effect operations such as reach effects as well as the success / failure result of the big win lottery. The variation pattern command stored in the command buffer is transmitted to the effect control unit 22 at the timing of subsequent step ST35.

  On the other hand, if this timing is during the symbol production process, the big hit lottery process will be in a standby state (lottery pending state), the running symbol production will end, and if the subsequent symbol presentation accompanying the big jackpot lottery ends, As the process of step ST32 at that timing, a lottery process using a random number value RND for jackpot lottery in a stored state or a random value RND ′ is executed.

  In any case, if the winning state is achieved by the big win lottery process of the special symbol process (ST32), the operation mode is changed to the big hit operation mode, and the process for the operation of the special electric accessory such as the big prize opening is performed (ST34).

  Next, the variation pattern command generated in step ST32 is transmitted to the effect control unit 22 (ST35), and the timer interrupt ends. As a result, the process returns to the process of the main routine (not shown), but when the predetermined time (4 mS) has elapsed, the process of step ST11 is started again, so that the processes of steps ST20 to ST35 are repeated every 4 mS. It will be.

  In the embodiment described above, the ON transition of the winning switch signal SG is determined based on the value of the signal input register 35f (ST23), and when the winning switch signal SG makes an ON transition, Two types of random values RND and RND ′ are obtained from the random number registers 35a and 35c (ST32), and the program load is minimized in that the latch registers 35b and 35d and the status register 35e are not accessed. Moreover, it is also excellent in that the value generated by the sequence generator 33 at the latest timing when the winning switch signal SG is turned ON can be acquired.

  However, it is not limited to such a configuration, and can be changed as appropriate. For example, it is also preferable to obtain a plurality of types of random values RND, RND ′,... From a latch register (35b, 35d, etc.) set in the overwrite prohibition mode or the overwrite permission mode. In this case as well, for the 16-bit latch register (35b), a 2-byte random number value is acquired at once by an instruction such as LDWA, (HL).

  Further, the ON transition of the winning switch signal SG is not necessarily determined based on the value of the signal input register 35f, and may be determined based on, for example, the status value (latch information) of the status register 35e. That is, in the present embodiment, the same reliable noise countermeasure as that applied to the signal input register 35f is taken, and then the latch pulse LT is output (see FIG. 6A (d)). Therefore, in addition to the status register 35e, There is no particular need to access the input register 35f.

  However, in order to prevent an operation in which the latch registers (35b, 35d, etc.) are accessed repeatedly while the ON state of the winning switch signal SG is continued, it corresponds to the ON edge of the winning switch signal SG. It is preferable to access the latch registers (35b, 35d, etc.). That is, in order to detect the ON edge of the winning switch signal SG, it is preferable to access the signal input register 35f in addition to the status register 35e.

  In the case of adopting a configuration for accessing the signal input register 35f, the status value (latch information) of the status register 35e can be cleared when the OFF edge of the winning switch signal SG is detected, and the latch registers (35b, 35d). Etc.) will not cause any problems when used in overwrite protection mode.

  The embodiment of the present invention has been described in detail above, but the specific circuit configuration and program processing can be changed as appropriate, and the present invention is not particularly limited. For example, in the circuit configuration of FIG. 5B, the D latch 50 is controlled by the output of the OR gate 52, but the OR gate 52 is omitted and the D latch 50 is controlled by the control signal MREQ and the control signal RD. You may do it.

The uses of the 16-bit fixed length / variable length sequence generator FCT ₁₆ and the 8-bit fixed length / variable length sequence generator VCT ₈ are not limited to those described above, and various applications are possible. For example, based on the special symbol lottery process (ST32), using a sequence generator VCT ₈ identical or different stream generators VCT ₈ used in the preceding examples, the numerical value thereof stream generators VCT ₈ generates Thus, the variation pattern command can be determined by lottery.

In this case, if the number of variation pattern commands and the numerical range of the numerical sequence generated by the sequence generator VCT ₈ are set to be the same, the winning rates of the respective variation patterns can be made the same. Conversely, if the numerical value range of the sequence generator VCT ₈ is expanded from the number of variation pattern commands, the winning rate can be set appropriately for each variation pattern by making the winning rate of each variation pattern non-identical. it can.

Also, assuming such sort lottery, based on the numerical value generated by the 16-bit variable-length sequence generator FCT ₁₆ , the decision of the variation pattern command and the symbol lottery that prescribes whether or not the probability variation is a probability variation is executed. It is also suitable to do. When the sequence generator FCT ₁₆ is used, the generated numerical range is wide, so that, for example, a fine sorting lottery can be performed based on random numbers in the numerical range of about 1000.

  In the embodiment of FIG. 10, the normal symbol processing (ST28) is performed based on the software counter (the winning counter RG) for convenience of explanation. However, it is preferable to use the acquired value from the random number generation circuit GNR. As described above.

In this case, as the random number used in the lottery process in the normal symbol processing ST28, numerical fixed length / variable length generated by the sequence generating unit CT ₈ and stream generators CT ₁₆ is utilized. The numerical values of the 8-bit variable length and the 16-bit variable length are used, for example, for the purpose of determining the normal symbol displayed on the normal symbol display unit 19 and other purposes.

  As another application, for example, a lottery determination of an open pattern of an electric tulip (electric chew) can be considered. In this case, there are many types of electric chew release patterns that are appropriately combined with the number of times of opening (3/4 times) and the opening time (3 seconds / 5 seconds). Sometimes one of them is decided by lottery.

  In the embodiment, the ON / OFF state of the winning switch signal SG is determined on the basis of the stored value of the signal input register 35f. However, if the winning switch signal SG is supplied to the normal input port INP, Based on the acquired value from the input port INP, the ON / OFF state of the winning switch signal SG can be determined.

  In such a case, it is not always necessary to supply the winning switch signal SG to the random number generation circuit GNR, and when it is determined that the winning switch signal SG is in the ON state, the numerical values of the random number registers 35a and 35c are acquired. Thus, a random number for lottery may be used. When determining that the winning switch signal SG acquired from the input port INP is in an ON state or an OFF state, it is determined that the winning switch signal SG is at the same level in a plurality of interrupt processes as a noise countermeasure. It is good as a condition.

  In any case, if the winning switch signal SG is not supplied to the random number generation circuit GNR, the latch circuit 34G and the latch registers 35b and 35d do not function, but in this embodiment, the outputs of the sequence generators 41a and 41b are output. Since the random number registers 35a and 35c to be received are provided, no problem occurs.

  In the embodiment shown in FIG. 10, in the special symbol process (ST32), the values of the random number registers 35a and 35c of the random number generation circuit GNR are acquired and the lottery process is executed. However, instead of the random number registers 35a and 35c, Of course, the numerical values of the latch registers 35b and 35d may be used. In this case, as in the embodiment shown in FIG. 10, the winning switch signal SG related to the symbol starting port 15 is preferably obtained by accessing the signal input register 35f of the random number generation circuit GNR (see ST23).

  FIG. 11 is a diagram for explaining an embodiment in which the values of the latch registers 35b and 35d are acquired and the lottery process is executed. The time charts of FIGS. This is a summary of permission modes. In the illustrated example, the value of the latch registers 35b and 35d is acquired by the CPU after the winning switch signal SG is turned off (see the lower right end read in FIG. 11), but is not particularly limited.

  To explain the above, when the winning switch signal SG (FIG. 11A) is in the ON state, the latch pulse LT is output, for example, every 128 (= 128τ) of the update clock Φ (FIG. 11). (D)). Further, the ON / OFF level of the winning switch signal SG is stored in the signal input register 35f after a delay time of about 128 update clocks Φ (≈128τ), for example. If the frequency of the update clock Φ is 10 MHz, the delay time is approximately 12.8 μS.

  Therefore, when the signal input register 35f is repeatedly accessed periodically, the ON edge of the stored value is confirmed, and the latch data of the latch registers 35b and 35d is read immediately (see ST23 and ST32 in FIG. 10). Can obtain a random value at a timing (+12.8 μS) very close to the ON edge of the winning switch signal SW. This is because the update value (numerical value X or numerical value) of the sequence generator 41 shown in FIG. 11 (f) or FIG. 11 (g) regardless of whether the operation mode is the overwrite prohibiting mode or the overwrite permitting mode. Y) is acquired by the CPU as a random number value for lottery.

  In addition, as confirmed from the relationship of FIG. 11D, FIG. 11E, and FIG. 11F, in the overwrite prohibition mode, the first latch pulse can be obtained no matter how late the acquisition timing of the CPU random number value is. The update value X of the timing of LT is acquired.

  Here, the configuration has been described in which the signal input register 35f is repeatedly accessed periodically, the ON edge of the stored value is confirmed, and the special symbol processing (ST32) is executed. The special symbol process (ST32) may be executed on condition that the OFF edge of the stored value of the register 35f is confirmed.

  In the case of adopting the overwrite prohibition mode, even with such a configuration, it is possible to acquire a random value (numerical value X) at a timing (+12.8 μS) very close to the ON edge of the winning switch signal SW. On the other hand, when the overwrite permission mode is adopted, a random value (numerical value Z) at a timing very close to the OFF edge of the winning switch signal SW can be acquired.

  When the configuration for confirming the OFF edge of the stored value of the signal input register 35f is adopted, the winning switch signal SG (FIG. 11 (a)) regardless of whether the mode is the overwrite prohibition mode or the overwrite permission mode. Since the status value (latch information) of the status register becomes OFF level after the signal has fallen reliably (see the read timing in FIG. 11 (h)), the latch can be latched no matter how long the winning switch signal SG is ON. There is no possibility of accessing the registers (35b, 35d, etc.) redundantly. That is, since the latch pulse LT is not output after the random number acquisition timing by the CPU (read in FIG. 11), the status value (latch information) of the status register 35e is not turned on again, and therefore There is no risk of duplicate execution of random number acquisition processing.

  The application of the present invention is not limited to a ball game machine, and can be applied to various game machines including a spinning machine.

GM gaming machine 21 main control means 21A one-chip microcomputer SG switch signal CLK system clock XCLK external clock GNR random number generation means 33G numerical value update means 34G random number acquisition means 36 abnormality detection means 41b normal circuit 41a special circuit

Claims (1)

A gaming machine that executes a lottery process due to a predetermined switch signal and executes a game control operation corresponding to a lottery result,
The main control means for executing the game control operation including the lottery process generates a ROM for storing the control program and fixed data in a nonvolatile manner, a RAM for storing work data in a volatile manner, and a random value for the lottery process. Comprising a one-chip microcomputer with a built-in random number generating means and a CPU that operates in response to a system clock,
The random number generating means includes a numerical value updating means for repeatedly updating the numerical value based on a system clock or other external clock, and a random number capable of obtaining the numerical value of the numerical value updating means when the switch signal is in an ON state. Obtaining means,
When the switch signal of the signal acquisition means for receiving the switch signal is in an ON state, the numerical value is acquired from the random number acquisition means or the numerical value update means,
The numerical value updating means receives the update clock generated based on the system clock or other external clock, and generates based on the system clock and a first circuit for updating the numerical value in a numerical range of 0 to 2 ⁿ −1. And a second circuit that updates the numerical value within a numerical range of 0 to MAX that is within a numerical range of 0 to 2 ⁿ -1 and that does not exceed a preset maximum value MAX. Configured,
A determination unit that repeatedly determines the switch signal received by the signal acquisition unit every predetermined time; and a lottery unit that executes the lottery process based on the determination unit determining the ON state of the switch signal,
The lottery process includes a first process executed based on a generated value of the first circuit and a second process executed based on a generated value of the second circuit, and the result of the first process The special gaming state control operation is executed based on the result of the second process,
A gaming machine in which the second circuit is configured to start an updating operation on condition that a maximum value MAX is set .

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