JP4704444B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a ball ball game machine or a slot machine that generates a big hit state by a lottery process caused by a gaming operation, and more particularly to a gaming machine that facilitates an operator's switch operation.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7-7-7, a big hit state is established, and the big winning opening is repeatedly opened to generate a profit state advantageous to the player.

Many of these gaming machines are provided with a backup function, and even after the AC power supply is shut off due to the end of business or due to a power failure, the memory contents are maintained so that the power supply is turned on after the next power-on. The game operation before the interruption can be resumed (Patent Document 1). However, there may be cases where you do not want to carry over the previous day's gaming operation, such as when the previous day's business was closed, so you can also execute RAM clear processing to erase the memory contents by turning on the initialization switch by the staff. It is configured as follows. Note that the initialization switch needs to be turned on prior to turning on the power switch, and after the power is turned on, it needs to be kept on until the gaming machine confirms the turn-on operation.
Japanese Patent Application No. 2007-184849

  Also, this type of gaming machine includes a main control board that outputs a control command to centrally control gaming operations, a payout control board that executes a payout operation of prize balls based on the control commands, and the control Generally, it is composed of one or a plurality of effect control boards that execute individual effect operations based on commands. In the gaming machine having such a configuration, the main control board and the other control board synchronize and match each other's control operations by, for example, processing as shown in FIG.

  In the main control board, after finishing the initial setting process (ST90), the main control board waits for the effect control board to normally start up (ST91). This is because if the control command is transmitted before the production control board is activated, the control command is missed. Next, it waits to receive a preparation completion signal ACK from the payout control board (ST92). This standby process is also for preventing the control command transmitted to the payout control board from being read out.

  After such standby processing (ST91, ST92), whether or not the initialization switch is turned on by an attendant is checked (ST93), and if the ON operation is confirmed, the stored contents of the RAM are erased. Is transmitted to an effect control board or the like. At this stage, the production control board has finished the initial processing of the liquid crystal display control dedicated IC and the voice control dedicated IC, so that, for example, an appropriate design can be displayed on the liquid crystal display screen, or an appropriate voice can be displayed. The notification process can be executed.

  By the way, in recent gaming machines, the production operation has become more complex and sophisticated in order to meet the demands of the player, so it takes a considerable amount of time (for example, 2 seconds) to initialize the dedicated IC for production control mounted on the production control board. It is the actual situation that requires a degree.

  Therefore, if the operation of the initialization switch by the attendant at the game hall is inappropriate, the RAM clear process is not executed as intended, and the same operation needs to be performed again. That is, at the timing when the gaming machine checks the switch operation (ST93), if the initialization switch is returned to the OFF state, the switch operation is ignored, so it is necessary to start again from turning on the power switch. And in order to avoid such a situation, the initialization switch must be continuously turned on for more than 2 seconds, which is a heavy work load for a staff member who needs to manage a large number of gaming machines. .

  In addition, when the backup function is provided not only on the main control board but also on other control boards, if the ON operation of the initialization switch is read out on any of the control boards, the operation of the entire gaming machine Consistency is lost and the corner backup function can be spoiled.

  Furthermore, it would be great if the main control board did not consume time for the initialization of a dedicated IC for voice production and design production, but could effectively use the standby time.

  The present invention has been made based on the above-mentioned problems and ideas, and an object thereof is to provide a gaming machine that facilitates the operation of a switch such as an initialization switch. It is another object of the present invention to provide a gaming machine that effectively uses the waiting time that occurs when the power is turned on.

To achieve the above object, the present invention executes a lottery process for determining whether or not a game state advantageous to a player is generated, and controls the game operation centrally based on the lottery result. And a sub-control unit that executes individual control operations based on a control command from the main control unit, and at least a backup function that maintains the stored contents even after the power supply voltage is shut off. a game machine provided in the control unit, together with the response to oN operation of the initialization switch configured to erase the stored contents of the memory, provided the holding circuit for storing the oN operation of the initialization switch, storage The holding circuit includes a signal input terminal that receives an input signal of a fixed level, a clock terminal that receives a clock signal that defines the storage timing of the input signal, an output terminal that outputs the stored input signal, and an output terminal A latch circuit that receives a clear signal that resets the power to the initial state, and a power source that resets the output terminal of the latch circuit to the initial state by supplying the clear signal to the clear terminal for a predetermined time after power-on. A reset circuit, and after the power is turned on, the latch circuit clear terminal receives a clear signal from the power reset circuit, so that the output terminal of the latch circuit is automatically reset to the initial state, When the initialization switch operation signal is supplied to the clock terminal of the latch circuit, the fixed level input signal supplied to the signal input terminal is input to the latch circuit at the timing when the initialization switch that has been turned ON returns to the OFF state. After that, the output terminal of the latch circuit is maintained at a fixed level .

  According to the present invention described above, the gaming machine does not miss the ON operation regardless of whether the switch operation is appropriate.

  Hereinafter, embodiments of the present invention will be described in detail. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side rather than from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. An upper plate 8 for storing game balls for launch is mounted on the front plate 7, and a lower plate 9 for storing game balls overflowing from or extracted from the upper plate 8 and a launch handle 10 are mounted at the bottom of the front frame 3. And are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, the game board 5 is provided with a guide rail 13 formed of a metal outer rail and an inner rail in an annular shape, and a liquid crystal color display DISP is provided at the approximate center of the game area 5a inside. Has been placed. In addition, right and left two symbol start openings 15A and 15B, a single large winning opening 16, four left and right normal winning openings 17, and a gate 18 which is two right and left passing openings are provided at appropriate positions in the game area 5a. It is arranged. Each of these winning openings and gates 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  In the lower part of the liquid crystal display DISP, special symbol display parts SPa and SPb composed of a 7-segment LED or a dot matrix are provided. Two special symbol display portions are provided corresponding to the left and right symbol start openings 15A and 15B, and the lottery result of the big hit lottery executed on condition that the game balls win the respective symbol start openings 15A and 15B This is a display unit for clearly indicating. Each special symbol display part SPa, SPb starts the changing operation of the display contents when a game ball wins in the corresponding symbol start opening 15A, 15B, and then stops by displaying a lottery result as to whether it is a big hit state or not. It is like that. As shown in the figure, when the special symbol display portions SPa and SPb are composed of 7-segment LEDs, any special symbol (for example, “1” to “9”) is displayed in the big hit state, and there is a loss state. "-" Is displayed.

  Under the special symbol display portions SPa and SPb, two lottery holding number display portions 14A and 14B each constituted by four LED lamps are provided corresponding to the symbol start openings 15A and 15B. The lottery hold number display portions 14A and 14B indicate that more game balls have been won at the symbol start ports 15A and 15B during the changing operation of the special symbol display portions SPa and SPb. The winning prize is stored, and the subsequent big hit lottery process is put on hold.

  In the case of the present embodiment, the liquid crystal display DISP does not function as a special symbol display unit, but functions as an effect symbol display unit that variably displays effect symbols. And the effect operation | movement synchronized with special symbol display part SPa or special symbol display part SPb is performed. Specifically, the effect symbol related to the big hit state (simply the same “1” to “9” as the special symbol) is variably displayed, and background images and various characters are animatedly displayed. .

  A normal symbol display unit 19 is provided in the upper right part of the liquid crystal display DISP. The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the displayed normal symbol fluctuates for a predetermined time and is extracted at the time when the game ball passes through the gate 18. The stop symbol determined by the random number for lottery is displayed and stopped. If the game ball passes through the gate 18 during the normal symbol variation operation, the start of the variation operation is suspended up to four.

  The special winning opening 16 is controlled to open and close by, for example, an opening / closing plate 16a that can be opened forward, but the stop symbols of the special symbol display portions SPa and SPb and the effect symbol display portion DISP are “7” and “7 / 7.7”. In the case of a special symbol such as, a special game called “big hit” is started, and the opening / closing plate 160 is opened.

  After the opening / closing plate 16a of the big prize opening 16 is opened, the opening / closing plate 16a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. In such an operation, the special game is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display unit is a specific symbol of the special symbols, a privilege that the game after the end of the special game is in a high probability state is given.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations. A dashed line in the figure mainly indicates a DC voltage line. FIG. 4 shows in detail the connection relationship between the power supply board 20, the main control board 21, and the payout control board 24 for the circuit configuration of the pachinko machine GM. In FIG. 4, the description of the main circuit board 28, the buffer circuits to be connected to the input ports IN2 to IN4 and the output ports OUT1 and OUT3 is omitted.

  As shown in FIG. 3 and FIG. 4, this pachinko machine GM centralizes the game control operation and the power supply board 20 that receives various AC voltages and outputs various DC voltages, system reset signals (power reset signals) SYS, and the like. The main control board 21 responsible, the effect control board 22 for executing the lamp effect and the sound effect based on the control command CMD received from the main control board 21, and the liquid crystal display based on the control command CMD 'received from the effect control board 22 A liquid crystal control board 23 that drives the DISP, a payout control board 24 that controls the payout motor M based on a control command CMD "received from the main control board 21, and pays out a game ball. It is mainly composed of a launch control board 25 that launches game balls.

  However, in this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the command relay board 26 and the effect interface board 27. Further, the control command CMD ′ output from the effect control board 22 is transmitted to the liquid crystal control board 23 via the effect interface board 27, and the control command CMD ″ output from the main control board 21 is set to the main board relay board 28. Is transmitted to the payout control board 24 via.

  The main control board 21, the effect control board 22, the liquid crystal control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer. Accordingly, the circuits mounted on the control boards 21 to 24 and the operations realized by the circuits are collectively referred to as a function. In this specification, the main control unit 21, the effect control unit 22, and the liquid crystal control unit 23 are used. , And the payout control unit 24. All or part of the effect control unit 22, the liquid crystal control unit 23, and the payout control unit 24 is a sub-control unit.

  By the way, the pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and the new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame-side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, and a frame relay board 32, and these circuit boards are Each is fixed in place on the front frame 3. On the other hand, on the back of the game board 5, a main control board 21, an effect control board 22, and a liquid crystal control board 23 are fixed together with a liquid crystal display DISP and other circuit boards.

  And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place. In this embodiment, the connection connectors C1 to C4 are concentrated in the lower left of the game board 5 as viewed from the back. Then, with the glass door 6 open, the left end of the game board 5 is locked to the front frame 3 from the front side of the front frame 3 to secure a rotation fulcrum, and the game board 5 is rotated around the secured rotation fulcrum. By doing so, the game board 5 is fitted inside the front frame 3. When the game board 5 is fitted, all the connection connectors C1 to C4 are connected, and the connection between the frame side member GM1 and the board side member GM2 is completed, and the pachinko machine GM is operable. .

  As shown in FIG. 3, the power supply board 20 is connected to the main board relay board 28 through the connection connector C2, and is connected to the power supply relay board 30 through the connection connector C3. The main board relay board 28 outputs the system reset signal SYS, the RAM clear signal DEL, the voltage drop signal DWN, the backup power supply BU, DC12V, and DC32V received from the power board 20 to the main controller 21 as they are. Similarly, the power supply relay board 30 also outputs the system reset signal SYS received from the power supply board 20 and the AC and DC power supply voltages to the effect interface board 27 as they are. The production interface board 27 outputs the received system reset signal SYS to the production control unit 22 and the liquid crystal control unit 23 as they are.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and the system reset signal SYS, the RAM clear signal DEL, the voltage drop signal DWN, the backup, which are received by the main control unit 21. The power supply BU is directly received together with other power supply voltages (see FIG. 4).

  Here, the system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V is turned on to the power supply board 20, and the one-chip microcomputers of the respective control units 21 to 24 by this power supply reset signal. The other IC elements are reset in power supply.

  The RAM clear signal DEL received from the power supply board 20 by the main control unit 21 and the payout control unit 24 is a signal that determines whether or not to initialize all areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. Therefore, it has a value corresponding to the ON / OFF state of the initialization switch SW operated by the attendant. When the initialization switch SW is turned ON, the RAM clear signal DEL becomes L level, and when the hand is released from the initialization switch SW, the RAM clear signal DEL returns to H level.

  As shown in FIG. 4, the main control unit 21 acquires the RAM clear signal DEL from the input port IN <b> 1 via the memory holding circuit (signal latch circuit) 45. On the other hand, the payout control unit 24 acquires the RAM clear signal DEL directly from the input port IN3. In practice, it goes without saying that the data is routed through a buffer circuit.

  The voltage drop signal DWN received from the power supply board 20 by the main control unit 21 and the payout control unit 24 is a signal indicating that the AC power supply 24V has started to drop. By receiving this voltage drop signal DWN, each control unit In 21 and 24, necessary end processing is started prior to a power failure or business end. The backup power source BU is a DC 5V DC power source that retains data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power source 24V is cut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 25 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  On the other hand, the effect control unit 22 and the liquid crystal control unit 23 are not provided with the power supply backup function described above. However, as described above, the system reset signal SYS is commonly supplied to the effect control unit 22 and the liquid crystal control unit 23 via the power relay board 30 and the effect interface board 27, and other controls are performed. The power supply reset operation is realized at a timing substantially synchronized with the units 21 and 24.

  As shown in FIG. 4, the main control unit 21 transmits a control command CMD ″ from the output port OUT1 to the input port IN4 of the payout control unit 25 via a buffer circuit (not shown). On the other hand, the payout control unit 25 sends a prize ball counting signal indicating a payout operation of a game ball from the output port OUT3 to the input port IN2 of the main control unit 21 via a buffer circuit (not shown) A completion signal ACK indicating that the initial processing after the input is completed and a status signal CON related to an abnormality in the payout operation are transmitted, for example, a replenishment out signal, a payout shortage error signal, a lower plate A full signal is included.

  The main control unit 21 is connected to each game component of the game board 5 via the game board relay board 29. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The switch signal includes two systems of winning switch signals SWa and SWb transmitted from the symbol start ports 15A and 15B to the main control unit 21 (see FIG. 6A).

  FIG. 5 is a circuit diagram showing, in particular, a random number generation circuit in the circuit configuration of the main control unit 21. The random number generation circuit is closely related to the random value RND used in the big hit lottery process executed when the game ball is won at the symbol start openings 15A and 15B. A random value RND is generated based on the switch signals SWa and SWb.

  As shown in the figure, the random number generation circuit includes a one-chip microcomputer 21A having an input port IN and an output port OUT, an oscillation circuit 40 for generating a counting clock Φ, and two winning switch signals SWa from the symbol start ports 15A and 15B. , SWb, an OR gate group 41 for receiving test pulses TSa, TSb output from the one-chip microcomputer 21A and winning switch signals SWa, SWb output from the buffer BUF, and an output signal SGa, of the OR gate group 41 Winning latch circuit 42 that temporarily holds SGb, two series of counting circuits 43 that count the counting clock Φ, an abnormality detection circuit 44 that detects an abnormality in the counting operation of the counting circuit 43, and a RAM clear signal received from the power supply substrate 20 And a signal latch circuit 45 that holds DEL.

  The winning switch signals SWa and SWb supplied to the OR gate group 41 are also supplied to the input port IN1 of the one-chip microcomputer 21A, and the CPU core performs a periodic switch input process to the symbol start ports 15A and 15B. The ON state of the switch signal is grasped redundantly. Then, the CPU core that grasps the ON state of the winning switch signals SWa and SWb acquires the 16-bit data of the counting circuit 43 and sets it as the random value RND for the big hit lottery. The 16-bit data is acquired every 8 bits corresponding to the processing capability of the CPU core.

  The oscillation circuit 40 is composed of a crystal oscillation circuit OSC that oscillates a high-frequency pulse of about 25 MHz and a D-type flip-flop FF1 wired in a toggle manner. Then, the output signal of the crystal oscillation circuit OSC is supplied to the clock terminal CLK of the D-type flip-flop FF1, so that the oscillation frequency is divided by two to become a count clock Φ having a frequency of about 12.5 MHz.

  The winning latch circuit 42 includes two D-type flip-flops FF2 and FF3. Output signals SGa and SGb that have passed through the OR gate group are supplied to the D input terminals of the flip-flops FF2 and FF3, respectively. On the other hand, an inverted count clock Φ ′ is supplied to the clock terminals CLK of the flip-flops FF2 and FF3. Therefore, the value of the D input terminal (that is, the level value of the output signals SGa and SGb) at the signal edge of the inverted count clock Φ ′ is acquired by each of the flip-flops FF2 and FF3 in synchronization with the inverted count clock Φ ′. .

  The counting circuit 43 includes two systems of 16-bit counters CTa and CTb, two latches (count value holding circuits) Ra and Rb each receiving the outputs of the counters CTa and CTb, and outputs of the latches Ra and Rb. The output register Ro outputs 8-bit data selected by the control signal CTL. The 16-bit counters CTa and CTb are both ripple counter type binary counters. The carry signal CYa of the 16-bit counter CTa is output as the detection pulse PL.

  A latch clock RCK which is a Q output signal of the flip-flops FF2 and FF3 is supplied to the first latch Ra and the second latch Rb. In synchronization with the edge of the latch clock RCK, the count values of the counters CTa and CTb at that time are acquired by the latches Ra and Rb having a 16-bit length, and the values are held until the next latch clock RCK is received.

  The output register Ro operates based on the control signal CTL output from the one-chip microcomputer 21A. The control signal CTL is 4-bit data for output switching. The upper 8 bits of the first latch Ra, the lower 8 bits of the first latch Ra, the upper 8 bits of the second latch Rb, and the lower 8 bits of the second latch Rb. Is selected and output to the data bus of the one-chip microcomputer 21A. Note that the output of the output register Ro is one of three states of H level, L level, and high impedance.

  The abnormality detection circuit 44 includes a D-type flip-flop FF4 wired in a toggle manner and a watchdog circuit 46. The detection pulse PL output from the counting circuit 43 is supplied to the clock terminal CLK of the D-type flip-flop FF4. Therefore, an output pulse obtained by dividing the detection pulse PL by two is output from the Q output terminal of the D-type flip-flop FF4.

  In this embodiment, TA8030S (TOSHIBA), which is a dedicated IC, is used as the watchdog circuit 46. In the watchdog circuit 46, when the clear pulse received at the clear terminal WD is interrupted, the oscillation circuit including the resistor R1 and the capacitor C1 enters a free-running state, and a pulse signal is output from the output terminal RST1. However, in a state where a regular clear pulse is supplied to the clear terminal WD, the output terminal RST1 maintains the H level.

  As shown in the drawing, the detection pulse PL divided by two is supplied to the clear terminal WD of the watchdog circuit 46 via the differential capacitor C3. Therefore, in the normal state where the counter CTa periodically outputs the carry signal CYa, the detection pulse PL functions as a clear pulse, so that the output terminal RST1 of the watchdog IC 46 maintains the H level. On the other hand, when the counter CTa stops the counting operation, the clear pulse (detection pulse PL) is interrupted, so that a pulse signal (abnormality detection signal ABN) is output from the output terminal RST1 of the watchdog IC 46 in the self-running state.

  This abnormality detection signal ABN is supplied to the input port IN1 of the one-chip microcomputer 21A via a waveform shaping circuit by two NOT gates G3 and G4. Therefore, the one-chip microcomputer 21A can grasp the abnormality of the random number generation circuit by periodically determining the level of the abnormality detection signal ABN. Since the output values of the counters CTa and CTb of the random number generation circuit are used as the random value RND of the big hit lottery process, it is extremely important that the output value is updated at high speed as designed, and the abnormality detection circuit 44 has great significance.

  The signal latch circuit (memory holding circuit) 45 is configured around a D-type flip-flop FF5 whose D input terminal is fixed at the H level. The Q bar output of the D flip-flop FF5 is supplied to the input port IN1 of the one-chip microcomputer 21A. The clock terminal CLK is pulled up by the resistor R4 and receives the RAM clear signal DEL from the power supply substrate 20. In the flip-flop FF5, the H level data of the D input terminal is held in the Q output terminal in synchronization with the rising edge of the RAM clear signal DEL supplied to the clock terminal CLK.

  The RAM clear signal DEL becomes the L level when the clerk presses the initialization switch SW, and becomes the H level when the hand is released. Therefore, an L level signal is supplied to the input port IN at the timing when the clerk releases the initialization switch SW, and the one-chip microcomputer 21A accesses the input port IN1 to Thus, the ON operation of the initialization switch SW can be grasped.

  The clear terminal CLR of the D flip-flop FF5 is connected to the output port OUT2 of the one-chip microcomputer 21A. The clear terminal CLR of the D-type flip-flop FF5 is grounded through the capacitor C2 and the resistor R2, and receives the power supply voltage through the resistor R3. Here, the capacitor C2 and the resistors R2 and R3 constitute a power reset circuit, and the D-type flip-flop FF5 is automatically reset when the gaming machine is turned on. As a result, the Q-bar output of the D-type flip-flop FF5 becomes H level, and this H level is maintained unless the staff operates the initialization switch SW.

  On the other hand, when the clerk turns ON the initialization switch SW, the Q bar output of the D-type flip-flop FF5 changes from the H level to the L level, and this state is maintained. Therefore, when necessary, the D-type flip-flop FF5 is returned to the initial state by outputting an L level pulse signal from the output port OUT of the one-chip microcomputer 21A.

  Thus, in the present embodiment, the flip-flop FF5 that temporarily holds the RAM clear signal DEL is particularly provided. Therefore, even if the elapsed time from when the gaming machine is turned on until the one-chip microcomputer 21A checks the RAM clear signal DEL is long, there is no possibility of missing the ON operation of the initialization switch SW. Further, the RAM clear signal DEL can be surely acquired even if the ON operation of the initialization switch SW by the attendant is inappropriate and the operator quickly releases the switch.

  The reason why the power supply reset circuit is provided in relation to the flip-flop FF5 is to quickly reset the power supply of the flip-flop FF5. Therefore, the flip-flop FF5 can correctly acquire the RAM clear signal DEL even when the attendant quickly releases his hand from the initialization switch SW. On the other hand, the other flip-flops FF1 to FF4 and the counting circuit 43 are simultaneously reset in synchronization with the power reset signal (system reset signal) SYS.

  The flip-flop FF5 may also be reset by the power reset signal SYS from the power supply board 20, but in this case, the RAM clear signal DEL returns to the H level before the rising timing of the power reset signal SYS. Then, the ON operation is missed.

  FIG. 6A shows in detail the connection relationship among the buffer BUF, the OR gate group 41, the output port OUT2, and the input port IN1. The output port OUT2 outputs inspection pulses TSa and TSb. Here, the inspection port TS2 is output from bit0 of the output port OUT2, and the inspection pulse TSb is output from bit1 of the output port OUT2.

  The buffer BUF is an interface circuit that converts sensor outputs from the two proximity switches SW1 and SW2 into TTL (Transistor transistor logic) level signals SWa and SWb. Therefore, + 12V for proximity switches SW1 and SW2 and + 5V for winning switch signals SWa and SWb are supplied to this IC.

  The proximity switch is configured to include a high-frequency oscillation circuit and a detection coil. When the game ball passes through the detection coil, the proximity switch is configured to output an ON signal based on a change in impedance at that time (FIG. 6B). )reference). Upon receiving the ON signal, the buffer BUF outputs TTL level winning switch signals SWa and SWb.

  The OR gate group is composed of two OR gates G5 and G6. To the OR gate G5, the winning switch signal SWa and the inspection pulse TSa are supplied, and an output signal SGa logically ORed is output. On the other hand, the winning switch signal SWb and the inspection pulse TSb are supplied to the OR gate G6, and an output signal SGa logically ORed is output.

  Next, an outline of a program of the main control unit 21 that controls the game operation in an integrated manner will be described. FIG. 7 is a flowchart showing a control program of the main control unit 21. The control program of the main control unit 21 includes a system reset process (FIG. 7) that is activated based on the restoration or input of the power supply voltage, and a maskable timer interrupt process (FIG. 9 (FIG. 9 ( a)). Note that a Z80 CPU (Zilog) equivalent product is built in the one-chip microcomputer 21A that realizes these processes. The one-chip microcomputer 21A also has a built-in watchdog timer, and is configured to forcibly reset the CPU when periodic clear processing is interrupted.

  Hereinafter, the system reset processing program (main processing) will be described with reference to FIG. The main process is started when the initialization switch SW is turned off and the power is turned on, such as when recovering from a power failure, and when the game hall is opened, the initialization switch SW is turned on. There is a case where the power source is turned on by being operated. Note that the runaway of the control program may start the watchdog timer and forcibly reset the CPU.

  In any case, the Z80 CPU first sets itself to the interrupt disabled state (ST71) and sets to the interrupt mode 2 (ST72). Further, the value of the stack pointer SP in the CPU is initialized to the final address of the stack area (ST73), and the values of internal registers including each part of the one-chip microcomputer are initialized (ST74).

  Next, it is examined whether or not the random number generation circuit shown in FIG. 5 is operating normally (ST75). Specifically, as shown in the time chart of FIG. 6B, it is determined whether the random number generation circuit is operating normally by outputting repeated inspection pulses TSa and TSb.

  The program processing for realizing this operation is as shown in FIG. 8. First, a variable CNT that counts the number of wins, a variable NUM that counts the number of inspections, and an abnormality flag FG that is set at the time of abnormality are initialized to 0 Set (ST50). The variables CNT and NUM function as a 16-bit counter.

  When the above processing setting is completed, first, an H level signal is output to bit0 of the output port OUT2 (ST51). As a result, the inspection pulse TSa rises, and the value of the counter CTa at that moment is held in the first latch Ra. Next, the output switching signal CTL is output to the counting circuit 43, and the value of the first latch Ra is acquired from the output register RO and stored (ST52). Since the stored value is the count value of the counter CTa, subsequently, an L level signal is output from bit 0 of the output port OUT2, and the inspection pulse TSa is lowered to the L level (ST53).

  Then, it is determined whether the count value of the counter CTa stored in the process of step ST52 is in a winning state (ST54). In this embodiment, since the circulation range of the counters CTa and CTb is 0 to 65535, the numerical range to be in the winning state is, for example, 10001 to 10210. Therefore, in step ST54, it is determined whether or not the acquired count value of the counter CTa is included in the winning range of 10001 to 10210. And if it is a winning state, the variable CNT is incremented (ST55), and if it is a disengaged state, the process of step ST55 is skipped.

  Subsequently, this time, an H level signal is output from bit1 of the output port OUT2 (ST56), the inspection pulse TSb rises, and the value of the counter CTb at that moment is held in the second latch Rb. Next, the output switching signal CTL is output to the counting circuit 43, and the count value of the counter CTb, which is the value of the second latch Rb, is acquired from the output register RO and stored (ST57). Further, an L level signal is output from bit 1 of the output port OUT2, and the inspection pulse TSb falls to the L level (ST58).

  Then, it is determined whether or not the count value of the counter CTb stored in the process of step ST57 is included in the winning range of 10001 to 10210 (ST59). And if it is a winning state, the variable CNT is incremented (ST60), and if it is a disengaged state, the process of step ST60 is skipped.

  As a result of the above processing, since one inspection process is completed for the two counters CTa and CTb, the variable NUM is incremented (ST61). Then, it is determined whether or not the 16-bit variable NUM has overflowed and returned to 0 (ST62). If NUM ≠ 0, the processes of steps ST50 to ST61 are repeated.

  If such processing is repeated, NUM = 0 is eventually reached, and at that time, it is determined whether or not the value of the variable CNT indicating the number of winning is a normal value (ST63). The variable CNT means the number of times the counters CTa and CTb are included in the winning range as a result of 65536 × 2 inspection operations. Therefore, the winning rate CNT / 65536 calculated from the value of the variable CNT is essentially close to the winning rate setting value 1/312. Therefore, for example, with a margin of 50%, if the value of the variable CNT is included in the numerical range of (105 to 315) × 2, it is considered normal, and if it exceeds this numerical range, it is determined as abnormal. Then, the abnormality flag FG is set to 1 (ST64).

  As described above, the process of step ST75 in FIG. 7 is completed. If the value of the abnormality flag FG is 1, abnormality notification processing is executed without starting the gaming operation (ST77). Therefore, there is no possibility that the gaming operation is started even though the random number generation circuit is abnormal. Also, even if illegal modification related to the random number generation circuit is made, illegal games cannot be made successful.

  In this embodiment, since the abnormality check process (ST75) described above is provided, it is not necessary to execute the time consumption process as in step ST91 of FIG. Note that when the initial processing time of the rendering operation LSI mounted in the rendering control unit 22 is longer than the processing time of FIG. 8, the self-diagnosis operation is also performed for circuits other than the random number generation circuit. Is preferred.

  Then, it waits for the completion signal ACK from the payout control unit 24 (ST78). This is to prevent the main control unit 21 from starting a steady game operation until the initial processing of the payout control unit 24 is completed. If the completion signal ACK is received from the payout control unit 24, the RAM clear signal DEL is acquired from the input port IN1 (ST79).

  As described above, the RAM clear signal DEL is a signal for determining whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer 21A, and ON / OFF of the initialization switch SW operated by the staff. It has a value corresponding to the state. In this embodiment, since the signal latch circuit 45 is provided and the RAM clear signal DEL is latched in the flip-flop FF5, the RAM clear signal DEL is read no matter how long the processes from step ST75 to ST78 are prolonged. I will not drop it.

  Next, a clear signal is output from the output port OUT2 to the signal latch circuit 45, and the latched RAM clear signal DEL is returned to the H level (an erasing process (not shown)). However, this erasing process is not necessarily required and may be omitted. Here, when the erasing process is omitted, the RAM clear signal DEL latched in response to the operation of the initialization switch SW immediately after the power is turned on is maintained at the L level. It is where it is done.

  However, even when the watchdog timer circuit in the one-chip microcomputer functions and the system reset process of FIG. 7 is re-executed during the game operation, the level of the RAM clear signal DEL received by the input port IN1 is limited. First, the RAM clear process (ST84) is always executed through the determinations of the next steps ST81 and ST83, so that no adverse effects occur. Note that after the game operation is interrupted due to a power failure or the like, the power reset circuit of the flip-flop FF5 functions, and the RAM clear signal DEL received by the input port IN1 automatically becomes H level.

  In any case, next, the level of the RAM clear signal acquired in the process of step ST79 is determined (ST80). Here, assuming that the RAM clear signal is in the ON state (L level), following the determination in step ST80, the entire area of the built-in RAM is cleared to zero (ST84). Therefore, the value of the backup flag BFL set in the process of step ST37 in FIG. 9B becomes zero together with other checksum values.

  Next, a power-on command for notifying that the RAM area has been cleared to zero is output (ST85), and a CTC (Z80 counter timer circuit that outputs an interrupt signal INT for starting the timer interrupt operation (FIG. 9A) is output. ) Is initialized (ST86). Then, with the CPU set to the interrupt disabled state (ST87), update processing is executed for various counters (ST88), and then the CPU is returned to the interrupt enabled state and returns to step ST87. The counter updated in step ST88 includes a miss symbol counter. This miss symbol counter is out of the result of the big hit lottery process in the special symbol process (ST27) of FIG. 9A. It is a counter for deciding what kind of out-of-game to produce when it becomes a state.

  Now, returning to the determination processing in step ST80, the RAM clear signal is in the OFF state (H level) when recovering from the power failure state. In such a case, following the determination in step ST80, the contents of the backup flag BFL are determined (ST81). The backup flag BFL is data indicating that the operation of the power supply monitoring process of FIG. 9B has been executed. In this embodiment, the backup flag BFL is set to 5AH in the process of step ST37 when the power is turned off. It is cleared to zero in the process of step ST33 after the power is restored.

  When the power is turned on or when recovering from a power failure, the content of the backup flag BFL is 5AH. However, if the program goes into a runaway state for some reason and a CPU reset operation is caused by the watchdog timer, the backup flag BFL = 00H. Therefore, if BFL ≠ 5AH (normally BFL = 00H), the process proceeds from step ST81 to step ST84 to return the operation of the gaming machine to the initial state.

  On the other hand, if backup flag BFL = 5AH, checksum calculation for calculating the checksum value is executed (ST82). Here, the checksum operation is an 8-bit addition operation for the work area of the built-in RAM. Naturally, the work area whose contents are changed in the processes of steps ST75 to ST81 is not included in the checksum calculation target area. When the checksum value is calculated, the calculation result is compared with the stored value at the SUM address in the RAM (ST83).

  In the SUM address, the checksum value by the same checksum calculation is stored in the power supply monitoring process (FIG. 9B) executed when the voltage drops (ST38). The stored calculation results are maintained by a backup power source together with other data in the built-in RAM. Therefore, the two should be matched by the determination in step ST83.

  However, if the checksum calculation (ST38) cannot be executed when the power is turned off, or if it can be executed, the data in the work area will be damaged after the checksum calculation (ST82) of the main process is executed. In such a case, the determination result in step ST83 is inconsistent. If data corruption is detected due to a discrepancy between the determination results, the process proceeds to step ST84 to execute a RAM clear process to return the operation of the gaming machine to the initial state. On the other hand, if it is determined in step ST83 that the checksum value obtained by the checksum calculation (ST82) matches the stored value at the SUM address, the process proceeds to step ST86.

  Next, a timer interrupt processing program (FIG. 9A) that is started every 2 mS while interrupting the main processing described above will be described. When the timer interrupt occurs, the power supply monitoring process is immediately executed without saving the CPU register (ST20). This is because the timing at which the timer interrupt process is started is fixed immediately after step ST89.

  In the power supply monitoring process (ST20), the level of the voltage drop signal DWN supplied from the power supply board 20 is determined. The specific processing content will be described later. When the power monitoring process (ST20) ends, the value of the winning counter RG used in the lottery operation in the normal symbol process (ST26) is updated (ST21). Note that the jackpot determination random number value RND used in the lottery operation in the special symbol process (ST27) is generated by the random number generation circuit of FIG. 5 and is not updated in the process of step ST21.

  When the winning random number update process (ST21) ends, a timer subtraction process is performed for the timer that manages the time of each gaming operation (ST22). The timer to be subtracted here is mainly used for managing the opening time of the electric tulip and the special winning opening and other game effect times.

  Subsequently, ON / OFF signals of various switches including the winning detection switches of the symbol start openings 15A and 15B and the big winning opening 16 are inputted, and the ON / OFF signals are stored in the work area (ST23). The winning switch signals SWa and SWb supplied from the symbol start ports 15A and 15B through two paths are acquired via the input port IN1, and when the rising edges of the winning switch signals SWa and SWb are detected, the work is performed. An ON signal is stored in the area.

  When the switch input process (ST23) is completed, an error management process is performed (ST24). The error management process includes a determination as to whether an abnormality has occurred inside the device, such as whether or not the supply of game balls has stopped or the game balls are clogged. In this error management process (ST24), the level of the abnormality detection signal ABN is also determined. If an abnormality is recognized in the operation of the counting circuit 43, an error process including a notification process is started. In the present embodiment, since the random number RND for jackpot determination is generated by the counting circuit 43, when the operation of the counter CTa is stopped, an appropriate response can be taken immediately even during the game operation. The level of the abnormality detection signal ABN is determined every 2 mS (ST24).

  Next, after executing the management process based on the prize ball counting signal received from the payout control unit 24 (ST25), the normal symbol process is performed (ST26). The normal symbol processing means determination as to whether or not to operate an ordinary electric accessory such as an electric tulip. Specifically, when it is determined that the game ball has passed through the gate based on the switch input result in step ST33, the winning counter RG updated in the random number updating process (ST21) is compared with the winning winning value. Done. If the comparison result is a winning state, the operation mode is changed to the winning operation mode. In addition, if it is a hit, processing for the operation of a normal electric accessory such as an electric tulip is performed.

  Subsequently, special symbol processing is performed (ST27). The special symbol process is a determination as to whether or not to operate a special electric accessory such as the special winning opening 16. First, it is determined whether or not the game ball has passed the symbol start ports 15A and 15B by the switch input process of step ST23. If it is determined that the winning state is obtained, 16-bit length data relating to the winning switch signal (SWa or Swb) corresponding to the winning state is acquired from the counting circuit 43 in FIG. Specifically, the upper 8-bit data of the 16-bit latch (Ra or Rb) is acquired while switching the output switching signal CTL, and subsequently the lower 8-bit data of the 16-bit latch (Ra or Rb) is acquired.

  Then, based on the acquired 16-bit length data, the big hit lottery process is executed. Then, if the lottery result is a winning state, the operation mode is changed to the big hit operation mode. In addition, if it is a big hit, processing for the operation of special electric accessories such as a big prize opening is performed.

  After such special symbol processing (ST27), the lighting operation of the LEDs managed by the main control unit 21 is advanced (ST28), and the solenoid drive processing for realizing the opening / closing operation of the electric tulip, the big prize opening, etc. is executed. Later (ST29), the CPU is returned to the interrupt permission state EI and the timer interrupt is finished (ST30). As a result, the process returns from the interrupt process routine to the infinite loop process (FIG. 7) of the main process, and the process of step ST88 is executed.

  Next, the power supply monitoring process (ST20) shown in FIG. In the power supply monitoring process (ST20), first, a voltage drop signal supplied from the power supply board 20 is acquired through an input port (not shown) (ST31), and it is determined whether it is an abnormal level (ST32). If it is not an abnormal level, the abnormal number counter and the backup flag BFL are cleared to zero and the process is terminated (ST33).

  On the other hand, if the voltage drop signal is at an abnormal level, the abnormal number counter is incremented (+1) (ST34), and it is determined whether the counting result exceeds the upper limit value MAX (ST35). This is because the data acquired from the input port may be garbled due to the influence of noise or the like, and the abnormal level is continuously set for a predetermined number of times (for example, upper limit MAX = 2). In the case of maintaining, it is determined that the AC power source is actually shut off.

  As described above, in this embodiment, the subsequent backup processing is not started immediately even when the power is shut off, and the operation start timing is delayed by MAX × 2 mS. However, (1) The power supply drop signal is not a drop in the DC power supply voltage, but a drop in the AC DC voltage is detected. (2) The DC power supply voltage is maintained for a while after the AC power supply is shut off by a large-capacitance capacitor. (3) The power supply monitoring process is repeated at a high speed (every 2 ms), and (4) the backup process is extremely simple and finishes quickly, so there is virtually no adverse effect.

  By the way, as a result of the determination in step ST35, if the count value of the abnormal number counter coincides with the upper limit value MAX, the abnormal number counter is cleared to zero (ST36), and then 5AH is set to the backup flag BFL (ST37). Next, the same calculation as in step ST7 of the main routine is executed for the same work area (work area), and the calculation result is stored (ST38). The operation to be executed is typically an 8-bit addition operation.

  Thereafter, the one-chip microcomputer 21A is set in a RAM access prohibited state (ST39), and output data of all output ports is cleared (ST40). As a result, unreasonable data is prevented from being transmitted to the payout control unit 24 that starts the same type of power supply monitoring process later than the main control unit 21. When the above backup process is completed, the generation of the interrupt signal INT is prohibited by the setting process for the CTC, and the DC power supply voltage is lowered while repeating the infinite loop process (ST41). At this timing, the CPU is originally in an interrupt disabled state (see ST30). However, in this embodiment, an interrupt signal from the CTC is used to eliminate as much as possible the possibility of malfunction due to a drop in power supply voltage. INT output is also prohibited.

  Next, the operation content of the payout control unit 24 will be described with reference to FIG. The operation of the payout control unit 24 can be summarized as follows: main processing (FIG. 10) that starts after power-on and ends with infinite loop processing, and reception interrupt processing (not shown) that is activated by the strobe signal STB from the main control unit 1. And timer interrupt processing (not shown) that is started every certain time (2 mS). In the reception interrupt process, the control command CMD "is acquired from the input port IN4 (FIG. 4), stored in the command buffer area of the RAM, and then the CPU is set to the interrupt enabled state (EI). Finish.

  Next, the operation content of the main process (FIG. 10) of the payout control unit 24 will be described. However, this process has much in common with the main process of the main control unit 21 described with reference to FIG. That is, the processing of steps ST100 to ST101 of the payout control unit 24 corresponds to steps ST71 to ST72 of FIG. 7, and the processing of steps ST103 to ST105 corresponds to steps ST81 to ST83 of FIG. Steps ST107 and ST109 are the same processes as steps ST84 and ST86 in FIG. Note that the payout control unit 24 represents the backup flag BAK to distinguish it from the backup flag BFL. Then, the payout control unit 24 immediately resets the backup flag BAK to zero if the result of the sum calculation in step ST105 matches (ST106).

  Further, the process of step ST102 of the payout control unit 24 is substantially the same as the process of steps ST79 to ST80 of FIG. However, in the payout control unit 24 of the embodiment, unlike the main control unit 21, the abnormality check process (ST75) of the random number generation circuit is not provided, so that the RAM clear signal DEL is held in the signal latch circuit 45. There is no.

  Then, the initial process of the payout control unit 24 is completed by the process of step ST106 or the process of step ST107, and a completion signal ACK is returned to the main control unit 21 to indicate this (ST108). As a result, the main control unit 21 can exit the standby process in step 78 by receiving the completion signal ACK. Therefore, the game operation is not started until the preparation of the payout control unit 24 is completed. As described with respect to the signal latch circuit 45, the main control unit 21 does not read out the RAM clear signal no matter how long the standby process in step 78 is prolonged.

  If the transmission of the completion signal ACK is completed (ST108), next, a CTC (Z80 counter timer circuit) that outputs a timer interrupt signal is initialized (ST109), the CPU is set in an interrupt enabled state (ST110), Repeat infinite loop processing. During execution of this infinite loop process, a timer interrupt process is executed at regular time intervals (2 mS), and a payout operation based on a control command from the main control unit 21 is executed.

  As mentioned above, although embodiment of this invention was described concretely, the concrete description content does not limit this invention at all, and various modifications are possible.

  For example, in the algorithm of FIG. 8, the latch pulse is generated by software processing (ST51, 53, 56, 58), but the latch pulse may be generated by the circuit configuration of FIG. Here, an AND gate G7 that receives the count clock Φ and the permission signal ALW, a delay circuit DLT that delays the output of the AND gate G7, an OR gate G8 that receives the output of the delay circuit DLT and the Q output of the flip-flop FF2, An OR gate G9 for receiving the output of the delay circuit DLT and the Q output of the flip-flop FF3 is provided.

  The outputs of the OR gate G8 and the OR gate G9 are supplied to the first latch Ra and the second latch Rb as the latch clock RCK, respectively. The permission signal ALW is set to the H level only during the abnormality check process (ST78). According to such a circuit configuration, the abnormality check process (ST78) of the random number generation circuit can be realized with the minimum necessary program, and there is an advantage that the use area of the ROM is not wasted and the processing time can be shortened. Note that according to the circuit configuration of FIG. 11, the OR gate group 41 is not required, and the winning opening switch signals SWa and SWb are directly supplied to the D input terminals of the flip-flops FF2 and FF3.

It is a perspective view of the pachinko machine shown in an embodiment. It is the front view which illustrated in detail the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is the block diagram which extracted a part of FIG. It is a circuit block diagram which shows the random number generation circuit which is a part of main control board. 6 is a circuit block diagram (a) illustrating a part of FIG. 5 in detail, and a time chart (b) for explaining the operation content. It is a flowchart explaining the system reset process of a main control part. It is a flowchart explaining the abnormality check process of a random number generation circuit. It is a flowchart explaining the timer interruption process of a main control part. It is a flowchart explaining the system reset process of a payout control part. It is a circuit block diagram which shows another circuit structure of a random number generation circuit. It is a flowchart explaining a prior art.

Explanation of symbols

21 Main Control Units 22-24 Sub Control Unit SW Initialization Switch 45 Memory Holding Circuit

Claims (7)

A main control unit that executes a lottery process for determining whether or not to generate a gaming state advantageous to a player and centrally controls game operations based on the lottery result, and a control command from the main control unit And a sub-control unit that executes individual control operations,
A gaming machine provided with a backup function at least in the main control unit for maintaining the stored contents even after the power supply voltage is cut off,
In addition to being configured to erase the stored contents of the memory in response to the ON operation of the initialization switch, a memory holding circuit for storing the ON operation of the initialization switch is provided,
The memory holding circuit
A signal input terminal that receives a fixed level input signal, a clock terminal that receives a clock signal that defines the storage timing of the input signal, an output terminal that outputs the stored input signal, and a clear that resets the output of the output terminal to the initial state A latch circuit having a clear terminal for receiving a signal;
A power reset circuit that supplies a clear signal to the clear terminal for a predetermined time after power-on and resets the output terminal of the latch circuit to an initial state, and
After the power is turned on, the latch circuit clear terminal receives a clear signal from the power reset circuit, so that the latch circuit output terminal is automatically reset to the initial state,
When the initialization switch operation signal is supplied to the clock terminal of the latch circuit, the fixed level input signal supplied to the signal input terminal is input to the latch circuit at the timing when the initialization switch that has been turned ON returns to the OFF state. A gaming machine configured to be stored and thereafter the output terminal of the latch circuit is maintained at a fixed level . The clear input terminal of the latch circuit is connected to a signal output terminal that allows the main control unit to output a clear signal by program processing.
The gaming machine according to claim 1, wherein the main control unit grasping the ON operation of the initialization switch is configured to be able to erase the stored contents of the latch circuit. The main control unit determines whether or not the sub-control unit has received a completion signal indicating completion of the initial processing prior to confirming the ON operation of the initialization switch. The gaming machine described.   The gaming machine according to any one of claims 1 to 3, wherein the main control unit self-diagnose a circuit abnormality of the main control unit prior to confirming the ON operation of the initialization switch.   The gaming machine according to claim 4, wherein the circuit to be subjected to self-diagnosis is a random number generation circuit that generates a random value used for the lottery process.   6. The gaming machine according to claim 5, wherein the main control unit operates by having a signal output process of repeatedly outputting a latch signal a plurality of N times to the random number generation circuit. The random number generator circuit
An oscillation unit for generating a counting clock;
A counting circuit whose counter value is updated by a counting clock;
A temporary holding circuit for temporarily holding the counter value of the counting circuit based on the stored signal;
On the condition that the main control unit is outputting a permission signal, a transient operation unit that generates a memory signal based on the output of the oscillation unit and supplies the memory signal to the temporary holding circuit;
The gaming machine according to claim 5, comprising: