JP7033863B2 - Pachinko machine - Google Patents

Description

The present invention relates to a gaming machine that generates a big hit state by a lottery process caused by a gaming operation, and more particularly to a gaming machine provided with a unique gaming frame.

A ball game machine such as a pachinko machine is equipped with a symbol start opening provided on the game board, a symbol display unit that displays a series of symbol variation modes by a plurality of display symbols, and a large winning opening for opening and closing the opening / closing plate. It is composed of. Then, when the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is set, and after the game ball is paid out as the prize ball, the displayed symbol is changed for a predetermined time on the symbol display unit. After that, when the symbol is stopped in a predetermined mode such as 7, 7, 7, a big hit state is reached, and the big winning opening is repeatedly opened to generate a game state advantageous to the player.

Whether or not to generate such a game state is determined by a big hit lottery executed on the condition that the game ball wins at the symbol start opening, and the above symbol variation operation is based on this lottery result. It has become a thing. For example, when the lottery result is in the winning state, an effect operation called a reach action or the like is executed for about 20 seconds, and then special symbols are arranged. On the other hand, the same reach action may be executed even in the case of a lost state, and in this case, the player pays close attention to the transition of the production operation while strongly paying attention to the big hit state. Then, if the predetermined symbols are aligned on the stop line at the end of the symbol variation operation, the player is guaranteed to be in the big hit state.

Japanese Unexamined Patent Publication No. 2016-209305 Japanese Unexamined Patent Publication No. 2016-073369 Japanese Unexamined Patent Publication No. 2016-0733368 Japanese Unexamined Patent Publication No. 2016-063865 Japanese Unexamined Patent Publication No. 2016-005698

This type of gaming machine is generally divided into a frame-side member that is used for a long period of time and a board-side member that is changed for each model, and by attaching the board-side member to the frame-side member installed in the game hall. It will be in a completed state. When changing the model, the old board-side member is removed from the frame-side member and a new board-side member is attached, but the frame-side member up to that point is used as it is (Patent Documents 1 to Patent). Document 5).

Therefore, there is a problem that the design of the frame side member cannot be individualized. In other words, if the frame side member has a unique design, it matches exactly with the production concept that the model is trying to realize for a specific model, but there is a problem that unnaturalness cannot be denied for another model. be.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a gaming machine that operates appropriately even if the design of the frame side member is changed in accordance with the production concept for each model. And.

In order to achieve the above object, the present invention is a gaming machine that executes all or part of an image effect, a lamp effect, or a sound effect in response to a lottery result of a predetermined lottery process. The machine is configured to include a game board that holds a computer circuit that controls an effect operation, and a frame-side member having a plurality of members, and the frame-side member is a first member that constitutes an outer frame. A second member mounted on the first member, a third member mounted on the second member, and a changeable member mutatably mounted on the third member. The game board corresponding to the change member is detachably attached to the second member, and the change member has a determination code corresponding to the game board and a drive device that contributes to the effect operation. The computer circuit is configured to have a first serial port that outputs a clock signal and receives the serial signal of the discrimination code in synchronization with the output clock signal, and the drive device in synchronization with the clock signal. A second serial port for outputting drive data is provided, and when the power is turned on, the computer circuit acquires the discrimination code from the change member via the first serial port, and the change member obtains the determination code. , It is configured to perform a matching determination as to whether or not the member corresponds to the game board, and to execute an abnormality notification if the members do not match.

In the present invention, when the power is turned on, the computer circuit acquires the discrimination code from the change member, determines the consistency between the game board and the change member, and if they do not match, the abnormality notification is executed. Appropriate operation is avoided .

It is preferable that the consistency determination by the determination code is limited to the time when the power is turned on, and after passing the consistency determination, it is preferable to acquire the design code on a regular basis and reflect it in the effect operation.

According to the present invention, it is possible to realize a gaming machine that operates appropriately even if the design of the frame side member is changed according to the production concept for each model.

It is an exploded perspective view which shows roughly the equipment composition of the gaming machine of an Example. It is a front view about the whole game machine and a game board. It is a drawing explaining the assembled state and separated state of a frame unit and a design unit. It is a six-sided view which shows the assembled state of a frame unit and a design unit. It is a six-sided view which shows the frame unit. It is a six-sided view showing a design unit. It is a drawing explaining the design determination part. It is a drawing explaining the ejection mechanism. It is a block diagram explaining the circuit structure of a gaming machine. It is a drawing explaining the serial transmission path between an effect control board and a frame side member, and the circuit structure of serial transmission / reception. It is a drawing explaining the PS conversion circuit.

Hereinafter, the present invention will be described in detail based on examples. As shown in FIG. 1, the gaming machine GM of the embodiment is roughly classified into a general-purpose section GER used in a gaming hall without change for a long period of time and a changing section CHG that can be changed for each model change.

In the case of the illustrated embodiment, the general-purpose unit GER has a rectangular frame-shaped wooden outer frame 1 that is detachably attached to the island structure of the game hall and an inner that is pivotally attached to the wooden outer frame 1 so as to be openable and closable. It is composed of a frame 2 and a front frame main body 3 that is pivotally attached to the inner frame 2 so as to be openable and closable.

On the other hand, the changing portion CHG includes a game board 4 (see FIG. 2B) that is detachably mounted from the front side of the inner frame 2, a frame unit 5 that is detachably mounted on the front frame main body 3, and a frame unit. It is composed of a design unit 6 that is detachably attached to 5.

Then, in the completed state, it is in the state of the front view shown in FIG. 2 (a). When this gaming machine GM is described with reference to the circuit configuration diagram shown in FIG. 9, the frame-side member GM1 is composed of a general-purpose unit GER, a frame unit 5, and a design unit 6, and the board-side member GM2. However, it is composed of the game board 4 (FIG. 2 (b)).

Before explaining the modified CHG characteristic of the present embodiment, first, the overall configuration of the gaming machine GM will be schematically described with reference to FIG. 2. In the gaming machine GM of the embodiment, an illuminated lamp such as an LED lamp is arranged on the left side of the front frame main body 3 and on the design unit 6. Further, as shown in FIG. 1, a total of three speaker SPs are arranged at the left and right positions of the upper part of the front frame main body 3 and the lower right side of the inner frame 2.

As shown in FIG. 2A, a firing handle HD for launching a game ball is provided on the lower right side of the lowermost portion of the front frame main body 3. In addition, the front frame main body 3 is provided with a storage plate for storing game balls and an operation panel for ball lending operation for a card-type ball lending machine, so that appropriate ball lending operation and storage operation are possible.

As shown in FIG. 2B, a main display device DS1 composed of a large liquid crystal color display is arranged substantially in the center of the game board 4, and a small liquid crystal color display is arranged below the main display device DS1. The sub-display device DS2 is arranged.

The sub-display device DS2 is held by four movable objects (concealed state in the figure), and is configured to be able to move up and down the front surface of the main display device DS1. Further, the sub-display device DS2 is configured to be rotatable in a raised position while being held by a movable accessory. In any operating state, the sub-display device DS2 is performing an appropriate image effect.

The main display device DS1 is a device that displays a specific symbol related to a jackpot state in a variable manner and displays a background image, various characters, and the like in an animation manner. Then, in the main display device DS1, along with the variable display operation of the specific symbol, a reach effect that expects a big hit state to be invited, a notice effect, and the like may be executed. The notice effect includes the appearance of a movable accessory holding the sub-display device DS2, the rotation operation of the sub-display device DS2, and the like.

In this embodiment, an arc passage through which the game ball falls and moves is formed on the left side and the right side of the main display device DS1, a symbol start port STR is arranged at the bottom of the left side passage, and a large size is provided at the bottom of the right side passage. A winning opening ATC is arranged.

A detection switch is arranged inside each winning opening, and when the detection switch detects the passage of a game ball, a predetermined number of prize balls are paid out. However, in the normal game state, the entrance of the large winning opening ATC is closed, and even if the game ball is dropped into the arc passage on the right side of the main display device DS1, the prize ball cannot be obtained.

Therefore, in the normal game state, the player fires the game ball so that the game ball falls into the arc passage on the left side of the main display device DS1 (left-handed). Then, when the dropped game ball passes through the symbol start opening STR (winning state), the big hit lottery process is executed as long as the hold upper limit value is not exceeded, and it is decided by lottery whether or not to shift to the game state advantageous to the player. Will be done.

However, regardless of the result of the big hit lottery, the main display device DS1 starts a series of image effects accompanied by the fluctuation operation of the special symbol, triggered by the winning of the game ball. Further, in response to this image effect, a sound effect accompanied by background music and a production sound, and a lamp effect in which the lamp blinks are executed.

In parallel with this series of effect operations, the main display device DS1 and the sub display device DS2 may execute the reach effect and the advance notice effect. After that, when the variable operation of the special symbol is completed, the result of the big hit lottery process is notified to the player.

Then, when the game state shifts to the big hit state, the entrance of the big winning opening ATC is opened, so that the player fires the game ball so that the game ball falls into the arc passage on the right side of the main display device DS1. It will be (right-handed).

The operation of the big winning opening ATC is not particularly limited, but in a typical big hit state, the entrance is controlled to close when a predetermined time elapses or a predetermined number (for example, 10) of game balls win a prize. Such an operation is continued up to, for example, 15 times, and is controlled in a state advantageous to the player. If the stop symbol after the change of the special symbol is a specific symbol among the special symbols, the privilege that the game after the end of the special game is in a high probability state (probability change state) is given.

Since the schematic operation of the gaming machine GM has been described above, the modified portion CHG will be described by returning to FIG. As shown in FIG. 1, the frame unit 5 of the embodiment is composed of a horizontal piece 50 and a vertical piece 51 in an inverted L shape, and is detachably fixed along the upper side and the right side of the front frame main body 3. There is. Further, the design unit 6 of the embodiment is vertically long and is detachably fixed along the vertical piece 51 of the frame unit 5.

Here, the frame unit 5 is roughly divided into a general-purpose unit 5G having a general general-purpose design and a wide variety of individuality units 5U having a unique design. As the individuality unit 5U, for example, a series with a boxing movie as a motif. Gong frame 5U1 used in the game machine of, glasses girl frame 5U2 used in a series of game machines with the motif of the anime hero (glasses girl), ..., XX frame 5Ui, XX frame 5Uj, etc. Is prepared.

Further, a plurality of design units 6 are prepared for each type of frame unit 5. For example, as the design unit 6 corresponding to the spectacle girl frame 5U2 (see FIG. 2A), the main character's clothing is used. There are multiple types with different colors and designs.

As described above, in this embodiment, a plurality of frame units 5 to be mounted on the front frame main body 3 are prepared, and a plurality of design units 6 are prepared for each frame unit 5, so that the game board 4 is provided. The periphery of the game board 4 can be optimally decorated according to the intended game characteristics.

FIG. 3 shows the combined state of the frame unit 5 and the design unit 6 (FIG. 3 (a)), the single frame unit 5 (FIG. 3 (b)), and the single design unit 6 (FIG. 3 (c)). , Each front view is illustrated. The six views of the combined state of the frame unit 5 and the design unit 6 are shown in FIG.

Further, FIG. 5 is a six-view view of the frame unit 5, and FIG. 6 is a six-view view of the design unit 6. By comparing the six views of FIG. 4 with the six views of FIGS. 5 and 6, the shapes of the frame unit 5 and the design unit 6 become clear.

Although not particularly limited, the illustrated frame unit 5 is a spectacle girl frame 5U2, and the design unit 6 is formed with a straw doll 9 corresponding to the spectacle girl frame 5U2. As shown in FIG. 2, an image of a girl with glasses is drawn on the actual design unit 6 according to the playability of the game board 4, but in FIGS. 3 to 6, these images are displayed for convenience. Is omitted.

In any case, the game bar 10 is operably attached to the frame unit 5 through the straw doll 9 (see FIG. 3B). Then, in the advance notice effect suggesting that the lottery process result is in the big hit state, if the reliability of the advance notice effect is high, the pressing operation of the game bar 10 is permitted. The reliability means that the lottery processing result may be in a big hit state.

Further, the frame unit 5 is provided with an opening hole 11 for receiving the locking piece 15 (FIG. 6) protruding from the design unit 6 (see FIG. 3 (b)). A swing member 12 that can swing downward in FIGS. 3 and 5 is arranged in the opening hole 11.

As shown in FIG. 6, the locking piece 15 is a plate material having an L-shaped cross section. Then, when the design unit 6 is assembled to the frame unit 5, the frame unit 5 is operated so as to polymerize the design unit 6 in a state where the upper appropriate position of the design unit 6 is engaged with the frame unit 5. Then, the tip of the locking piece 15 rushes into the opening hole 11 and comes into contact with the rocking member 12.

As described above, since the swing member 12 is configured to swing vertically downward, when the tip of the locking piece 15 further enters, the swing member 12 swings downward and the opening hole. The locking piece 15 is immersed in the eleven. Next, in the immersed state of the locking piece 15, the rocking member 12 is swung upward by using an appropriate locking member (not shown) or by applying an elastic force to the rocking member 12. Then, the hook tip of the locking piece 15 is locked to the swing member 12.

At this time, since the same hook state is realized at other places, the design unit 6 is accurately positioned with respect to the frame unit 5. Then, in this polymerization state, the design unit 6 and the frame unit 5 are completely fixed by screwing them in place.

Returning to FIG. 3, and continuing the description of the configuration of the frame unit 5, the model discrimination board BD0 is arranged inside the horizontal piece 50 of the frame unit 5. An 8-bit length discrimination code is fixedly stored in the model discrimination board BD0, and the frame unit 5 is a general-purpose unit 5G, or any individual frame 5U (5U1, 5U2, ... 5Uj) is uniquely specified (see FIG. 3D).

As described above, the frame unit 5 corresponds to the game board 4, and the matching relationship between the frame unit 5 and the game board 4 can be confirmed by determining the determination code when the power is turned on. Then, in the unlikely event that the frame unit 5 does not match the game board 4, the abnormality notification operation is executed.

Further, as shown in FIG. 3 (b), photo interrupters PI0 to PI2 (= PIi) for receiving the light-shielding plate MK protruding from the design unit 6 are arranged on the vertical piece 51 of the frame unit 5 and are close to the photo interrupters PI0 to PI2 (= PIi). , The design discrimination substrate BD1 is arranged. The light-shielding plate MK and the photo interrupter PIi constitute the design determination unit 13.

FIG. 7C illustrates the circuit configuration of the design discrimination substrate BD1, and FIG. 7A illustrates the design determination unit 13 composed of the light-shielding plate MK and the photointerruptor PIi. ..

In this embodiment, the design determination unit 13 includes three photo interrupters PI0 to PI2. As shown in the figure, each photointerruptor PIi is configured such that a photodiode D that emits inspection light and a phototransistor TR that receives inspection light face each other with an appropriate gap GP interposed therebetween.

The light-shielding plate MK is a transparent portion formed in a substantially T-shape in cross-sectional view by a base MK1 fixed to the design unit 6 and a protruding portion MK2 that plunges into the gap GP between the photodiode D and the phototransistor TR at the time of assembly. It is a plastic material. Then, the mask sheet SH is attached to the transparent protruding portion MK2 to realize the light-shielding performance.

As shown in the figure, the protruding portion MK2 is divided into three parts corresponding to the photo interrupters PI0 to PI2, and the appropriate place thereof is a light-shielding portion by the mask sheet SH. Therefore, the output Di of each photo interrupter PIi is 0 (= L) in the light-shielded state of the inspection light and 1 (= H) in the light-transmitting state.

Although not particularly limited, in this embodiment, one or two of the three portions of the three-divided protruding portions MK2 are light-shielding portions, and the outputs D2 to D0 of the photo interrupters PI2 to PI0 are shown in FIG. 7 ( As shown in b), up to five types of design units 6 (designs A to F) can be specified.

In the configuration of FIG. 7A, since only the photo interrupter PI2 is in a light-shielding state, only the output D2 becomes 0, and the design unit 6 is drawn with the image of the design C.

Next, as shown in FIG. 5 (c), the outside air introduction port H0 and the ejection port H1 are formed in the frame unit 5, and the ejection mechanism 16 communicating with the ejection port H1 is formed at a position below the outside air introduction port H0 (FIG. 8). See) is arranged in a tilted position. The ejection mechanism 16 is arranged inside the frame unit 5, and in FIG. 6C, only the ejection port H1 and the connecting hole IN appear with respect to the ejection mechanism 16.

A scent bag 17 is arranged in the design unit 6 corresponding to the ejection mechanism 16 (see FIG. 6 (c)). The scent bag 17 contains an appropriate fragrance corresponding to the game concept of the gaming machine, and the scent of the scent bag 17 is emitted from the ejection port H1 of the ejection mechanism 16 only at the time of a predetermined advance notice production. It is designed to be released toward.

In this embodiment, the ejection mechanism 16 is arranged in the frame unit 5, while the odor bag 17 is arranged in the design unit 6. Therefore, it is possible to change the fragrance of the scent bag 17 according to the color and design of the clothes of the main character for each design unit 6, and it becomes possible to further demonstrate the individuality of each gaming machine.

FIG. 8A is an exploded perspective view showing the configuration of the ejection mechanism 16. As shown in the figure, the ejection mechanism 16 includes a foundation member BS0 that receives the outside air introduced from the outside air introduction port H0 in the connecting hole IN, a solenoid member SL built in the first member BS1 that is continuously connected to the foundation member BS0, and the solenoid member SL. It is configured to have a blower member BLW built in a second member BS2 connected to the first member. As described above, the odor bag 17 is arranged in the design unit 6 in the vicinity of the connecting hole IN of the foundation member BS0.

FIG. 8B is a principle diagram illustrating the operating principle of the ejection mechanism 16. Actually, the ejection mechanism 16 is attached in the inclined state shown in FIG. 8 (c). As shown by the arrow (→), the outside air introduced into the connecting hole IN via the scent bag 17 is introduced into the first member BS1 containing the solenoid member SL via the bent outside air passage. The outside air is introduced toward the back of the paper in FIG. 8B with respect to the connecting hole IN.

As shown in FIG. 8A, the solenoid member SL is composed of an electromagnetic solenoid SL1, a blocking portion SL2, and a plunger SL3 for advancing and retreating the blocking portion SL2, and the plunger SL3 is provided with a spring SP.

Therefore, when the electromagnetic solenoid SL1 is in a non-energized state, the plunger SL3 and the blocking portion SL2 project to the left in the drawing due to the elastic force of the spring SP to block the outside air passage. On the other hand, when the electromagnetic solenoid SL1 is energized, the plunger SL3 is pulled in to the right in the drawing, so that the outside air passage is opened.

Although not particularly limited, in the present embodiment, the electromagnetic solenoid SL1 is configured to be energized at the time of a highly reliable advance notice effect, and the blower member BLW is operated in response to this conduction operation.

8 (b) and 8 (c) show the conduction state of the electromagnetic solenoid SL1, and show the state in which the outside air introduced into the first member BS1 is introduced into the second member BS2. The outside air contains an appropriate scent by passing through the odor bag 17.

The second member BS2 has a built-in blower member BLW, and the blower motor (blower) starts to rotate in response to the energization operation of the electromagnetic solenoid SL1. Therefore, the outside air containing the scent introduced into the second member BS2 is ejected from the ejection port H1. The outside air is blown out toward the ejection port H1 toward the front of the paper surface of FIG. 8B like a long sigh. It should be noted that the number of times of ejection may be completed only once or repeated a plurality of times depending on the reliability of the advance notice effect.

As shown in FIG. 5 (c), this spout H1 is open to the player, and the player feels a blast or a scent at the time of a predetermined advance notice effect, so that a big hit state is invited at a predetermined high level. You will expect it with reliability.

As described above, in this embodiment, in addition to the advance notice effect by the video, the sound, the lamp, and the accessory, the effect operation by the blast and the scent is possible, and the extremely novel advance notice effect is realized. Moreover, it is possible to emit different unique scents according to the playability. Normally, since the blower member BLW is stopped and the electromagnetic solenoid SL1 is in a non-energized state, the player does not feel the blower or the scent.

Now that the equipment configuration of the gaming machine has been described, the circuit configuration will be described next. FIG. 9 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes each of the above operations. Further, FIG. 10 shows a part of FIG. 9 in detail, and shows the connection state between the effect control board 22 and the motor drive board 37 and the like.

As shown in FIG. 9, this pachinko machine GM has a power supply board 20 that receives AC voltage and outputs various DC voltages, power supply abnormality signals ABN1 and ABN2, system reset signal (power supply reset signal) SYS, and game control. The main control board 21 that is centrally responsible for the operation, the effect control board 22 that executes the lamp effect and the sound effect based on the control command CMD received from the main control board 21, and the control command CMD received from the effect control board 22. The image control board 23 that drives the display device DS based on', the payout control board 24 that controls the payout motor M based on the control command CMD received from the main control board 21, and pays out the game ball, and the player. It is mainly composed of a launch control board 25 that launches a game ball in response to the operation of.

The control command CMD output by the main control board 21 is transmitted to the effect control board 22 via the effect interface board 27, and the control command CMD'output by the effect control board 22 is the effect interface board 27 and the image. It is transmitted to the image control board 23 via the interface board 28. Further, the control command CMD "output by the main control board 21 is transmitted to the payout control board 24 via the main board relay board 32.

The control commands CMD, CMD', CMD "are all 16-bit length, but the control commands related to the main control board 21 and the payout control board 24 are transmitted in parallel twice every 8 bit length. On the other hand, the control command CMD'transmitted from the effect control board 22 to the image control board 23 is collectively transmitted in parallel with a 16-bit length.

A computer circuit including a one-chip microcomputer is mounted on each of the main control board 21, the effect control board 22, the image control board 23, and the payout control board 24. As shown in FIG. 10, for example, the one-chip microcomputer 40 is mounted on the effect control board 22. Therefore, the circuits mounted on the control boards 21 to 24 and the interface boards 27 to 28, and the operations realized by the circuits are functionally generically referred to, in this specification, the main control unit 21 and the effect control. It may be referred to as a unit 22, an image control unit 23, and a payout control unit 24.

Further, the pachinko machine GM is roughly classified into a frame-side member GM1 surrounded by a broken line in FIG. 9 and a board-side member GM2 integrated with the game board 4. As described above, the frame-side member GM1 of this embodiment is composed of a permanently used general-purpose unit GER, a frame unit 5 and a design unit 6 that can be changed for each model, and is a general-purpose unit. The GER is composed of an outer frame 1, an inner frame 2, and a front frame 3.

The general-purpose unit GER is fixedly installed in the game hall for a long period of time regardless of the model change. However, the frame unit 5 and the design unit 6 are replaced together with the new game board 4 by a staff member of the game hall or the like when the model is changed.

As shown in the broken line frame in FIG. 9, the frame side member GM 1 includes a power supply board 20, a payout control board 24, a launch control board 25, a frame relay board 35, a lamp drive board 36, and a motor drive board 37. , Are included, and these circuit boards are fixed in appropriate places on the inner frame 2 and the front frame 3, respectively.

Further, the frame-side member GM1 includes a model discrimination board BD0, a design discrimination board BD1, and a sensor & switch board BD2. Although not particularly limited, the model discrimination board BD0 and the design discrimination board BD1 are arranged in the frame unit 5, and the sensor & switch board BD2 is arranged in the front frame 3.

The lamp drive board 36 is configured by connecting a plurality of lamp drivers having the same configuration in series to receive a serial signal output from the one-chip microcomputer 40 of the effect control unit 22, and is arranged in the front frame main body 3 and the design unit 6. It is driving an illuminated lamp.

Further, the motor drive board 37 is connected in series by a plurality of motor drivers DV having the same configuration that receive the serial signal SDATA0 output from the one-chip microcomputer 40 (serial port S0) of the effect control unit 22 in synchronization with the clock signal CK1. It is configured to drive the first group of effect motor MOi and effect solenoid (see FIG. 10).

In the case of this embodiment, the effect motor MOi of the first group includes a rotary motor for rotating the sub display device DS2, a bonus motor for moving a movable accessory together with the sub display device DS2, a blower motor for a blower member BLW, and the like. It is included. Further, the effect solenoid includes an electromagnetic solenoid SL1 that moves the solenoid member SL.

As shown in FIG. 10, the sensor & switch board BD2 has a PS conversion circuit CV2 that receives a sensor signal SN from an origin sensor arranged at the origin position of the effect motor MOi together with other switch signals and sensor signals, and PS conversion. A buffer circuit BF that outputs a sensor signal serially converted by the circuit CV2 to the serial port S1 of the one-chip microcomputer 40 is arranged.

Further, the PS conversion circuit CV1 is arranged on the design discrimination board BD1, and the PS conversion circuit CV0 is arranged on the model discrimination board BD0. Here, the three PS conversion circuits CV2 to CV0 have the same circuit configuration as shown in FIG. 11A, and receive the clock signal CK1 and the acquisition signal LOAD in common, and receive the serial signal SDAT1 as the clock signal CK1. It is transferred in synchronization with.

The PS conversion circuit CV0 receives the discrimination code shown in FIG. 3D, and the PS conversion circuit CV1 receives the design code shown in FIG. 7B together with other switch signals. The switch signal received by the PS conversion circuit CV1 also includes a switch signal for detecting the operation of the game bar 10. As described above, the game bar 10, the model discrimination board BD0, and the design discrimination board BD1 are respectively arranged in the frame unit 5.

On the other hand, on the back surface of the game board 4, a main control board 21, an effect control board 22, and an image control board 23 are fixed together with a display device DS and other circuit boards. The frame-side member GM1 and the board-side member GM2 are electrically connected by connection connectors C1 to C4 centrally arranged at one location.

The power supply board 20 is connected to the main board relay board 32 through the connection connector C2, and is connected to the power supply relay board 33 through the connection connector C3. The power supply board 20 is provided with a power supply monitoring unit MNT that monitors the on / off of the AC power supply. When the power supply monitoring unit MNT detects that the AC power is turned on, the system reset signal SYS is maintained at the L level for a predetermined time, and then transitions to the H level. Further, when the power supply monitoring unit MNT detects that the AC power supply is cut off, the power supply abnormality signals ABN1 and ABN2 are immediately transitioned to the L level.

The system reset signal of this embodiment is generated by a DC power source based on an AC power source. Therefore, after the AC power supply is detected (usually the power switch is turned on) and increased to the H level, the H level is maintained unless the DC power supply voltage drops to an abnormal level. Therefore, even if the AC power supply is in a momentary power failure state while the DC power supply voltage is maintained, the system reset signal SYS does not reset the CPU.

The main board relay board 32 outputs the power supply abnormality signal ABN1, the backup power supply BAK, and other DC power supplies output from the power supply board 20 to the main control unit 21 as they are. On the other hand, the power supply relay board 33 outputs the system reset signal SYS received from the power supply board 20 and the AC and DC power supply voltages as they are to the effect control unit 22 and the image control unit 23.

On the other hand, the payout control board 24 is directly connected to the power supply board 20, and receives the same power supply abnormality signal ABN2 and backup power supply BAK as those received by the main control unit 21 directly together with other power supply voltages.

The system reset signal SYS output by the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V is turned on to the power supply board 20, and the one-chip microcomputer of the effect control unit 22 and the image control unit 23 is generated by this power supply reset signal. Is designed to be reset together with other IC elements.

However, this system reset signal SYS is not supplied to the main control unit 21 and the payout control unit 24, and a power supply reset signal (CPU reset signal) is generated in the reset circuit RST of each of the circuit boards 21 and 24. ing.

The reset circuit RST provided in the main control unit 21 and the payout control unit 24 each has a built-in watchdog timer, and each CPU unless a periodic clear pulse is received from the CPUs of the control units 21 and 24. Is forcibly reset.

Further, in this embodiment, the RAM clear signal CLR is generated by the main control unit 21 and transmitted to the one-chip microcomputers of the main control unit 21 and the payout control unit 24. Here, the RAM clear signal CLR is a signal for determining whether or not to initialize the entire area of the built-in RAM of the one-chip microcomputers of the control units 21 and 24, and the initialization switch SW operated by the staff is turned on. It has a value corresponding to the / OFF state.

By receiving the power supply abnormality signals ABN1 and ABN2 from the power supply board 20, the main control unit 21 and the payout control unit 24 start necessary termination processing prior to a power failure or business termination. Further, the backup power supply BAK is a DC 5V DC power supply that retains the data of the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is cut off due to the closing of business or a power failure. Therefore, the main control unit 21 and the payout control unit 24 can restart the game operation before the power is cut off after the power is turned on (power backup function).

As shown in FIG. 9, the main control unit 21 transmits a control command CMD ”to the payout control unit 24 via the main board relay board 32, while the payout control unit 24 shows a game ball payout operation. The prize ball counting signal, the status signal CON related to the abnormality of the payout operation, and the operation start signal BGN are received. The status signal CON includes, for example, a supply shortage signal, a payout shortage error signal, and a lower plate full signal. The operation start signal BGN is a signal for notifying the main control unit 21 that the initial operation of the payout control unit 24 is completed after the power is turned on.

Further, as shown in FIG. 9, the effect control unit 22 refers to the motor driver mounted on the motor drive board 30 and the lamp driver mounted on the lamp drive board 29 via the effect interface board 27. The necessary drive data is supplied as a serial signal. Further, the effect control unit 22 grasps the rotation state of each effect motor Mx based on the serial signal received from the motor drive board 30.

Similarly, the effect control unit 22 is between the motor drive board 37, the lamp drive board 36, and the sensor & switch board BD2 via the effect interface board 27, the frame relay board 34, and the frame relay board 35. Is executing the transmission / reception processing of the serial signal.

The sensor & switch board BD2, the design discrimination board BD1, and the model discrimination board BD0 are connected by a serial transmission line, and the effect control unit 22 is a serial signal for the PS conversion circuits CV0 to CV2 mounted on each circuit board. Is being executed (FIG. 10).

As shown in FIG. 9, the effect control unit 22 outputs the control command CMD'and the strobe signal STB', the system reset signal SYS received from the power supply board 20, and the DC voltage to the image control unit 23. There is. Then, the image control unit 23 drives the main display device DS1 and the sub display device DS2 based on the control command CMD'to execute various image effects.

Since the circuit configuration of the gaming machine of the embodiment has been schematically described above, the motor drive board 37, the sensor & switch board BD2, the design discrimination board BD1, and the model discrimination are subsequently described based on FIGS. 10 and 11. The connection relationship between the board BD0 and the effect control unit 22 will be described. As described above, the one-chip microcomputer 40 is mainly in charge of the operation of the effect control unit 22.

As shown in FIG. 10A, the one-chip microcomputer 40 includes a CPU core (hereinafter referred to as a CPU), a counter circuit CT, a parallel output port Po, and serial ports S0 to S1. ing. Then, the parallel output port Po outputs the reset signal RESET, the latch signal LATCH, and the acquisition signal LOAD at appropriate timings based on the control of the CPU.

Further, in the case of this embodiment, the serial port S0 functions as a serial output port and outputs serial data (drive data) SDATA0 in synchronization with the clock signal CK0. On the other hand, the serial port S1 functions as a serial input port and acquires serial data SDAT1 in synchronization with the clock signal CK1.

Next, the motor drive board 37 is configured by connecting a plurality of motor drivers DV having the same configuration in series. The motor driver DV is configured by incorporating four shift registers, for example, and receives a 4-bit drive output terminal corresponding to the number of built-in registers and a reset signal RESET that clears all the drive data of the drive output terminal. The terminal, the LATCH terminal that receives the latch signal LATCH that outputs the holding data of the built-in register to the drive output terminal, the input terminal IN that supplies the drive data SDATA0 to the most upstream internal register, and the drive data SDATA0 from the most downstream internal register. It is configured to have an output terminal OUT from which is output and a clock terminal SCLK that receives the clock signal CK0 that shifts the holding data of the built-in register.

Then, the drive data SDATA0 serially output by the serial port S0 is supplied to the input terminal IN of the most upstream motor driver DV, and the output terminal OUT of the most upstream motor driver DV is the input terminal of the motor driver DV on the downstream side thereof. It is supplied to IN. Hereinafter, the same applies, and the output terminal OUT of the series of motor driver DV is connected to the input terminal IN of the motor driver DV on the downstream side thereof.

Next, FIG. 11A illustrates a specific circuit configuration of the PS conversion circuit CV. In the case of this embodiment, the PS conversion circuit CV shown in FIG. 11A is arranged on the model discrimination board BD0, the design discrimination board BD1, and the sensor & switch board BD2, respectively, and the PS conversion circuits have the same configuration. CV0 to CV2 are connected in series as shown in FIG. 11 (c).

As shown in FIG. 11A, the PS conversion circuit CV is configured by incorporating eight shift registers QA to QH, and incorporates parallel signal input terminals A to H and parallel signals of input terminals A to H. The acquisition terminal LOAD that receives the acquisition signal LOAD for acquisition in the registers QA to QH, the input terminal INPUT that supplies the serial signal to the most upstream shift register QA, the clock terminal CLOCK that receives the shift clock CK, and the most downstream shift. It is configured to have an output terminal QH that receives a serial signal from the register QH.

As described above, in this embodiment, the model discrimination code is supplied to the input terminals A to H of the PS conversion circuit CV0 (model discrimination board BD0), and the input terminal of the PS conversion circuit CV1 (design discrimination board BD1). The design code and the like are supplied to A to H, and the sensor signal SN and others specifying the origin position of the effect motor MOi are supplied to the input terminals A to H of the PS conversion circuit CV2 (sensor & switch board BD2).

Therefore, when the acquisition terminals LOAD of the PS conversion circuits CV0 to CV2 receive a negative logic latch pulse (acquisition signal LOAD), the above parallel signals supplied to the input terminals A to H are transferred to the built-in registers QA to QH. It will be acquired (see FIG. 11 (b)). After that, each time the clock terminal CLOCK receives the shift clock CK, the data of the built-in registers QA to QH are shifted to the downstream side. As shown in the figure, the CLOCK INHIBIT terminal is fixed to the L level, so by receiving eight shift clocks CK, the acquisition data of the PS conversion circuit on the upstream side moves to the PS conversion circuit on the downstream side. Will be done. The shift clock CK1 to which the serial port S1 is output is logically inverted to become the shift clock CK for the PS conversion circuits CV0 to CV2.

FIG. 11B is a time chart illustrating the shift operation, and shows a state in which the 1-byte data (ABCDEFGH) acquired in synchronization with the acquisition signal LOAD is shifted in synchronization with the shift clock CK. There is. That is, for example, the output QA of the most upstream register of the second stage (CV1) changes to the shift clock CK corresponding to the change of the output QH of the most downstream register of the first stage (CV0) as shown in the figure. It is shown that the changes are H-> G-> F-> E-> D-> C-> B-> A in synchronization with each other.

Subsequently, returning to FIG. 10, the serial ports S0 and S1 will be described in more detail. The serial output port S0 has a transmission data register DR that receives 1-byte data from the CPU, a transmission shift register SR that receives transfer of 1-byte data from the transmission data register DR and serially outputs drive data SDAT0, and the inside of the serial port. It is configured to have a large number of control registers RG that manage the operating state and a baud rate generator BG that receives the output pulse Φ of the counter circuit CT and outputs the clock signal CK0 of the division ratio specified by the control register RG. There is.

The control register RG of the serial output port S0 includes a READable control register including an empty bit EMP, and indicates whether or not the transmission data register DR can accept new data. That is, it is shown that when the transmission of the 1-byte data of the transmission shift register SR is completed, the empty bit EMP transitions to the H level (empty level) and new data can be written to the transmission data register DR. Therefore, the CPU writes the new data to the transmission data register DR after confirming that the empty bit EMP is at the H level.

Further, the control register RG of the serial port S0 includes a control register capable of WRITE including the transmission permission bit TXE, and when the CPU sets the transmission permission bit TXE to the ON (H) level, the serial output port S0 Transmission operation is permitted, and when set to the OFF level, transmission operation is prohibited. Therefore, in this embodiment, the CPU sets the transmission permission bit TXE to the ON state at the start of the transmission process, and resets the transmission permission bit TXE to the OFF level at the end of the transmission process (see FIG. 10B). ).

FIG. 10B is a time chart showing the operation of the serial output port S0 at the start of transmission. As shown in the figure, when the serial output port S0 is in the transmission prohibited state (TXE = L), or after the data in the transmission data register DR is serially output, the clock signal CK is at the H level in the fixed state. Further, the transmission data register DR is empty, and the empty bit EMP is also H level (empty level).

Then, after the CPU sets the transmission permission bit TXE to the ON state (transmission permission state), when the transmission data of the first byte is written to the transmission data register DR, the empty bit EMP transitions to the L level, and then. After the lapse of a predetermined time (τ), the transmission data of the first byte is transferred to the transmission shift register SR, and the serial transmission operation is started.

Further, since the transmission data is transferred to the transmission shift register SR, the empty bit EMP shifts to the H level (empty level) in response to the start of serial transmission of the first bit. Therefore, the CPU will write the second byte transmission data to the transmission data register DR after confirming the H-level empty bit EMP.

Then, the empty bit EMP transitions to the L level (full level) in response to the data writing operation to the transmission data register DR. After that, when all the transmission data of the first byte is transmitted, the data of the second byte is transferred from the transmission data register DR to the transmission shift register SR, the data transmission of the second byte is started, and the empty bit EMP. Transitions to the H level.

This empty bit EMP changes to the L level corresponding to the data writing operation of the third byte to the transmission data register DR, but maintains the H level when no new data is written, as shown in the figure. .. Further, after all the data is transmitted, the clock signal CK maintains the H level and does not change.

Although not particularly limited, in this embodiment, 1-byte data is transmitted from the MSB (Most Significant Bit) to the LSB (Least Significant Bit) in synchronization with the clock signal CK0 in accordance with the internal operation of the motor driver DV. The operation is set to be executed (MSB first), and an appropriate set value is set in the corresponding control register RG. Further, as shown in the figure, the transmission operation proceeds in synchronization with the falling edge of the clock signal CK0.

In this embodiment, the serial port S0 that operates as described above is used to control the effect motor MOi of the first group and the solenoid member SL that shuts off the outside air passage. That is, the serial output port S0 outputs the drive data SDATA0 including the drive data of the effect motor MOi and the solenoid member SL in synchronization with the clock signal CK0. The configuration of the motor drive board 37 that receives the drive data SDAT0 and the operation of the motor driver DV are as described above.

Corresponding to the configuration of the motor drive board 37 shown in FIG. 10, the serial port S0 outputs the drive data SDAT0 in synchronization with the clock signal CK0 based on the control of the CPU, and all the drive data. After the transmission of SDAT0 is completed, the parallel output port Po outputs a LATCH signal based on the control of the CPU. As a result, the effect motor MOi of the first group and the solenoid member SL that shuts off the outside air passage operate based on the new drive data.

When the power is turned on or when the motor effect is finished, the parallel output port Po outputs a reset signal RESET to the motor driver DV based on the control of the CPU, thereby clearing all the drive output terminals at once. is doing. As a result, the effect motor MOi of the first group is stopped, and the outside air passage is closed.

Next, the serial input port S1 receives the serial data SDAT1 from the outside and performs parallel conversion, the receive shift register SR', the receive data register DR' which receives the transfer of 1-byte data from the receive shift register SR', and 1 from the CPU. The transmission data register DR that receives byte data, a large number of control registers RG that manage the internal operating state of the serial port, and the clock signal CK1 with the division ratio specified by the control register RG that receives the output pulse Φ of the counter circuit CT. It is configured to have a baud rate generator BG for output.

The control register RG of the serial input port S1 also includes a completion bit FULL indicating that data having a length of 1 byte has been transferred to the received data register DR'. ), And then the received data is acquired from the received data register DR'.

Further, the control register RG of the serial port S1 includes a control register capable of wrITE including the reception permission bit RXE. Then, when the CPU sets the reception permission bit RXE to the ON (H) level, the reception operation of the serial input port S1 is permitted, and when the reception permission bit RXE is set to the OFF level, the reception operation is prohibited. Therefore, in this embodiment, the CPU sets the reception permission bit RXE to the ON state at the start of the reception processing, and resets the reception permission bit RXE to the OFF level at the end of the reception processing (see FIG. 11D). ).

FIG. 11D is a time chart showing a data reception operation for the serial input port S1. In the case of the figure, for convenience, the received data has a total length of 2 bytes, but the received data has an appropriate required byte length. Then, when the serial input port S1 is in the reception prohibition state (RXE = L), or after the reception processing of the required byte length is completed, the clock signal CK1 is the H level in the fixed state. The completion bit FULL is also an L level (empty level).

Then, when the CPU sets the reception permission bit RXE to the ON state and then writes the dummy data of the first byte to the transmission data register DR, the output of the clock signal CK1 is started.

As described with respect to FIG. 11B, in the PS conversion circuits CV2 to CV0, when the acquisition signal LOAD = H, the serial data is synchronized with the falling edge of the clock signal CK1 (the rising edge of the shift clock CK). Outputs SDAT1. Therefore, the serial input port S1 receives the serial data SDAT1 bit by bit in the reception shift register in synchronization with the rising edge of the clock signal CK1 output by the serial input port S1 corresponding to the shift operation of the PS conversion circuits CV2 to CV0. Get to SR'.

In this way, when the data acquired in the reception shift register SR'in synchronization with the clock signal CK1 reaches 8 bits, the 8-bit acquisition data is transferred from the reception shift register SR'to the reception data register DR'. At the same time, the completion bit FULL is set to the H level (completion level). Therefore, the CPU acquires the received data of the first byte from the received data register DR'after confirming the H level completion bit FULL.

Then, the completion bit FULL returns from the H level to the L level (empty level) in response to the acquisition operation of the CPU, so that the CPU changes the completion bit FULL to the H level again if necessary. Wait, the received data of the second byte will be acquired.

Since the clock signal CK1 returns to the steady level (H) when the reception operation of the preset number of data bytes (up to 3 bytes in this embodiment) is completed or the reception permission bit RXE is set to the OFF level. , No extra data is transmitted serially.

As shown in FIG. 11B, the parallel output port Po outputs a negative logic latch pulse (acquisition signal LOAD) based on the control of the CPU prior to the series of serial reception operations. be.

As described above, a maximum of 3 bytes of data is acquired by a series of serial reception operations. Then, as shown in FIG. 11C, the acquired data is configured to be received in the order of various switch signals (CV2) → various sensor signals (CV2 + CV1) → design code (CV1) → discrimination code (CV0). ing.

Therefore, when the power is turned on, the 8 × 3 bit clock signal CK1 is output, the model identification code is acquired, and then the matching determination between the game board 4 and the frame unit 5 is performed. When the frame unit 5 does not match the game board 4, the effect control unit 22 transmits a control command CMD'to the image control unit 23 to execute an abnormality notification operation on the main display device DS1.

However, once the matching determination is made, it is not necessary to acquire the identification code of the model. Therefore, after that, the 8 × 2 bit clock signal CK1 is output periodically to be used as various switch signals (CV2). , Various sensor signals (CV2 + CV1) and design code (CV1) are acquired.

As described above, the sensor signal acquired on a regular basis also includes the sensor signal SN of the origin sensor arranged at the origin position of the effect motor MOi, and the necessary motor effect is executed. Further, based on the acquired design code, an image effect matching the design of the design unit 6 is executed. Specifically, for example, the clothing design of the main character is made to correspond. The design code acquisition process may be limited to the time when the power is turned on, but in consideration of the possibility of bit garbled, the design code is repeatedly acquired in this embodiment. Therefore, there is no possibility that the image production that does not match the design of the design unit 6 will be continued under any noise environment.

Although the examples of the present invention have been described in detail above, the specific description contents are not limited to the present invention. For example, in the embodiment, the design code (CV1) and the discrimination code (CV0) are acquired by the effect control unit 22, but the design code (CV1) and the determination code (CV0) are not limited in any way. In this case, the discriminant code acquired by the payout control unit 24 is transmitted to the main control unit 21 as a part of the operation start signal BGN, so that the game operation is performed when the frame unit 5 does not match the game board 4. Can perform controls that do not start. It is also possible to prohibit the firing operation of the game ball.

GM gaming machine 22 Computer circuit GM1 Frame side member 1 First member (outer frame)
2 Second member (inner frame)
3 Third member (front frame body)
4 Game board 5 Frame unit 6 Design unit

Claims (1)

A gaming machine that executes all or part of an image effect, a lamp effect, or an audio effect in response to a lottery result of a predetermined lottery process.
The gaming machine is configured to include a gaming board that holds a computer circuit that controls an effect operation, and a frame-side member having a plurality of members.
The frame-side member can be changed to the first member constituting the outer frame, the second member mounted on the first member, the third member mounted on the second member, and the third member. It is composed of a changing member to be mounted and
The game board corresponding to the modified member is detachably attached to the second member.
The change member is configured to have a discriminant code corresponding to the game board and a drive device that contributes to the effect operation.
The computer circuit outputs a clock signal and drives the drive device in synchronization with the clock signal and a first serial port for receiving the serial signal of the discrimination code in synchronization with the output clock signal. A second serial port is provided to output drive data,
When the power is turned on, the computer circuit acquires the discrimination code from the change member via the first serial port, and determines whether the change member is a member corresponding to the game board or not. , A gaming machine characterized in that it is configured to perform anomaly notification if it does not match.

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