JP5859185B2 - 低複雑性命令プリフェッチシステム - Google Patents

低複雑性命令プリフェッチシステム Download PDF

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Publication number
JP5859185B2
JP5859185B2 JP2009540408A JP2009540408A JP5859185B2 JP 5859185 B2 JP5859185 B2 JP 5859185B2 JP 2009540408 A JP2009540408 A JP 2009540408A JP 2009540408 A JP2009540408 A JP 2009540408A JP 5859185 B2 JP5859185 B2 JP 5859185B2
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Japan
Prior art keywords
instruction
line
cache
fetch address
fetch
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Expired - Fee Related
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JP2009540408A
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English (en)
Japanese (ja)
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JP2010512580A (ja
Inventor
モロー、マイケル・ウィリアム
ディーフェンダーファー、ジェームズ・ノリス
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
JP2009540408A 2006-12-08 2007-12-03 低複雑性命令プリフェッチシステム Expired - Fee Related JP5859185B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/608,309 US8060701B2 (en) 2006-12-08 2006-12-08 Apparatus and methods for low-complexity instruction prefetch system
US11/608,309 2006-12-08
PCT/US2007/086254 WO2008073741A1 (en) 2006-12-08 2007-12-03 Methods and apparatus for low-complexity instruction prefetch system

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2015018674A Division JP6030160B2 (ja) 2006-12-08 2015-02-02 低複雑性命令プリフェッチシステム

Publications (2)

Publication Number Publication Date
JP2010512580A JP2010512580A (ja) 2010-04-22
JP5859185B2 true JP5859185B2 (ja) 2016-02-10

Family

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Family Applications (2)

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JP2009540408A Expired - Fee Related JP5859185B2 (ja) 2006-12-08 2007-12-03 低複雑性命令プリフェッチシステム
JP2015018674A Expired - Fee Related JP6030160B2 (ja) 2006-12-08 2015-02-02 低複雑性命令プリフェッチシステム

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2015018674A Expired - Fee Related JP6030160B2 (ja) 2006-12-08 2015-02-02 低複雑性命令プリフェッチシステム

Country Status (7)

Country Link
US (1) US8060701B2 (enExample)
EP (1) EP2097809B1 (enExample)
JP (2) JP5859185B2 (enExample)
KR (1) KR101095204B1 (enExample)
CN (2) CN101548266B (enExample)
AT (1) ATE513261T1 (enExample)
WO (1) WO2008073741A1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7917731B2 (en) * 2006-08-02 2011-03-29 Qualcomm Incorporated Method and apparatus for prefetching non-sequential instruction addresses
US20110231634A1 (en) * 2010-03-22 2011-09-22 Fishel Liran System and method for grouping alternative possibilities in an unknown instruction path
EP2798470A4 (en) * 2011-12-29 2015-07-15 Intel Corp PRE-ACQUISITION OF ANTEMOTE BY MANAGED INSTRUCTION
US10175987B2 (en) * 2016-03-17 2019-01-08 International Business Machines Corporation Instruction prefetching in a computer processor using a prefetch prediction vector
US20210081323A1 (en) * 2019-09-12 2021-03-18 Marvell International Ltd. Method of improving l1 icache performance with large programs
CN111399913B (zh) * 2020-06-05 2020-09-01 浙江大学 一种基于预取的处理器加速取指方法
US11409657B2 (en) 2020-07-14 2022-08-09 Micron Technology, Inc. Adaptive address tracking
US11422934B2 (en) * 2020-07-14 2022-08-23 Micron Technology, Inc. Adaptive address tracking
US11561796B2 (en) 2020-07-15 2023-01-24 International Business Machines Corporation Linked miss-to-miss instruction prefetcher
CN112416438A (zh) * 2020-12-08 2021-02-26 王志平 一种流水线预分支的实现方法
US11822922B2 (en) 2021-12-31 2023-11-21 International Business Machines Corporation Miss-driven instruction prefetching
CN115480826B (zh) * 2022-09-21 2024-03-12 海光信息技术股份有限公司 分支预测器、分支预测方法、装置和计算设备

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS615357A (ja) * 1984-06-07 1986-01-11 Fujitsu Ltd デ−タ処理装置
JPS63146143A (ja) * 1986-12-10 1988-06-18 Hitachi Ltd 記憶装置の転送制御方式
JP2786886B2 (ja) * 1989-05-17 1998-08-13 富士通株式会社 プリフェッチ制御方法およびプリフェッチ制御装置
JPH0588891A (ja) * 1991-09-30 1993-04-09 Toshiba Corp キヤツシユメモリ制御装置
JP3590427B2 (ja) * 1994-08-30 2004-11-17 株式会社ルネサステクノロジ 先行読出機能付命令キャッシュメモリ
US5809529A (en) * 1995-08-23 1998-09-15 International Business Machines Corporation Prefetching of committed instructions from a memory to an instruction cache
US6119222A (en) * 1996-12-23 2000-09-12 Texas Instruments Incorporated Combined branch prediction and cache prefetch in a microprocessor
US6728839B1 (en) * 1998-10-28 2004-04-27 Cisco Technology, Inc. Attribute based memory pre-fetching technique
JP2000242557A (ja) * 1999-02-25 2000-09-08 Nec Corp キャッシュプリフェッチ装置
JP2000347934A (ja) * 1999-06-02 2000-12-15 Matsushita Electric Ind Co Ltd キャッシュメモリ装置
JP2001142698A (ja) * 1999-11-12 2001-05-25 Mitsubishi Electric Corp メモリアクセス方式
US6584549B2 (en) * 2000-12-29 2003-06-24 Intel Corporation System and method for prefetching data into a cache based on miss distance
US20030105926A1 (en) * 2001-12-03 2003-06-05 International Business Machies Corporation Variable size prefetch cache
US7032076B2 (en) * 2002-09-16 2006-04-18 Intel Corporation Prefetching data in a computer system

Also Published As

Publication number Publication date
CN101548266B (zh) 2012-12-05
JP2015122094A (ja) 2015-07-02
CN102968294A (zh) 2013-03-13
WO2008073741A1 (en) 2008-06-19
EP2097809B1 (en) 2011-06-15
JP2010512580A (ja) 2010-04-22
CN102968294B (zh) 2015-07-22
JP6030160B2 (ja) 2016-11-24
ATE513261T1 (de) 2011-07-15
EP2097809A1 (en) 2009-09-09
KR20090095633A (ko) 2009-09-09
KR101095204B1 (ko) 2011-12-16
US20080140996A1 (en) 2008-06-12
US8060701B2 (en) 2011-11-15
CN101548266A (zh) 2009-09-30

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