EP2798470A4 - Managed instruction cache prefetching - Google Patents

Managed instruction cache prefetching

Info

Publication number
EP2798470A4
EP2798470A4 EP11878987.4A EP11878987A EP2798470A4 EP 2798470 A4 EP2798470 A4 EP 2798470A4 EP 11878987 A EP11878987 A EP 11878987A EP 2798470 A4 EP2798470 A4 EP 2798470A4
Authority
EP
European Patent Office
Prior art keywords
instruction cache
managed instruction
cache prefetching
prefetching
managed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP11878987.4A
Other languages
German (de)
French (fr)
Other versions
EP2798470A1 (en
Inventor
Kyriakos A Stavrou
Codina Enric Gibert
Josep M Codina
Requena Crispin Gomez
Antonio Gonzalez
Mirem Hyuseinova
Christos E Kotselidis
Fernando Latorre
Pedro Lopez
Marc Lupon
Carlos Madriles
Grigorios Magklis
Pedro Marcuello
Vicente Alejandro Martinez
Raul Martinez
Daniel Ortega
Demos Pavlou
Georgios Tournavitis
Polychronis Xekalakis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of EP2798470A1 publication Critical patent/EP2798470A1/en
Publication of EP2798470A4 publication Critical patent/EP2798470A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30047—Prefetch instructions; cache control instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3848—Speculative instruction execution using hybrid branch prediction, e.g. selection between prediction techniques
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/452—Instruction code

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
EP11878987.4A 2011-12-29 2011-12-29 Managed instruction cache prefetching Withdrawn EP2798470A4 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2011/067964 WO2013101121A1 (en) 2011-12-29 2011-12-29 Managed instruction cache prefetching

Publications (2)

Publication Number Publication Date
EP2798470A1 EP2798470A1 (en) 2014-11-05
EP2798470A4 true EP2798470A4 (en) 2015-07-15

Family

ID=48698355

Family Applications (1)

Application Number Title Priority Date Filing Date
EP11878987.4A Withdrawn EP2798470A4 (en) 2011-12-29 2011-12-29 Managed instruction cache prefetching

Country Status (5)

Country Link
US (1) US9811341B2 (en)
EP (1) EP2798470A4 (en)
CN (1) CN104220980B (en)
TW (1) TWI620123B (en)
WO (1) WO2013101121A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106383926A (en) * 2016-08-29 2017-02-08 北京中电华大电子设计有限责任公司 Instruction prefetching method based on Cortex-M series processor and circuit

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US10558437B1 (en) * 2013-01-22 2020-02-11 Altera Corporation Method and apparatus for performing profile guided optimization for high-level synthesis
US10154072B2 (en) * 2014-09-17 2018-12-11 Microsoft Technology Licensing, Llc Intelligent streaming of media content
US9891916B2 (en) * 2014-10-20 2018-02-13 Via Technologies, Inc. Dynamically updating hardware prefetch trait to exclusive or shared in multi-memory access agent system
JP6457836B2 (en) * 2015-02-26 2019-01-23 ルネサスエレクトロニクス株式会社 Processor and instruction code generation device
US10719321B2 (en) 2015-09-19 2020-07-21 Microsoft Technology Licensing, Llc Prefetching instruction blocks
US20170083338A1 (en) * 2015-09-19 2017-03-23 Microsoft Technology Licensing, Llc Prefetching associated with predicated load instructions
US10915446B2 (en) 2015-11-23 2021-02-09 International Business Machines Corporation Prefetch confidence and phase prediction for improving prefetch performance in bandwidth constrained scenarios
US10296463B2 (en) * 2016-01-07 2019-05-21 Samsung Electronics Co., Ltd. Instruction prefetcher dynamically controlled by readily available prefetcher accuracy
US10191845B2 (en) 2017-05-26 2019-01-29 International Business Machines Corporation Prefetch performance
CN111209043B (en) * 2018-11-21 2022-07-12 华夏芯（北京）通用处理器技术有限公司 Method for realizing instruction prefetching in front-end pipeline by using look-ahead pointer method
CN110825442B (en) * 2019-04-30 2021-08-06 成都海光微电子技术有限公司 Instruction prefetching method and processor
US20210342134A1 (en) * 2020-04-29 2021-11-04 Intel Corporation Code prefetch instruction
US11561796B2 (en) * 2020-07-15 2023-01-24 International Business Machines Corporation Linked miss-to-miss instruction prefetcher
CN112579175B (en) * 2020-12-14 2023-03-31 成都海光微电子技术有限公司 Branch prediction method, branch prediction device and processor core
US11960893B2 (en) * 2021-12-29 2024-04-16 International Business Machines Corporation Multi-table instruction prefetch unit for microprocessor
US11822922B2 (en) 2021-12-31 2023-11-21 International Business Machines Corporation Miss-driven instruction prefetching

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US20060174090A1 (en) * 2005-02-03 2006-08-03 Sartorius Thomas A Power efficient instruction prefetch mechanism
US7441110B1 (en) * 1999-12-10 2008-10-21 International Business Machines Corporation Prefetching using future branch path information derived from branch prediction

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US5704053A (en) * 1995-05-18 1997-12-30 Hewlett-Packard Company Efficient explicit data prefetching analysis and code generation in a low-level optimizer for inserting prefetch instructions into loops of applications
US6055621A (en) * 1996-02-12 2000-04-25 International Business Machines Corporation Touch history table
US6029228A (en) * 1996-12-31 2000-02-22 Texas Instruments Incorporated Data prefetching of a load target buffer for post-branch instructions based on past prediction accuracy's of branch predictions
US5822790A (en) * 1997-02-07 1998-10-13 Sun Microsystems, Inc. Voting data prefetch engine
US6167506A (en) * 1997-11-17 2000-12-26 Advanced Micro Devices, Inc. Replacing displacement in control transfer instruction with encoding indicative of target address, including offset and target cache line location
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US6799263B1 (en) * 1999-10-28 2004-09-28 Hewlett-Packard Development Company, L.P. Prefetch instruction for an unpredicted path including a flush field for indicating whether earlier prefetches are to be discarded and whether in-progress prefetches are to be aborted
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WO1998003908A1 (en) * 1996-07-24 1998-01-29 Idea Corporation Instruction prefetch mechanism utilizing a branch predict instruction
US7441110B1 (en) * 1999-12-10 2008-10-21 International Business Machines Corporation Prefetching using future branch path information derived from branch prediction
US20060174090A1 (en) * 2005-02-03 2006-08-03 Sartorius Thomas A Power efficient instruction prefetch mechanism

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See also references of WO2013101121A1 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106383926A (en) * 2016-08-29 2017-02-08 北京中电华大电子设计有限责任公司 Instruction prefetching method based on Cortex-M series processor and circuit

Also Published As

Publication number Publication date
US20140019721A1 (en) 2014-01-16
US9811341B2 (en) 2017-11-07
CN104220980A (en) 2014-12-17
EP2798470A1 (en) 2014-11-05
CN104220980B (en) 2018-01-19
WO2013101121A1 (en) 2013-07-04
TW201346757A (en) 2013-11-16
TWI620123B (en) 2018-04-01

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