JP5853139B2 - 三次元集積回路設計装置、三次元集積回路設計方法、プログラム - Google Patents

三次元集積回路設計装置、三次元集積回路設計方法、プログラム Download PDF

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JP5853139B2
JP5853139B2 JP2012542047A JP2012542047A JP5853139B2 JP 5853139 B2 JP5853139 B2 JP 5853139B2 JP 2012542047 A JP2012542047 A JP 2012542047A JP 2012542047 A JP2012542047 A JP 2012542047A JP 5853139 B2 JP5853139 B2 JP 5853139B2
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integrated circuit
temperature
standard cell
multilayer chip
circuit design
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JPWO2012120792A1 (ja
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高志 森本
高志 森本
橋本　隆
隆 橋本
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Panasonic Intellectual Property Management Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H01L27/0211—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique adapted for requirements of temperature
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2012542047A 2011-03-09 2012-02-17 三次元集積回路設計装置、三次元集積回路設計方法、プログラム Expired - Fee Related JP5853139B2 (ja)

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JP2011052026 2011-03-09
JP2011052026 2011-03-09
JP2012542047A JP5853139B2 (ja) 2011-03-09 2012-02-17 三次元集積回路設計装置、三次元集積回路設計方法、プログラム
PCT/JP2012/001057 WO2012120792A1 (fr) 2011-03-09 2012-02-17 Dispositif de conception de circuit intégré tridimensionnel, procédé de conception de circuit intégré tridimensionnel et programme

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JPWO2012120792A1 JPWO2012120792A1 (ja) 2014-07-17
JP5853139B2 true JP5853139B2 (ja) 2016-02-09

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