JP5821765B2 - 電子装置の製造方法 - Google Patents
電子装置の製造方法 Download PDFInfo
- Publication number
- JP5821765B2 JP5821765B2 JP2012094077A JP2012094077A JP5821765B2 JP 5821765 B2 JP5821765 B2 JP 5821765B2 JP 2012094077 A JP2012094077 A JP 2012094077A JP 2012094077 A JP2012094077 A JP 2012094077A JP 5821765 B2 JP5821765 B2 JP 5821765B2
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- substrate
- adhesive
- elastic member
- load
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Description
基板、電子部品、および接着剤を用意する用意工程と、接着剤中に弾性変形可能な弾性部材(40)を含有させた状態で、接着剤を基板の一面と電子部品との間に介在させる接着剤配置工程と、次に、電子部品に第1の荷重(F1)を印加して、接着剤および弾性部材を介して電子部品を基板に押し付け、弾性部材を弾性変形によって縮ませることにより、電子部品と基板の一面との距離が所定間隔よりも狭くなるようにする押し付け工程と、続いて、第1の荷重よりも小さい第2の荷重(F2)を電子部品に印加しながら、弾性部材が復元しようとする弾性力(F3)により、電子部品を基板の一面から離れる方向に移動させ、電子部品と基板の一面との距離を所定間隔まで戻す復元工程と、しかる後、第2の荷重の印加を行いつつ電子部品と基板の一面との距離が所定間隔となった状態で、接着剤を硬化させる硬化工程と、を備えることを特徴とする。
本発明の第1実施形態に係る電子装置S1について、図1を参照して説明する。この電子装置S1は、たとえば自動車に搭載されるECU(電子制御装置)の構成要素等として適用されるものである。
本発明の第2実施形態にかかる電子装置の製造方法について、図3、図4を参照して述べる。ここでは、本実施形態の製造方法と上記第1実施形態との相違点を中心に述べることとする。
本発明の第3実施形態にかかる電子装置の製造方法について、図5、図6を参照して述べる。ここでは、本実施形態の製造方法と上記第1実施形態との相違点を中心に述べることとする。
なお、上記各実施形態では、電子部品20の全体が接着剤30を介して基板10に支持された構成であった。
11 基板の一面
20 電子部品
30 接着剤
40 弾性部材
F1 第1の荷重
F2 第2の荷重
L1 所定間隔
L2 所定間隔よりも狭い間隔
Claims (3)
- 基板(10)と、前記基板の一面(11)上に所定間隔(L1)を介して搭載された電子部品(20)と、前記基板の一面と前記電子部品との間に介在し前記基板と前記電子部品とを接着する接着剤(30)と、を備える電子装置の製造方法であって、
前記基板、前記電子部品、および前記接着剤を用意する用意工程と、
前記接着剤中に弾性変形可能な弾性部材(40)を含有させた状態で、前記接着剤を前記基板の一面と前記電子部品との間に介在させる接着剤配置工程と、
次に、前記電子部品に第1の荷重(F1)を印加して、前記接着剤および前記弾性部材を介して前記電子部品を前記基板に押し付け、前記弾性部材を弾性変形によって縮ませることにより、前記電子部品と前記基板の一面との距離が前記所定間隔よりも狭くなるようにする押し付け工程と、
続いて、前記第1の荷重よりも小さい第2の荷重(F2)を前記電子部品に印加しながら、前記弾性部材が復元しようとする弾性力(F3)により、前記電子部品を前記基板の一面から離れる方向に移動させ、前記電子部品と前記基板の一面との距離を前記所定間隔まで戻す復元工程と、
しかる後、前記第2の荷重の印加を行いつつ前記電子部品と前記基板の一面との距離が前記所定間隔となった状態で、前記接着剤を硬化させる硬化工程と、を備えることを特徴とする電子装置の製造方法。 - 前記接着剤配置工程では、予め前記弾性部材を前記基板の一面に固定しておき、その後、前記接着剤を前記基板の一面上に塗布し、続いて前記基板の一面上に前記電子部品を載置することにより、
前記弾性部材を含有する前記接着剤を前記基板の一面と前記電子部品との間に介在させるようにすることを特徴とする請求項1に記載の電子装置の製造方法。 - 前記接着剤配置工程では、予め前記弾性部材を前記電子部品に固定しておき、その後、前記接着剤を前記基板の一面上に塗布し、続いて前記基板の一面上に前記電子部品を載置することにより、
前記弾性部材を含有する前記接着剤を前記基板の一面と前記電子部品との間に介在させるようにすることを特徴とする請求項1に記載の電子装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012094077A JP5821765B2 (ja) | 2012-04-17 | 2012-04-17 | 電子装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012094077A JP5821765B2 (ja) | 2012-04-17 | 2012-04-17 | 電子装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013222853A JP2013222853A (ja) | 2013-10-28 |
JP5821765B2 true JP5821765B2 (ja) | 2015-11-24 |
Family
ID=49593617
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012094077A Expired - Fee Related JP5821765B2 (ja) | 2012-04-17 | 2012-04-17 | 電子装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5821765B2 (ja) |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3608476B2 (ja) * | 2000-06-09 | 2005-01-12 | 松下電工株式会社 | 半導体チップ実装回路基板及び回路基板への半導体チップの実装方法 |
US20090289098A1 (en) * | 2005-12-06 | 2009-11-26 | Katsumi Terada | Chip Mounting Apparatus and Chip Mounting Method |
-
2012
- 2012-04-17 JP JP2012094077A patent/JP5821765B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2013222853A (ja) | 2013-10-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6518461B2 (ja) | 実装装置および実装方法 | |
JP2010118373A (ja) | 半導体装置の製造方法 | |
JP6931311B2 (ja) | 異方性導電膜またはペーストを用いて高さの異なる複数のチップを可撓性基板上に同時に接着する方法 | |
JP2009260247A (ja) | 電子部品及び電子部品の製造方法 | |
US10276592B2 (en) | Display substrate, method of fabricating the same, display panel and pressure welding device | |
KR102019298B1 (ko) | 전사 방법 및 실장 방법 | |
TWI378749B (en) | Semiconductor device producing method, semiconductor device producing apparatus and pin | |
JP2001237274A5 (ja) | ||
JP5285144B2 (ja) | チップ部品実装構造、チップ部品実装方法および液晶表示装置 | |
JP5821765B2 (ja) | 電子装置の製造方法 | |
KR20070077087A (ko) | 복합 시트 | |
JP2008192725A (ja) | 半導体装置及びその製造方法並びに半導体装置の製造装置 | |
US10276538B2 (en) | Electronic device having an under-fill element, a mounting method of the same, and a method of manufacturing a display apparatus having the electronic device | |
JP2014225563A (ja) | 半導体装置の製造方法 | |
JP2005129757A (ja) | 半導体装置の接続方法 | |
JP7453035B2 (ja) | 圧着ヘッド、これを用いた実装装置および実装方法 | |
WO2016125763A1 (ja) | 実装装置および実装方法 | |
JP2014063905A (ja) | 半導体装置の製造方法、半導体装置 | |
JP3999222B2 (ja) | フリップチップ実装方法およびフリップチップ実装構造 | |
JP2010225924A (ja) | 電子部品の実装装置及び実装方法 | |
JP4389696B2 (ja) | 半導体装置およびその製造方法 | |
JP2004327531A (ja) | 撮像装置 | |
JP2016189427A (ja) | 実装方法および実装装置 | |
JP6371699B2 (ja) | 半導体パッケージの製造方法 | |
JP4840953B2 (ja) | 光半導体装置の作製方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20140620 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20150624 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20150630 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150805 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20150908 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20150921 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 5821765 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |