JP5795934B2 - Operational amplifier - Google Patents

Description

  The present invention relates to an operational amplifier, and more particularly to an operational amplifier in which output phase inversion is prevented.

As a conventional operational amplifier, for example, the one having the configuration shown in FIG. 6 is known.
Such an operational amplifier is roughly divided into an input unit 10a composed of a differential circuit composed of transistors Q1 and Q2, and a folded cascode unit 20a in which a folded cascode amplifier circuit is configured.
In this operational amplifier, since a so-called inversion prevention circuit is not provided, when the input terminal voltage at the input terminals 100 and 200 is reduced by 0.7 V from the voltage at the power supply terminal 400, the output voltage as shown in FIG. Changes and causes the output phase inversion.
In FIG. 7, the dotted line indicates the level of the power supply voltage, the solid characteristic line indicates the change in the input voltage, and the two-dot chain characteristic line indicates the change in the output voltage. Here, the change in the output voltage is the same as the change in the input voltage represented by the solid characteristic line before and after the above-described output phase inversion, and overlaps with the solid characteristic line. .

For example, an operational amplifier having the circuit configuration shown in FIG. 8 is known as an operational amplifier in which measures for preventing the output phase inversion as described above are taken (see, for example, Patent Document 1).
Hereinafter, a conventional operational amplifier having an output phase inversion prevention function will be described with reference to FIG.
FIG. 6 shows that this operational amplifier is roughly divided into an input unit 10b composed of a differential circuit composed of transistors Q1 and Q2 and a folded cascode unit 20b in which a folded cascode amplifier circuit is configured. This is basically the same as the conventional circuit.

  In such an operational amplifier, in the basic configuration described above, the first diode D1 is further connected between the inverting input terminal 100 and the collector of the transistor Q2 so that the anode is on the collector side of the transistor Q2. On the other hand, a second diode D2 is provided between the non-inverting input terminal 200 and the collector of the transistor Q1 so that the anode is on the collector side of the transistor Q2.

In this configuration, the output phase inversion prevention operation when the voltage at the non-inverting input terminal 200 is lower than the voltage at the first power supply terminal 400 will be described.
First, considering the case where the voltage of the first power supply terminal 400 is 0 V and the terminal voltage V200 of the non-inverting input terminal 200 is V200 <−0.7 (V), at this time, the collector-base of the transistor Q2 A current ID4 flows through the parasitic diode D4. At the same time, a current ID2 flows through the diode D2 connected to the non-inverting input terminal 200. When such a current flows, the voltage VB at the point B and the voltage VA at the point A are lowered. In FIG. 8, the parasitic diodes D3 and D4 are represented by dotted lines.

  Here, for convenience, when the anode-cathode voltage of the parasitic diode D4 of the transistor Q2 is VD4 and the anode-cathode voltage of the diode D2 is VD2, the voltages of VA and VB are expressed by the following equations 1 and 2. Will be.

  VA = V200 + VD2 = V200 + VT * ln {ID2 / (nD2 * Is)} Equation 1

  VB = V200 + VD4 = V200 + VT * ln {ID4 / (nD4 * Is)} Equation 2

Here, VT is a thermal voltage, which is about 26 (mV) when the ambient temperature is 300K. Further, Is is a reverse saturation current, and nD2 and nD4 are magnifications with respect to the unit element area.
When the relationship of VA> VB is established, output phase inversion does not occur. However, when VA <VB, the behavior of the transistors Q5 and Q6 of the folded cascode portion 20b changes, and output phase inversion occurs. When the condition in this case is expressed numerically, it is expressed by the following Expression 3.

  VA−VB> 0, and ln {ID4 × nD2 / (ID2 × nD4)}> 0 Equation 3

By adjusting nD2 so as to satisfy Equation 3, output phase inversion can be prevented as shown in FIG.
In FIG. 9, the dotted line indicates the power supply voltage level, the solid characteristic line indicates the change in the input voltage, and the two-dot chain characteristic line indicates the change in the output voltage. Here, the change in the output voltage is the same as the change in the input voltage represented by the solid characteristic line before and after the input voltage exceeds the power supply voltage level and before and after the input voltage falls below the power supply voltage level. This overlaps with the characteristic line of the solid line.

However, the circuit shown in FIG. 8 can surely prevent the output phase inversion, but when the voltage at the non-inverting input terminal 200 is lower than the first power supply terminal 400, the base of the folded cascode portion 20b. There is a problem that the base-emitter voltage of the grounded transistors Q5 and Q6 increases and the collector current increases.
This phenomenon will be described below.
First, when the voltage of the first power supply terminal 400 is set to 0 V and the terminal voltage V200 of the non-inverting input terminal 200 becomes V200 <−0.7 (V), the point A which is the emitter potential of the transistors Q5 and Q6. As described above, the potential at the point B is expressed by the equations 1 and 2. At this time, the potential Vc at the point C, which is the base potential of the transistors Q5 and Q6, is given by the following equation 4.

  Vc = Ics3 * R5 + VT * ln {Ics3 / (nQ9 * Is)} Expression 4

Here, Ics3 is the collector current of the transistor Q3, R5 is the resistance value of the load connected to the emitter of the transistor Q9, VT is the thermal voltage, and nQ9 is the magnification of the reverse saturation current Is with respect to the unit element area of the transistor Q9. .
Therefore, the base-emitter potential difference VBEQ5 of the transistor Q5 is expressed by the following equation 5.

  VBEQ5 = Vc-VB = Ics3 * R5 + VT * ln {Ics3 / (nQ9 * Is)}-V200-VT * ln {ID4 / (nD4 * Is)} = Ics3 * R5 + VT * ln {Ics3 * nD4 / (nQ9 * ID4 )}-V200 Formula 5

  Here, it is assumed that the non-inverting input terminal voltage V200 is smaller than −0.7 V, but it is clear from Equation 5 that the base-emitter potential difference VBEQ5 of the transistor Q5 increases as this voltage decreases. It is. When the base-emitter potential difference VBEQ5 of the transistor Q5 increases, the collector current of the transistor Q5 increases, leading to an increase in current consumption of the operational amplifier.

  On the other hand, the base-emitter potential difference VBEQ6 of the transistor Q6 is expressed by Equation 6 below.

  VBEQ6 = Vc-VA = Ics3 * R5 + VT * ln {Ics3 / (nQ9 * Is)}-V200-VT * ln {ID2 / (nD2 * Is)} = Ics3 * R5 + VT * ln {Ics3 * nD2 / (nQ9 * ID2 )}-V200 Formula 6

Similar to the transistor Q5, the base-emitter potential difference VBEQ6 of the transistor Q6 increases as the non-inverting input terminal voltage V200 decreases, and the collector current of the transistor Q6 increases as shown in FIG. There is a problem of causing an increase.
In FIG. 10, a solid characteristic line indicates a change in input voltage, a two-dot chain line characteristic line indicates a change in output voltage, and a one-dot chain line characteristic line indicates a change in collector current. Here, the change of the output voltage is the same as the change of the input voltage represented by the solid characteristic line except for the range where the input voltage exceeds 10V and the range where the input voltage is less than 0V. It overlaps with the characteristic line.

As a measure for solving this problem of increase in current consumption, for example, the circuit configuration shown in FIG. 11 has been proposed (see, for example, Patent Document 2).
Hereinafter, such a circuit will be described with reference to FIG.
The same components as those in the circuit configuration examples shown in FIGS. 6 and 8 are denoted by the same reference numerals, detailed description thereof is omitted, and the following description focuses on the different points. To do.
Such a circuit is configured to be able to suppress an increase in current consumption by controlling the base current of the grounded base transistors Q5 and Q6 of the folded cascode portion 20c. Is constituted by transistors Q7, Q8, Q9 and a current source CS4.

JP 2001-308656 A (page 4-12, FIGS. 1 to 6) JP 2010-28311 A (Page 5-9, FIGS. 1 to 9)

However, the circuit shown in FIG. 11 can suppress an increase in current consumption as described above, but has a disadvantage that the minimum operating power supply voltage is raised by an additional circuit.
Such drawbacks will be described below.
First, when the minimum operating voltage of the conventional circuit shown in FIG. 8 above and V ^{+ (min)} 2, the minimum operating voltage of the conventional circuit shown in FIG. 11 and V ^{+ (min)} 3, minimum The operating power supply voltage is expressed by Expression 7 and Expression 8, respectively.

V ⁺ (min) 2 = VCEQ5 + VBEQ3 + VR4 Equation 7

V ⁺ (min) 3 = VCECS4 + VBEQ8 + VBEQ9 ... Equation 8

Where VCEQ5 is the voltage drop between the collector and emitter of the transistor Q5, VBEQ3 is the base-emitter voltage of the transistor Q3, VR4 is the voltage drop at the load R4, VCECS4 is the voltage drop at the current source CS4, and VBEQ8 is the transistor The base-emitter voltage of Q8, VBEQ9, is the base-emitter voltage of transistor Q9.
In the conventional circuit shown in FIG. 11, it is desirable to operate as a so-called single power supply operational amplifier in which the voltage gain of the operational amplifier is maintained even when the input terminal voltage drops to the voltage of the first power supply terminal 400. .
Therefore, in that case, the voltage drop at the load R4 is expressed by the following Expression 9.

  VR4 = VBEQ2-VCEQ2 Equation 9

Here, VBEQ2 is the base-emitter voltage of transistor Q2, and VCEQ2 is the voltage drop between the collector and emitter of transistor Q2. Therefore, the minimum operating power supply voltage V ⁺ (min) 2 in the conventional circuit shown in FIG.

V ⁺ (min) 2 = VCEQ5 + VBEQ3 + VBEQ2-VCEQ2 ... Equation 10

Assuming that the subscript voltage of VCE (collector-emitter voltage) is about 0.2 V and the subscript voltage of VBE (base-emitter voltage) is about 0.7 V, it is shown in FIG. The minimum operating power supply voltage V ⁺ (min) 2 of the conventional circuit is 1.4 V, and the minimum operating power supply voltage V ⁺ (min) 3 of the conventional circuit shown in FIG. 11 is 1.6 V.
Therefore, when the conventional circuit shown in FIG. 11 is used, the minimum operating power supply voltage is raised by 0.2 V compared to the conventional circuit shown in FIG.

  The present invention has been made in view of the above circumstances, and provides an operational amplifier capable of suppressing output phase inversion without causing an increase in current consumption or an increase in the minimum operating power supply voltage.

In order to achieve the above object of the present invention, an operational amplifier according to the present invention comprises:
In an operational amplifier comprising: an input unit configured with a differential amplifier circuit; and a folded cascode unit configured to amplify and output the output of the input unit by a folded cascode circuit.
The differential amplifier circuit is provided by connecting first and second transistors so that differential amplification is possible, and the base of the first transistor is connected to an inverting input terminal via a first resistor, and the second transistor is connected to the second amplifier. The bases of the transistors are respectively connected to the non-inverting input terminal via a second resistor,
The first and second transistors each have a load connected to the output side, and the first input section is connected between the connection point between the second transistor and the corresponding load and the inverting input terminal. A diode is connected between the connection point of the first transistor and the corresponding load and the non-inverting input terminal, and a second input diode is connected between the inverting input terminal and the non-inverting input terminal. The voltage at the connection point of the first transistor with the load can be maintained larger than the voltage at the connection point of the second transistor with the load even if the input voltage between them exceeds the range of the power supply voltage. Are connected to each other,
The folded cascode circuit includes first and second folded cascode transistors connected in a folded cascode, and a bias circuit for supplying a bias to the bases of the first and second folded cascode transistors. Provided,
Wherein the bias circuit, between the high voltage power supply and low-voltage power supply, provided a diode-connected bias circuit transistor is, the mutual connection point of the bias circuit transistor and load, the said inverting input and non An inverting input terminal is connected to each of the first and second folded cascode diodes, and the first and second folded cascode diodes are used for the first and second input parts, respectively. The diode is connected so as to be in the same direction as the connection direction with respect to the inverting input terminal and the non-inverting input terminal.

  According to the present invention, unlike the prior art, there is an effect that output phase inversion can be reliably prevented without causing an increase in current consumption or an increase in the minimum operating power supply voltage.

It is a circuit diagram in the 1st example of composition of the operational amplifier of an embodiment of the invention. It is a circuit diagram in the 2nd example of composition of an operational amplifier of an embodiment of the invention. It is a circuit diagram in the 3rd example of composition of an operational amplifier of an embodiment of the invention. It is a circuit diagram in the 4th example of composition of an operational amplifier of an embodiment of the invention. FIG. 10 is a characteristic diagram showing a result of simulating changes in collector currents of fifth and sixth transistors with respect to changes in input voltage in the first configuration example shown in FIG. 1. It is a circuit diagram which shows the 1st structural example of a conventional circuit. FIG. 7 is a characteristic diagram showing a change in output voltage with respect to a change in input voltage in the conventional circuit shown in FIG. 6. It is a circuit diagram which shows the 2nd structural example of a conventional circuit. FIG. 9 is a characteristic diagram showing a change in output voltage with respect to a change in input voltage in the conventional circuit shown in FIG. 8. FIG. 9 is a characteristic diagram showing a simulation result of a change in collector current with respect to a change in input voltage in the conventional circuit shown in FIG. 8. It is a circuit diagram which shows the 3rd structural example of a conventional circuit.

Embodiments of the present invention will be described below with reference to FIGS. 1 to 5.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, a first configuration example of the operational amplifier according to the embodiment of the present invention will be described with reference to FIG.
This operational amplifier includes an input section 10 having a differential circuit mainly composed of first and second transistors (indicated as “Q1” and “Q2” in FIG. 1) 1 and 2, and a folded circuit, respectively. The main configuration is the same as that of the main conventional circuit in that it is roughly divided into the folded cascode section 20 in which the cascode amplifier circuit is configured.

The input unit 10 includes a differential circuit having PNP first and second transistors 1 and 2 as main components, and a differential amplification output is input to the folded cascode unit 20. .
Specifically, first, the emitters of the first and second transistors 1 and 2 are connected to each other and connected to a first constant current source (denoted as “CS1” in FIG. 1) 21. A constant current is allowed to flow. The first constant power supply 21 is connected to the second power supply terminal 300 so that a high voltage power supply voltage is applied.

  On the other hand, the base of the first transistor 1 is connected to the inverting input terminal 100 via the first resistor 31 (denoted as “R1” in FIG. 1), and the base of the second transistor 2 is the second resistor. 1 is connected to the non-inverting input terminal 200 via a resistor 32 (denoted as “R2” in FIG. 1).

In addition, the collector of the first transistor 1 is connected to the second load (in FIG. 1, “R3” in FIG. 1) and the collector of the second transistor 2 is “ Both are connected to the first power supply terminal 400 via the R34), and a low-voltage power supply voltage is applied.
Further, between the inverting input terminal 100 and the collector of the second transistor 2, a first input diode (shown as “D1” in FIG. 1) 11 is provided so that the cathode is on the inverting input terminal 100 side. It is connected.
Furthermore, a second input diode (denoted as “D2” in FIG. 1) 12 is provided between the non-inverting input terminal 200 and the collector of the transistor 1 so that the cathode is on the non-inverting input terminal 200 side. It is connected.

  Next, the folded cascode section 20 includes PNP-type third and fourth transistors (indicated as “Q3” and “Q4” in FIG. 1) 3, 4, and the first and second folded bits, respectively. NPN-type fifth and sixth transistors (represented as “Q5” and “Q6” in FIG. 1) 5 and 6, NPN-type ninth transistor 9, and third constants as cascode transistors, respectively. A folded cascode amplifier circuit is configured with a current source (indicated as “CS3” in FIG. 1) 23 as a main component.

Specifically, the bases of the third and fourth transistors 3 and 4 are connected to each other and connected to the collector of the third transistor 3, while each emitter is connected to the second power supply terminal 300. Thus, a current mirror circuit is configured.
The collector of the third transistor 3 is connected to the collector of the fifth transistor 5, while the collector of the fourth transistor 4 is connected to the output terminal 500 together with the collector of the sixth transistor 6.

The bases of the fifth and sixth transistors 5 and 6 are connected to each other and to the base and collector of the ninth transistor.
The emitter of the fifth transistor 5 is connected to the collector of the second transistor 2 and the emitter of the sixth transistor 6 is connected to the collector of the first transistor 1.
The collector of the ninth transistor 9 is connected to the third constant current source 23 so that a constant current is supplied. The third constant current source 23 is connected to the second power supply terminal 300 so that a high voltage power supply voltage is applied.

The emitter of the ninth transistor 9 is connected to the first power supply terminal 400 via a third load 35 (denoted as “R5” in FIG. 1) as a load.
The series circuit of the third constant current source 23, the ninth transistor 9, and the third load 35 described above functions as a bias circuit for the fifth and sixth transistors 5 and 6. Yes.
Further, the emitter of the ninth transistor 9 includes an anode of a fifth diode (denoted as “D5” in FIG. 1) 15 as a first folded cascode diode, and a second folded cascode. The anode of a sixth diode (denoted as “D6” in FIG. 1) 16 as a part diode is connected. The cathode of the fifth diode 15 is connected to the inverting input terminal 100, and the cathode of the sixth diode 16 is connected to the non-inverting input terminal 200.

With this configuration, output phase inversion is prevented, and when the voltage at the non-inverting input terminal 200 (non-inverting input terminal voltage) is reduced by about 0.7 V from the voltage at the first power supply terminal 400, the fifth and sixth The increase in the collector current of the transistors 5 and 6 is suppressed, and unlike the conventional circuit, the minimum operating power supply voltage is not raised.
Hereinafter, a specific circuit operation will be described focusing on the circuit operation particularly when the voltage at the non-inverting input terminal 200 (non-inverting input terminal voltage) is reduced by about 0.7 V from the voltage at the first power supply terminal 400. .

First, consider a case where the voltage of the first power supply terminal 400 is 0 V and the terminal voltage V200 of the non-inverting input terminal 200 is V200 <−0.7 (V).
Since the operation of the input unit 10 in this case is basically the same as that of the conventional circuit, a current ID4 first flows through the parasitic diode D4 between the collector and the base of the second transistor 2 in brief. At the same time, a current ID2 flows through the second input diode 12 connected to the non-inverting input terminal 200. When such a current flows, the voltage VB at the point B and the voltage VA at the point A are lowered.

  On the other hand, when the terminal voltage of the non-inverting input terminal 200 is not lower than the voltage of the first power supply terminal 400, the cathode potential of the sixth diode 16 is the same as that of the non-inverting input terminal 200. Decreases by about 0.7 V from the voltage of the first power supply terminal 400, a forward current flows from the anode to the cathode of the sixth diode 16. As the forward current flows through the third load 35, the potential at the point D decreases. The potential at the point D at this time is expressed by the following formula 11.

  VD = V200 + VD6 = V200 + VT * ln {ID6 / (nD6 * Is)} Equation 11

Here, VT is a thermal voltage, Is is a reverse saturation current, and nD6 is a magnification with respect to a unit element area. V200 is a terminal voltage of the non-inverting input terminal 200, VD6 is a forward voltage drop between the anode and cathode of the sixth diode 16, and ID6 is a forward current value thereof.
Since the potential at the point D decreases, the potential at the point C also decreases through the diode-connected ninth transistor 9. The potential Vc at this point C is expressed by the following Expression 12.

  Vc = VD + VT * ln {Ics3 / (nQ9 * Is)} = V200 + VT * ln {ID6 / (nD6 * Is)} + VT * ln {Ics3 / (nQ9 * Is)}

Here, Ics3 is the current value of the third constant current source 23, which is the current flowing through the ninth transistor 9. NQ9 is a magnification with respect to the unit element area of the ninth transistor 9.
Next, the potential at point B is calculated.
As described above, the potential at the point B decreases due to the occurrence of a backflow current from the collector to the base of the second transistor 2. Further, the potential at the point A decreases due to the forward current of the second input diode 12 flowing.
The potential VB at the point B and the potential VA at the point A are expressed by the following expressions 13 and 14.

  VB = V200 + VT * ln {ID4 / (nD4 * Is)} + ID4 * R2 Equation 13

  VA = V200 + VT * ln {ID2 / (nD2 * Is)} Expression 14

Here, ID4 is the reverse current value flowing from the collector to the base of the second transistor 2, ID2 is the forward current value flowing through the second input diode 12, and nD4 is between the collector and base of the second transistor 2. The magnification of the PN junction with respect to the unit element area, and nD2 is the magnification with respect to the unit element area of the second input diode 12.
From these equations, the base-emitter voltage of the fifth transistor 5 is obtained as follows.

  Vc-VB = VT * ln {ID6 / (nD6 * Is)} + VT * ln {Ics3 / (nQ9 * Is)}-VT * ln {ID4 / (nD4 * Is)}-ID4 * R2 = VT * ln { ID6 * Ics3 * nD4 / (nD6 * nQ9 * ID4 * Is)}-ID4 * R2 Expression 15

  Vc-VA = VT * ln {ID6 / (nD6 * Is)} + VT * ln {Ics3 / (nQ9 * Is)}-VT * ln {ID2 / (nD2 * Is)} ≈VT * ln {ID6 * Ics3 * nD2 / (nD6 × nQ9 × ID2 × Is)} Equation 16

  On the other hand, the non-inverting input terminal voltage V200 is such that the base-emitter voltages of the fifth and sixth transistors 5 and 6 near the midpoint of the first power supply terminal 400 and the second power supply terminal 300 are expressed by Equation 17 below. As shown.

  VBEQ5 = VT * ln {IQ5 / (nQ5 * Is)} = VT * ln {Ics3 / (nQ9 * Is)} Expression 17

  Therefore, when the conditions of the following expressions 18 and 19 are satisfied, even if the non-inverting input terminal voltage V200 is about 0.7 V lower than the voltage of the first power supply terminal 400, the fifth and sixth transistors 5, The collector current of 6 does not increase.

  Vc-VB <VBEQ5 ... Equation 18

  Vc-VA <VBEQ5 Equation 19

  Substituting Equations 15, 16, and 17 into Equations 18 and 19 to obtain more detailed conditions, the following is obtained.

  VT × ln {nD4 × ID6 / (nD6 × ID4)} <ID4 × R2

  VT × ln {nD2 × ID6 / (nD6 × ID2)} <0 Equation 21

By adjusting nD6, R2 and the like so as to satisfy Expressions 20 and 21, that is, by adjusting the size of the sixth diode 16 and the second resistor 32, the non-inverting input terminal voltage V200 is When the voltage becomes lower than the voltage of one power supply terminal 400 by about 0.7 V, the increase in collector currents of the fifth and sixth transistors 5 and 6 is suppressed.
FIG. 5 is a characteristic diagram showing simulation results of changes in the input / output voltages and changes in the collector currents of the fifth and sixth transistors in the operational amplifier having the circuit configuration shown in FIG.

In the figure, a solid characteristic line indicates a change in input voltage, and a two-dot chain characteristic line indicates a change in output voltage. The characteristic line of the alternate long and short dash line indicates the collector current.
Here, the change of the output voltage is the same as the change of the input voltage represented by the solid characteristic line except for the range where the input voltage exceeds 10V and the range where the input voltage is less than 0V. It overlaps with the characteristic line.
According to FIG. 5, even if the input voltage is about 0.7 V lower than the voltage of the first power supply terminal 400, the output phase is not inverted, and the collector currents of the fifth and sixth transistors 5 and 6 are reduced. It can be confirmed that the increase is suppressed.

Since the minimum operating power supply voltage is the same as the relational expression V ⁺ (min) 2 = VCEQ5 + VBEQ3 + VBEQ2−VCEQ2 previously shown in the description of the conventional circuit, the fifth and sixth transistors 5 and 6 The minimum operating power supply voltage is not raised by the additional circuit portion added to suppress the collector current of the current.
In the circuit configuration described above, the PNP transistor is replaced with an NPN transistor, the NPN transistor is replaced with a PNP transistor, and the forward direction of the first and second diodes 11 and 12 is reversed. The first and third constant current sources 21 and 23 are connected in reverse directions, and the second power supply terminal 300 on the high voltage power supply side and the first power supply terminal 400 on the low voltage power supply side are reversed. It is also good. In this case, when the input voltage to the inverting input terminal 100 and the non-inverting input terminal 200 exceeds the voltage of the second power supply terminal 300, the operation is the same as that of the configuration example described above.

Next, a second configuration example will be described with reference to FIG.
The same components as those of the first configuration example shown in FIG. 1 are denoted by the same reference numerals, detailed description thereof will be omitted, and different points will be mainly described below.
This second configuration example is the same as the first configuration example shown in FIG. 1 except that a sixth resistor (indicated as “R6” in FIG. 1) 36 is connected to the cathode side of the first input diode 11. In addition, a seventh resistor 37 (denoted as “R7” in FIG. 1) 37 is provided on the cathode side of the second input diode 12 to constitute the input section 10A.
That is, the cathode of the first input diode 11 is connected to the inverting input terminal 100 via the sixth resistor 36 as the first diode series resistor, and the cathode of the second input diode 12 is The non-inverting input terminal 200 is connected via a seventh resistor 37 as a second diode series resistor.

With this configuration, output phase inversion is prevented, and when the voltage at the non-inverting input terminal 200 (non-inverting input terminal voltage) is reduced by about 0.7 V from the voltage at the first power supply terminal 400, the fifth and sixth The increase in the collector current of the transistors 5 and 6 is suppressed, and unlike the conventional circuit, the minimum operating power supply voltage is not raised.
Hereinafter, a specific circuit operation will be described focusing on the circuit operation particularly when the voltage at the non-inverting input terminal 200 (non-inverting input terminal voltage) is reduced by about 0.7 V from the voltage at the first power supply terminal 400. . Since the operation in the input unit 10 is basically the same as that of the conventional circuit as described in the first configuration example, detailed description thereof is omitted here.

  First, in a state where the terminal voltage of the non-inverting input terminal 200 is not lower than the voltage of the first power supply terminal 400, the cathode potential of the sixth diode 16 is the same as that of the non-inverting input terminal 200. Decreases by about 0.7 V from the voltage of the first power supply terminal 400, a forward current flows from the anode to the cathode of the sixth diode 16. As the forward current flows through the third load 35, the potential at the point D decreases. The potential at point D at this time is expressed by Equation 11 as in the first configuration example.

Since the potential at the point D decreases, the potential at the point C also decreases through the diode-connected ninth transistor 9. The potential Vc at this point C is expressed by Expression 12 shown in the first configuration example.
Next, the potential at point B is calculated.
As described above, the potential at the point B decreases due to the occurrence of a backflow current from the collector to the base of the second transistor 2. Further, the potential at the point A decreases due to the forward current of the second input diode 12 flowing.
The potential VB at the point B is expressed by the equation 13 shown in the first configuration example, and the potential VA at the point A is expressed by the following equation 14A.

  VA = V200 + VT * ln {ID2 / (nD2 * Is)} + ID2 * R7 Expression 14A

Here, R 7 is the resistance value of the seventh resistor 37. In addition, the definition of each other item in the formula 14A is as described in the formula 14 above.
From these equations, the base-emitter voltage of the fifth transistor 5 is obtained as follows.
First, the difference Vc−VB between the potential at the point C and the potential at the point B is obtained by the equation 15 shown in the first configuration example.
On the other hand, the difference Vc−VA between the potential at the point C and the potential at the point A is obtained by the following equation 16A.

  Vc-VA = VT * ln {ID6 / (nD6 * Is)} + VT * ln {Ics3 / (nQ9 * Is)}-VT * ln {ID2 / (nD2 * Is)}-ID2 * R7 = VT * ln { ID6 * Ics3 * nD2 / (nD6 * nQ9 * ID2 * Is)}-ID2 * R7 ... Equation 16A

On the other hand, the non-inverting input terminal voltage V200 is the same as that of the first and second transistors 5 and 6 near the midpoint of the first power supply terminal 400 and the second power supply terminal 300. This is expressed by Expression 17 shown in the configuration example.
Therefore, when the conditions of Expressions 18 and 19 shown in the first configuration example are satisfied, even if the non-inverting input terminal voltage V200 is about 0.7 V lower than the voltage of the first power supply terminal 400, the fifth And the collector currents of the sixth transistors 5 and 6 do not increase.

  Here, by substituting Equation 15, Equation 16A, and Equation 17 into Equation 18 and Equation 19 to obtain more detailed conditions, Equation 20 is obtained as in the first configuration example, and is described below. Equation 21A is obtained.

  VT × ln {nD2 × ID6 / (nD6 × ID2)} <ID2 × R7 Equation 21A

Thus, by adjusting nD6, R2, etc. so as to satisfy the expressions 20 and 21A, that is, by adjusting the size of the sixth diode 16 and the second resistor 32, the non-inverting input terminal voltage V200. However, when the voltage is about 0.7 V lower than the voltage of the first power supply terminal 400, the increase in the collector current of the fifth and sixth transistors 5 and 6 is suppressed.
Note that the characteristic diagram based on the simulation of FIG. 5 previously shown in the first configuration example is similarly applied to the second configuration example, but detailed description thereof is omitted here.

Comparing the previous expression 21A in the second configuration example with the expression 21 shown in the first configuration example, the right side of the expression 21A is a value larger than 0, so that nD6 is larger than that in the first configuration example. Can be small. Therefore, the second configuration example has an advantage that the size of the sixth diode 16 of the folded cascode portion 20 can be suppressed as compared with the first configuration example.
As for the minimum operating power supply voltage, as described in the first configuration example, the minimum operation power supply voltage can be reduced by the additional circuit portion added to suppress the collector currents of the fifth and sixth transistors 5 and 6. The power supply voltage is not raised.

  In this second configuration example, the PNP transistor is replaced with an NPN transistor, the NPN transistor is replaced with a PNP transistor, and the first and second diodes 11 and 12 are in the forward direction. Are reversed, the first and third constant current sources 21 and 23 are reversed in direction, and the second power supply terminal 300 on the high voltage power supply side and the first power supply terminal 400 on the low voltage power supply side are reversed. It is good also as a structure. In this case, when the input voltage to the inverting input terminal 100 and the non-inverting input terminal 200 exceeds the voltage of the second power supply terminal 300, the operation is the same as that of the configuration example described above.

Next, a third configuration example will be described with reference to FIG.
The same components as those of the first configuration example shown in FIG. 1 are denoted by the same reference numerals, detailed description thereof will be omitted, and different points will be mainly described below.
This third configuration example is the same as the first configuration example shown in FIG. 1 except that PNP-type seventh and eighth transistors (indicated as “Q7” and “Q8” in FIG. 1) 7, The differential circuit comprised by 8 is provided, and the folded cascode part 20A is comprised.

Specifically, first, the PNP type seventh and eighth transistors 7 and 8 as the first and second additional differential circuit transistors are connected to each other, and the emitters are connected to each other. It is connected to a second constant current source (indicated as “CS2” in FIG. 1) 22 so that a constant current can flow in. The second constant power supply 22 is connected to the second power supply terminal 300 so that a high voltage power supply voltage is applied.
On the other hand, the collectors of the seventh and eighth transistors 7 and 8 are both connected to the first power supply terminal 400 via the third load 35.
The base of the seventh transistor 7 is connected to the inverting input terminal 100, and the base of the eighth transistor 8 is connected to the non-inverting input terminal 200.

With this configuration, output phase inversion is prevented, and when the voltage at the non-inverting input terminal 200 (non-inverting input terminal voltage) is reduced by about 0.7 V from the voltage at the first power supply terminal 400, the fifth and sixth The increase in the collector current of the transistors 5 and 6 is suppressed, and unlike the conventional circuit, the minimum operating power supply voltage is not raised.
Hereinafter, a specific circuit operation will be described focusing on the circuit operation particularly when the voltage at the non-inverting input terminal 200 (non-inverting input terminal voltage) is reduced by about 0.7 V from the voltage at the first power supply terminal 400. . Since the operation in the input unit 10 is basically the same as that of the conventional circuit as described in the first configuration example, detailed description thereof is omitted here.

First, the base potential of the eighth transistor 8 is the same as the terminal voltage of the non-inverting input terminal 200, and when the base potential is lowered by about 0.7 V from the voltage of the first power supply terminal 400, the eighth transistor 8. Reverse current flows from the collector to the base. When the reverse current flows through the third load 35, the potential at the point D decreases. The potential at point D at this time is expressed by Equation 11 as in the first configuration example.
In the third configuration example, VD6 in Expression 11 is a threshold voltage when a reverse current flows from the collector to the base of the eighth transistor 8, and ID6 is the reverse current value.
Since the potential at the point D decreases, the potential at the point C also decreases through the diode-connected ninth transistor 9. The potential Vc at this point C is expressed by Expression 12 shown in the first configuration example.

Next, the potential at point B is calculated.
As described above, the potential at the point B decreases due to the occurrence of a backflow current from the collector to the base of the second transistor 2. Further, the potential at the point A decreases due to the forward current of the second input diode 12 flowing.
Therefore, the potential VB at the point B is expressed by the equation 13 shown in the first configuration example, and the potential VA at the point A is expressed by the equation 14 shown in the first configuration example.

From these equations, the base-emitter voltage of the fifth transistor 5 is obtained as follows.
First, the difference Vc−VB between the potential at the point C and the potential at the point B is obtained by the equation 15 shown in the first configuration example.
Further, the difference Vc−VA between the potential at the point C and the potential at the point A is obtained by the equation 16 shown in the first configuration example.

On the other hand, the non-inverting input terminal voltage V200 is the same as that of the first and second transistors 5 and 6 near the midpoint of the first power supply terminal 400 and the second power supply terminal 300. This is expressed by Expression 17 shown in the configuration example.
Therefore, when the conditions of Expressions 18 and 19 shown in the first configuration example are satisfied, even if the non-inverting input terminal voltage V200 is about 0.7 V lower than the voltage of the first power supply terminal 400, the fifth And the collector currents of the sixth transistors 5 and 6 do not increase.

Here, when Expressions 15, 16, and 17 are substituted into Expressions 18 and 19, and more detailed conditions are obtained, Expressions 20 and 21 are obtained as in the first configuration example.
Thus, by adjusting nD6, R2, etc. so as to satisfy Expressions 20 and 21, that is, by adjusting the sizes of the eighth transistor 8 and the second resistor 32, the non-inverting input terminal voltage V200. However, when the voltage is about 0.7 V lower than the voltage of the first power supply terminal 400, the increase in the collector current of the fifth and sixth transistors 5 and 6 is suppressed.

Note that the characteristic diagram based on the simulation of FIG. 5 previously shown in the first configuration example is similarly applied to this third configuration example, but detailed description thereof is omitted here.
As for the minimum operating power supply voltage, as described in the first configuration example, the minimum operation power supply voltage can be reduced by the additional circuit portion added to suppress the collector currents of the fifth and sixth transistors 5 and 6. The power supply voltage is not raised.

  Also in this third configuration example, the PNP transistor is replaced with an NPN transistor, the NPN transistor is replaced with a PNP transistor, and the forward direction of the first and second diodes 11 and 12 is further increased. Are reversed, the first to third constant current sources 21 to 23 are reversed, and the second power supply terminal 300 on the high voltage power supply side and the first power supply terminal 400 on the low voltage power supply side are reversed. It is good also as a structure. In this case, when the input voltage to the inverting input terminal 100 and the non-inverting input terminal 200 exceeds the voltage of the second power supply terminal 300, the operation is the same as that of the configuration example described above.

Next, a fourth configuration example will be described with reference to FIG.
In addition, about the same component as the component of the 1st structural example shown by FIG. 1, FIG. 3, the same code | symbol is attached | subjected, the detailed description is abbreviate | omitted, and it focuses on a different point hereafter. explain.
In the fourth configuration example, the sixth and seventh resistors 36 and 37 are provided in the third configuration example shown in FIG. 3 as in the second configuration example shown in FIG. It is what has.

That is, the cathode of the first input diode 11 is connected to the inverting input terminal 100 via the sixth resistor 36, and the cathode of the second input diode 12 is connected via the seventh resistor 37. Each is connected to the non-inverting input terminal 200.
With this configuration, output phase inversion is prevented, and when the voltage at the non-inverting input terminal 200 (non-inverting input terminal voltage) is reduced by about 0.7 V from the voltage at the first power supply terminal 400, the fifth and sixth The increase in the collector current of the transistors 5 and 6 is suppressed, and unlike the conventional circuit, the minimum operating power supply voltage is not raised.

  Hereinafter, a specific circuit operation will be described focusing on the circuit operation particularly when the voltage at the non-inverting input terminal 200 (non-inverting input terminal voltage) is reduced by about 0.7 V from the voltage at the first power supply terminal 400. . Since the operation in the input unit 10 is basically the same as that of the conventional circuit as described in the first configuration example, detailed description thereof is omitted here.

  First, in a state where the terminal voltage of the non-inverting input terminal 200 is not lower than the voltage of the first power supply terminal 400, the cathode potential of the sixth diode 16 is the same as that of the non-inverting input terminal 200. Is about 0.7V lower than the voltage of the first power supply terminal 400, a reverse current flows from the anode to the cathode of the sixth diode 16. When the reverse current flows through the third load 35, the potential at the point D decreases. The potential at point D at this time is expressed by Equation 11 as in the first configuration example.

Since the potential at the point D decreases, the potential at the point C also decreases through the diode-connected ninth transistor 9. The potential Vc at this point C is expressed by Expression 12 shown in the first configuration example.
Next, the potential at point B is calculated.
As described above, the potential at the point B decreases due to the occurrence of a backflow current from the collector to the base of the second transistor 2. Further, the potential at the point A decreases due to the forward current of the second input diode 12 flowing.
The potential VB at the point B is expressed by the equation 13 shown in the first configuration example, and the potential VA at the point A is expressed by the following equation 14A shown in the second configuration example.

  VA = V200 + VT * ln {ID2 / (nD2 * Is)} + ID2 * R7 Expression 14A

Here, R 7 is the resistance value of the seventh resistor 37. In addition, the definition of each other item in the formula 14A is as described in the formula 14 above.
From these equations, the base-emitter voltage of the fifth transistor 5 is obtained as follows.
First, the difference Vc−VB between the potential at the point C and the potential at the point B is obtained by the equation 15 shown in the first configuration example.
On the other hand, the difference Vc−VA between the potential at the point C and the potential at the point A is obtained by the following equation 16A shown in the second configuration example.

  Vc-VA = VT * ln {ID6 / (nD6 * Is)} + VT * ln {Ics3 / (nQ9 * Is)}-VT * ln {ID2 / (nD2 * Is)}-ID2 * R7 = VT * ln { ID6 * Ics3 * nD2 / (nD6 * nQ9 * ID2 * Is)}-ID2 * R7 ... Equation 16A

On the other hand, the non-inverting input terminal voltage V200 is the same as that of the first and second transistors 5 and 6 near the midpoint of the first power supply terminal 400 and the second power supply terminal 300. This is expressed by Expression 17 shown in the configuration example.
Therefore, when the conditions of Expressions 18 and 19 shown in the first configuration example are satisfied, even if the non-inverting input terminal voltage V200 is about 0.7 V lower than the voltage of the first power supply terminal 400, the fifth And the collector currents of the sixth transistors 5 and 6 do not increase.

  Here, by substituting Equation 15, Equation 16A, and Equation 17 into Equations 18 and 19, and obtaining more detailed conditions, Equation 20 is obtained as in the first configuration example, and The following formula 21A shown in the second configuration example is obtained.

  VT × ln {nD2 × ID6 / (nD6 × ID2)} <ID2 × R7 Equation 21A

Thus, by adjusting nD6, R2, etc. so as to satisfy the expressions 20 and 21A, that is, by adjusting the size of the sixth diode 16 and the second resistor 32, the non-inverting input terminal voltage V200. However, when the voltage is about 0.7 V lower than the voltage of the first power supply terminal 400, the increase in the collector current of the fifth and sixth transistors 5 and 6 is suppressed.
The characteristic diagram based on the simulation of FIG. 5 previously shown in the first configuration example is similarly applied to this fourth configuration example, but detailed description thereof is omitted here.

Comparing the previous equation 21A in the fourth configuration example with the equation 21 shown in the first configuration example, the right side of the equation 21A is a value larger than 0, so that nD6 is larger than that in the first configuration example. Can be small. Therefore, the fourth configuration example has an advantage that the size of the sixth diode 16 of the folded cascode portion 20 can be suppressed as compared with the first configuration example.
As for the minimum operating power supply voltage, as described in the first configuration example, the minimum operation power supply voltage can be reduced by the additional circuit portion added to suppress the collector currents of the fifth and sixth transistors 5 and 6. The power supply voltage is not raised.

  In the fourth configuration example, the PNP transistor is replaced with an NPN transistor, the NPN transistor is replaced with a PNP transistor, and the first and second diodes 11 and 12 are in the forward direction. Are reversed, the first to third constant current sources 21 to 23 are reversed, and the second power supply terminal 300 on the high voltage power supply side and the first power supply terminal 400 on the constant pressure power supply side are reversed. It is good also as a structure. In this case, when the input voltage to the inverting input terminal 100 and the non-inverting input terminal 200 exceeds the voltage of the second power supply terminal 300, the operation is the same as that of the configuration example described above.

  The present invention can be applied to an operational amplifier in which an output phase inversion prevention operation is desired without causing an increase in current consumption or an increase in the minimum operating power supply voltage.

DESCRIPTION OF SYMBOLS 10, 10A ... Input part 20, 20A ... Folded cascode part 100 ... Inverted input terminal 200 ... Non-inverted input terminal 300 ... First power supply terminal 400 ... Second power supply terminal

Claims (3)

In an operational amplifier comprising: an input unit configured with a differential amplifier circuit; and a folded cascode unit configured to amplify and output the output of the input unit by a folded cascode circuit.
The differential amplifier circuit is provided by connecting first and second transistors so that differential amplification is possible, and the base of the first transistor is connected to an inverting input terminal via a first resistor, and the second transistor is connected to the second amplifier. The bases of the transistors are respectively connected to the non-inverting input terminal via a second resistor,
The first and second transistors each have a load connected to the output side, and the first input section is connected between the connection point between the second transistor and the corresponding load and the inverting input terminal. A diode is connected between the connection point of the first transistor and the corresponding load and the non-inverting input terminal, and a second input diode is connected between the inverting input terminal and the non-inverting input terminal. The voltage at the connection point of the first transistor with the load can be maintained larger than the voltage at the connection point of the second transistor with the load even if the input voltage between them exceeds the range of the power supply voltage. Are connected to each other,
The folded cascode circuit includes first and second folded cascode transistors connected in a folded cascode, and a bias circuit for supplying a bias to the bases of the first and second folded cascode transistors. Provided,
Wherein the bias circuit, between the high voltage power supply and low-voltage power supply, provided a diode-connected bias circuit transistor is, the mutual connection point of the bias circuit transistor and load, the said inverting input and non An inverting input terminal is connected to each of the first and second folded cascode diodes, and the first and second folded cascode diodes are used for the first and second input parts, respectively. An operational amplifier, wherein the diode is connected so as to have the same connection direction as that of the inverting input terminal and the non-inverting input terminal of the diode.   A first diode series resistor is provided between the inverting input terminal and the first input diode, and a second diode series resistor is provided between the non-inverting input terminal and the second input diode. 2. The operational amplifier according to claim 1, wherein diode series resistors are connected to each other.   Instead of the first and second folded cascode diodes, first and second additional differential circuit transistors connected so as to be differentially amplifiable are provided, and the first and second additional differences are provided. Both the collectors of the dynamic circuit transistors are connected to a connection point between the bias circuit transistor of the bias circuit and the load, and each emitter is configured to be able to supply a constant current, while the first circuit 2. The base of the additional differential circuit transistor is connected to the inverting input terminal, and the base of the second additional differential circuit transistor is connected to the non-inverting input terminal, respectively. Or the operational amplifier of 2.

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