JP5022318B2 - Operational amplifier - Google Patents

Description

  The present invention relates to an operational amplifier that takes measures against output phase inversion that occurs when an input voltage exceeds a power supply voltage.

  In an operational amplifier that does not take inversion prevention measures, when the input voltage is lower than the low-potential-side power supply voltage, for example, when the low-potential-side power supply voltage is 0 V and the input voltage is reduced to about −8 V, FIG. As shown, the output voltage changes, causing an output phase inversion phenomenon. Therefore, conventionally, even if the input voltage is lower than the low-potential side power supply voltage, the output voltage is not phase-inverted, and the output phase inversion prevention measure is obtained so that the characteristics shown in FIG. 6 can be obtained. Has been given.

  FIG. 7 is a circuit diagram showing a configuration of a conventional operational amplifier in which this output phase inversion prevention measure is taken (see, for example, FIG. 1 of Patent Document 1). This operational amplifier is composed of an input circuit 10A and an output circuit 20A. The input circuit 10A includes PNP transistors Q1 and Q2 and a current source I1 constituting a differential circuit, load resistors R2A and R2B of the differential circuit, and diodes D1A and D1B for preventing output phase inversion. The output circuit 20A includes PNP transistors Q3 and Q4 constituting a current mirror circuit, NPN transistors Q5 and Q6 connected to the load resistors R2A and R2B of the input circuit 10A, and a current for applying a base bias to the transistors Q5 and Q6. A series circuit comprising a source I4, a diode D3 and a resistor R3. 11 is an inverting input terminal, 12 is a non-inverting input terminal, and 21 is an output terminal. D2A and D2B are parasitic diodes formed between the collectors and bases of the transistors Q1 and Q2.

With respect to this operational amplifier, the output phase inversion prevention operation will be described using the operation when the voltage at the non-inverting input terminal 12 is lower than the low-potential side power supply voltage VEE. When the voltage VEE = 0V and the input voltage _{VIN +} of the non-inverting input terminal 12 becomes _{VIN +} <− 0.7 [V], the current _ID2B flows through the parasitic diode D2B of the transistor Q2. At the same time, a current _ID1B flows through the diode D1B connected to the non-inverting input terminal 12. As described above, when the currents I _{D2B and} I _D1B flow, the voltages V _N1 and V _{N2 of the} nodes N1 and _N2 are lowered.

となる。このとき、出力位相反転を生じさせないためには、Ｖ_Ｎ１＞Ｖ_Ｎ２が常に維持される必要がある。 _Assuming that the voltage between the anode and cathode of the diode D1B is V _AKD1B and the voltage between the anode and cathode of the parasitic diode D2B is V _AKD2B , the current flowing from the power supply VEE through the node N2 through the diode D1B is I _N2 , and the node N1 from the power supply VEE is the node N1 the current flowing through the parasitic diode D2B via the _{I N1,} is the reverse saturation current of the transistors Q1, Q2, thermal voltage _{V T,} when the ratio to a unit device area of n1, n2,

It becomes. At this time, in order not to cause the output phase inversion, it is necessary to always maintain V _N1 > V _N2 .

となる。 Assuming that the currents I _N1 and I _N2 are approximately the same, and that the potential difference for the thermal voltage is necessary to keep the voltage at the output terminal 21 low with a margin, the equations (1) and (2) ,

It becomes.

  Equation (3) indicates that the diode D1B needs to have an area 2.7 times that of the parasitic diode D2B in order to obtain a sufficient output phase inversion prevention effect. This indicates that a large area is required for the elements of the diodes D1A and D1B in order to prevent output phase inversion. Usually, the operational amplifier increases the element area of the transistors Q1 and Q2 due to the offset voltage characteristics, so that the diodes D1A and D1B also require a large area, which is difficult to realize when the element area is limited.

となる。 On the other hand, when the input voltages of the inverting input terminal 11 and the non-inverting input terminal 12 become 0.7 V or less than the low potential side power supply voltage VEE, the voltages V _N1 and V _{N2 of the} nodes N1 and N2 are lower than the voltage VEE. Become. The base-emitter voltage _{V BEQ5} of the transistor Q5 of the output circuit 20A, the base-emitter voltage _{V BEQ6} of the transistor Q6 is about 0.7 [V], respectively, the voltage _{V N3} of the base of the node N3 of the transistors Q5, Q6 Is

It becomes.

Ｉ_４＝１０μＡ、β_Ｎ＝２００とすると、式(5)、(6)より、

となる。この式(7)は、出力位相反転防止動作中に大きな回路電流が流れることを示す。 When V _N3 <0.7 [V], the current I ₄ of the current source I ₄ that has flowed through the diode D 3 and maintained the base voltage of the node N 3 does not flow into the diode D 3, and all of the bases of the transistors Q 5 and Q 6 Flow into. At this time, when the current _{I 4} is uniformly flows to the base of transistor Q5, Q6, the collector current _{I C6} of the collector current _{I C5} of the transistor Q6 of the transistor Q5, the current amplification factor of the NPN transistor when the beta _N,

Assuming that I ₄ = 10 μA and β _N = 200, from equations (5) and (6),

It becomes. This equation (7) indicates that a large circuit current flows during the output phase inversion prevention operation.

FIG. 8 shows a simulation circuit diagram in which the collector currents I _CQ5 and I _CQ6 of the transistors Q5 and Q6 are confirmed when the input voltage _{VIN +} of the non-inverting input terminal 12 changes. Here, the output terminal 21 is connected to the inverting input terminal 11 via a resistor of 5 kΩ, the resistors R2A = R2B = 2 kΩ, R3 = 1 kΩ, the current I ₁ of the current source I1 = 50 μA, and the current I _{4 of the} current source I4. The input voltage E1 was applied to the non-inverting input terminal 12 via a 5 kΩ resistor, and a voltage of 5 V was applied between the high potential side power supply terminal VCC and the low potential side power supply terminal VEE. FIG. 9 shows the simulation result. It is shown that the collector currents I _CQ5 and I _{CQ6 of} the transistors Q5 and Q6 greatly increase as the input voltage _{VIN +} of the non-inverting input terminal 12 decreases.
JP 2001-308656 A

  In the conventional operational amplifier, a large element area is required for the diodes D1A and D1B in order to prevent output phase inversion. Further, when the output phase inversion prevention circuit is operating, as shown in FIG. 9, since a large current flows through the output circuit 20A, the consumption current of the operational amplifier increases and the circuit operation becomes unstable. Further, since circuit wiring corresponding to a large current is required, the wiring area is increased.

  An object of the present invention is to reliably prevent output phase inversion without increasing the area in the input circuit, and in the output circuit, current does not increase during the output phase inversion prevention operation, and current consumption increases. It is an object of the present invention to provide an operational amplifier that can realize a stable circuit operation, does not require consideration for internal wiring, and does not increase the circuit area.

To achieve the above object, an operational amplifier according to a first aspect of the present invention connects the emitters of first and second transistors of the first conductivity type to a first power supply terminal via a first current source. The differential circuit, the first and second loads connected between the collectors of the first and second transistors and the second power supply terminal, respectively, the base of the first transistor and the first load A first resistor connected between the input terminal and a second resistor connected between a base of the second transistor and a second input terminal; a collector of the first transistor; and the first resistor. A first diode connected between a first common connection point with one load and the second input terminal so that the second input terminal side is a cathode; and a collector of the second transistor And the second common with the second load Characterized in that it comprises a second diode connected to the cathode of the first input terminal side between the and the attachment point first input terminal.
According to a second aspect of the present invention, in the operational amplifier according to the first aspect, a first current mirror circuit, a collector is connected to an input side of the first current mirror circuit, and an emitter is connected to the second common connection point. A third transistor of the second conductivity type connected to the first current mirror circuit, and a second transistor of the second conductivity type having a collector connected to the output side of the first current mirror circuit and an emitter connected to the first common connection point. And a second current source connected between the bases of the third and fourth transistors and the first power supply terminal, and the collector of the fourth transistor is an output terminal. It is characterized by being connected to.
According to a third aspect of the present invention, in the operational amplifier according to the second aspect, the second current source includes a third current source having one end connected to the first power supply terminal, and the third current. A current mirror circuit composed of fifth and sixth transistors of the first conductivity type commonly connected to the other end of the source; a base connected to the input side of the current mirror circuit; and a collector connected to the third mirror And a seventh transistor having an emitter connected to the second power supply terminal and an output side of the current mirror circuit connected to bases of the third and fourth transistors. To do.

  According to the present invention, output phase inversion can be reliably prevented without increasing the area of the input circuit. Also, in the output circuit, the current does not increase during the output phase inversion prevention operation, the current consumption of the operational amplifier does not increase, stable circuit operation can be realized, and there is no need to consider internal wiring. The area does not increase.

  FIG. 1 is a circuit diagram showing a configuration of an operational amplifier according to one embodiment of the present invention. This operational amplifier is composed of an input circuit 10 and an output circuit 20. The input circuit 10 includes PNP transistors Q1 and Q2 and a current source I1 constituting a differential circuit, load resistors R2A and R2B of the differential circuit, diodes D1A and D1B for preventing output phase inversion, and resistors R1A and R1B. . The output circuit 20 includes PNP transistors Q3 and Q4 constituting a current mirror circuit, NPN transistors Q5 and Q6 connected to the load resistors R2A and R2B of the input circuit 10, and a current for applying a base bias to the transistors Q5 and Q6. Source I2 is provided. 11 is an inverting input terminal, 12 is a non-inverting input terminal, and 21 is an output terminal. D2A and D2B are parasitic diodes formed between the collectors and bases of the transistors Q1 and Q2. In the conventional operational amplifier described with reference to FIG. 7, the resistors R1A and R1B are connected to the bases of the transistors Q1 and Q2 in the input circuit 10, respectively, and the base bias of the transistors Q5 and Q6 is used as the current source I2 The only thing that went on is different.

  In relation to the claims, the transistor Q1 corresponds to a first transistor, the transistor Q2 corresponds to a second transistor, the transistor Q5 corresponds to a third transistor, and the transistor Q6 corresponds to a fourth transistor.

The operation of the output phase inversion will be described using the operation when the input voltage of the non-inverting input terminal 12 is lower than the low-potential side power supply voltage VEE for this operational amplifier. When the voltage VEE = 0V and the input voltage _{VIN + of} the non-inverting input terminal voltage 12 becomes _{VIN +} <− 0.7 [V], the current _ID2B flows through the parasitic diode D2B of the transistor Q2. At the same time, a current _ID1B flows through the diode D1B connected to the non-inverting input terminal 12. In the conventional example, the diode D2B requires an area 2.7 times that of the parasitic diode D2B of the transistor Q2. However, in the present invention, output phase inversion prevention can be realized with a smaller diode area.

と近似できる。 The output phase inversion preventing operation will be described assuming that the element area of the diode D1B is 1/10 of the element area of the parasitic diode D2B of the transistor Q2. Assuming that the anode-cathode voltage V _AKD2B of the parasitic diode D2B of the transistor Q2 is 0.7 [V], the anode-cathode voltage V _AKD1B of the diode D1B is

Can be approximated.

となる。ノードＮ１、Ｎ２の電圧Ｖ_Ｎ１，Ｖ_Ｎ２は、式(8)、(9)より

となる。 Load resistor R2A, the resistance value of R2B and _{R 2,} resistors R1A, when the resistance value of R1B was _{R 1,} VEE → resistor R2B → node N1 → parasitic diode D2B → resistor R1B → current flowing through the non-inverting input terminal 12 I _N1 , VEE → resistor R2A → node N2 → diode D1B → current flowing through the non-inverting input terminal 12 is I _N2 .

It becomes. The voltages V _N1 and V _N2 of the nodes N1 and N2 are obtained from the equations (8) and (9).

It becomes.

となる。Ｒ_２＝１０ｋΩ、Ｖ_ＩＮ＋＝−５[Ｖ]とすると、出力位相反転を防止するために必要な抵抗Ｒ１Ｂの抵抗値Ｒ_１は、式（12）より、

となる。以上により、トランジスタＱ２の寄生ダイオードＤ２Ｂに対し、１／１０の面積のダイオードＤ１Ｂおよび小さな値の抵抗Ｒ１Ｂによって、確実に出力位相反転を防止することができる。 In order to prevent output phase inversion, the voltage V _N1 > V _N2 needs to be maintained at all times. For the voltage of the output terminal 12 is kept low enough with a margin, when a potential difference of the thermal voltage V _T min is assumed to be necessary, the formula (10) and (11),

It becomes. When R ₂ = 10 kΩ and V _{IN +} = −5 [V], the resistance value R ₁ of the resistor R _{1 B} necessary to prevent the output phase inversion is calculated from the equation (12):

It becomes. As described above, the output phase inversion can be reliably prevented by the diode D1B having the area of 1/10 and the resistor R1B having a small value with respect to the parasitic diode D2B of the transistor Q2.

  Next, the operation of the present invention in the output circuit 20 will be described. In the conventional operational amplifier, the base potentials of the transistors Q5 and Q6 are determined by a bias circuit including a diode D3 and a resistor R3. On the other hand, in this embodiment, the bases of the transistors Q5 and Q6 are commonly connected to the current source I2.

また、ベース電流Ｉ_ＢＱ５とＩ_ＢＱ６は電流源Ｉ２の電流Ｉ_２より、

である。ノードＮ３の電圧Ｖ_Ｎ３は、ノードＮ１，Ｎ２の電圧Ｖ_Ｎ１，Ｖ_Ｎ２と、式（14），（１５）より、

となる。 The base-emitter voltage _{V BEQ6} transistor Q5 Nobesu-emitter voltage _{V BEQ5} and transistor Q6, the base current _{I BQ6} base current _{I BQ5} the transistor Q6 of the transistor Q5,

The base currents I _BQ5 and I _BQ6 are _derived from the current I ₂ of the current source I2,

It is. The voltage V _N3 of the node _N3 is obtained from the voltages V _N1 and V _N2 of the nodes N1 and N2, and the equations (14) and (15),

It becomes.

When the voltages V _N1 and V _{N2 of the} nodes N1 and N2 become −0.7 [V] or lower than the low potential side power supply voltage VEE, the voltage V _{N3 of the} node _N3 also decreases according to the equation (17). At this time, the sum of the base currents I _BQ5 and I _BQ6 is constant depending on the current I ₂ of the current source I2, and thus is constant regardless of V _N3 .

となる。式（18）のように、本実施例の演算増幅器では、出力位相反転防止動作中にも大きな回路電流が流れることがないため、予期せぬ大電流による回路誤動作の心配がなく、大きな電流に対応する回路配線が不要となる。 Current _{I 2} of the current source I2, and was uniformly flow into the base of the transistor Q5 and the transistor _Q6, I 2 = 100 nA, when the beta _N = 200, the collector current _I of the collector current _{I CQ5} the transistor Q6 of the transistor Q5 _Cq6 Is

It becomes. As shown in equation (18), in the operational amplifier of this embodiment, since a large circuit current does not flow even during the output phase inversion prevention operation, there is no fear of a circuit malfunction due to an unexpected large current, and a large current is generated. Corresponding circuit wiring becomes unnecessary.

A current _I 2 = 100 nA current source I2 in Figure 2, shows the transistors Q5, Q6 simulation circuit diagram confirming collector current _{I CQ5, I Cq6} of when the non-inverting input voltage of the input terminal 12 _{V IN +} is changed. Here, the output terminal 21 is connected to the inverting input terminal 11 via a resistor of 5 kΩ, the resistors R1A = R1B = 200Ω, R2A = R2B = 2 kΩ, the current I ₁ of the current source I1 = 50 μA, and the non-inverting input terminal An input voltage E1 was applied to 12 via a 5 kΩ resistor, and a voltage of 5 V was applied between the high potential side power supply terminal VCC and the low potential side power supply terminal VEE. FIG. 3 shows the simulation result. It is _shown that the total current value of the collector currents I _CQ5 and I _CQ6 of the transistors Q5 and Q6 does not depend on the voltage _{VIN +} of the non-inverting input terminal 12 and is constant.

  FIG. 4 is a circuit diagram of an operational amplifier that embodies the current source I2 of the output circuit 20. The current source I2 includes a current source I3, PNP transistors Q7 and Q8 constituting a current mirror circuit, and an NPN transistor Q9. In relation to the claims, the transistor Q7 corresponds to a fifth transistor, the transistor Q8 corresponds to a sixth transistor, and the transistor Q9 corresponds to a seventh transistor.

となる。 The current _{I 3} of the current source I3, when the collector current _{I CQ9} flows through the transistor Q9, the base current _{I BQ9} of transistor Q9,

It becomes.

となる。 The base current _IBQ9 of the transistor Q9 flows into the bases of the transistors Q5 and Q6 by the current mirror circuit composed of the transistors Q7 and Q8. When the transistors Q7 and Q8 have the same size and the voltages V _N1 and V _{N2 of the} nodes N1 and N2 are V _N1 = V _N2 , the collector currents I _CQ5 and I _CQ6 of the transistors Q5 and Q6 are _expressed by the equation ( 19)

It becomes.

  By using the current source I2 having such a configuration, a large circuit current does not flow even during the output phase inversion prevention operation, and the collector currents of the transistors Q5 and Q6 can be easily set as shown in Equation (20). can do.

  In the operational amplifier of this embodiment described above, the PNP transistor is replaced with an NPN transistor, the NPN transistor is replaced with a PNP transistor, the directions of the diodes D2A and D2B are reversed, and the directions of the current sources I1 to I3 are reversed. The high potential side power supply terminal VCC and the low potential side power supply terminal VEE may be reversed. At this time, the same operation is performed when the input voltages of the inverting input terminal 11 and the non-inverting input terminal 12 exceed the high potential power supply voltage VCC.

It is a circuit diagram which shows the structure of the operational amplifier of the Example of this invention. FIG. 2 is a circuit diagram for simulation of the operational amplifier of FIG. 1. FIG. 3 is a characteristic diagram of collector currents of transistors Q5 and Q6 obtained by the simulation circuit of FIG. FIG. 2 is a circuit diagram showing a configuration of an operational amplifier that embodies a current source I2 portion of the operational amplifier of FIG. 1; It is an input / output waveform diagram of an operational amplifier that does not take measures to prevent output phase inversion. FIG. 6 is an input / output waveform diagram of an operational amplifier in which measures for preventing output phase inversion are taken. It is a circuit diagram which shows the structure of the conventional operational amplifier which took the countermeasure against output phase inversion. FIG. 8 is a circuit diagram for simulation of the operational amplifier of FIG. 7. FIG. 9 is a characteristic diagram of collector currents of transistors Q5 and Q6 obtained by the simulation circuit of FIG.

Explanation of symbols

10, 10A: input circuit, 11: inverting input terminal, 12: non-inverting input terminal 20, 20A: output circuit, 21: output terminal

Claims (3)

A differential circuit in which emitters of first and second transistors of a first conductivity type are connected to a first power supply terminal via a first current source;
First and second loads connected between the collectors of the first and second transistors and a second power supply terminal, respectively;
A first resistor connected between the base of the first transistor and a first input terminal and a second resistor connected between the base of the second transistor and a second input terminal; ,
The first input connected between the first common connection point of the collector of the first transistor and the first load and the second input terminal so that the second input terminal side is a cathode. A diode,
The second input terminal is connected between the second common connection point of the collector of the second transistor and the second load and the first input terminal so that the first input terminal side is a cathode. A diode,
An operational amplifier comprising: The operational amplifier according to claim 1,
A first current mirror circuit;
A third transistor of the second conductivity type having a collector connected to the input side of the first current mirror circuit and an emitter connected to the second common connection point;
A second transistor of the second conductivity type having a collector connected to the output side of the first current mirror circuit and an emitter connected to the first common connection point;
A second current source connected between the bases of the third and fourth transistors and the first power supply terminal;
An operational amplifier, wherein the collector of the fourth transistor is connected to an output terminal. 3. The operational amplifier according to claim 2, wherein the second current source is
A third current source having one end connected to the first power supply terminal;
A current mirror circuit comprising fifth and sixth transistors of the first conductivity type, the emitter of which is commonly connected to the other end of the third current source;
A seventh transistor having a base connected to the input side of the current mirror circuit, a collector connected to the third current source, and an emitter connected to the second power supply terminal;
An operational amplifier characterized in that an output side of the current mirror circuit is connected to bases of the third and fourth transistors.

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