JP5759833B2 - 半導体装置及びその作製方法 - Google Patents
半導体装置及びその作製方法 Download PDFInfo
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- JP5759833B2 JP5759833B2 JP2011183612A JP2011183612A JP5759833B2 JP 5759833 B2 JP5759833 B2 JP 5759833B2 JP 2011183612 A JP2011183612 A JP 2011183612A JP 2011183612 A JP2011183612 A JP 2011183612A JP 5759833 B2 JP5759833 B2 JP 5759833B2
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- layer
- insulating layer
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- conductive
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Images
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/702—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
- H01L21/707—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thin-film circuits or parts thereof
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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Description
本実施の形態では、本発明の一態様である半導体装置について図面を参照して説明する。
本実施の形態では、実施の形態1で説明した半導体装置の作製方法について説明する。
上記実施の形態にて作製した薄膜トランジスタを適用した半導体装置としては、電子ペーパーが挙げられる。電子ペーパーは、情報を表示するものであればあらゆる分野の電子機器に用いることが可能である。例えば、電子ペーパーを用いて、電子書籍(電子ブック)、ポスター、デジタルサイネージ、PID(Public Information Display)、電車などの乗り物の車内広告、クレジットカード等の各種カードにおける表示等に適用することができる。電子機器の一例を図7に示す。
上記実施の形態にて作製した薄膜トランジスタを適用した半導体装置としては、電子ペーパー以外にもさまざまな電子機器(遊技機も含む)が挙げられる。電子機器としては、例えば、テレビジョン装置(テレビ、またはテレビジョン受信機ともいう)、コンピュータ用などのモニタ、デジタルカメラ、デジタルビデオカメラ、デジタルフォトフレーム、携帯電話機(携帯電話、携帯電話装置ともいう)、携帯型ゲーム機、携帯情報端末、音響再生装置、パチンコ機などの大型ゲーム機などが挙げられる。
102 第1の導電層
104 第1の絶縁層
106 第1の半導体層
108 第2の半導体層
110 不純物半導体層
112 第2の導電層
114 第2の絶縁層
116 第3の絶縁層
116A 第3の絶縁層
116B 第3の絶縁層
118 第3の導電層
118A 第3の導電層
118B 第3の導電層
120 第1の開口部
122 第2の開口部
200 基板
202 第1の導電層
204 第1の絶縁層
206 第1の半導体膜
208 第2の半導体膜
210 不純物半導体膜
211 エッチングマスク
212 薄膜積層体
214 導電膜
216 絶縁膜
217 エッチングマスク
218 第2の絶縁層
220 第2の導電層
222 第1の半導体層
224 第2の半導体層
226 不純物半導体層
228 第3の絶縁層
229 開口部
229P 開口部
230 第3の導電層
231 開口部
231P 開口部
240 エッチングマスク
300 電子書籍
301 筐体
303 筐体
305 表示部
306 光電変換装置
307 表示部
308 光電変換装置
311 軸部
321 電源
323 操作キー
325 スピーカ
400 テレビジョン装置
401 筐体
403 表示部
405 スタンド
407 表示部
409 操作キー
410 リモコン操作機
420 デジタルフォトフレーム
421 筐体
423 表示部
441 上部筐体
442 下部筐体
443 表示部
444 キーボード
445 外部接続ポート
446 ポインティングデバイス
447 表示部
Claims (6)
- 第1の導電層を覆って設けられた第1の絶縁層と、
前記第1の絶縁層上に設けられた第1の半導体層と、
前記第1の半導体層上に、前記第1の半導体層を露出させて離間して設けられた第2の半導体層と、
前記第2の半導体層上に設けられた不純物半導体層と、
前記不純物半導体層上に、少なくとも一部が接するように設けられた第2の導電層と、
前記第2の導電層上に設けられた第2の絶縁層と、
前記第1の半導体層、前記第2の半導体層、前記不純物半導体層、前記第2の導電層、及び前記第2の絶縁層を覆って設けられた第3の絶縁層と、
少なくとも、前記第3の絶縁層上に設けられた第3の導電層と、を有し、
前記第1の絶縁層及び前記第3の絶縁層には、前記第1の導電層の一部に達する第1の開口部が設けられており、
前記第2の絶縁層及び前記第3の絶縁層には、前記第2の導電層の一部に達する第2の開口部が設けられており、
前記第1の絶縁層の厚さと前記第2の絶縁層の厚さは等しいことを特徴とする半導体装置。 - 第1の導電層を覆って設けられた第1の絶縁層と、
前記第1の絶縁層上に設けられた第1の半導体層と、
前記第1の半導体層上に、前記第1の半導体層を露出させて離間して設けられた第2の半導体層と、
前記第2の半導体層上に設けられた不純物半導体層と、
前記不純物半導体層上に、少なくとも一部が接するように設けられた第2の導電層と、
前記第2の導電層上に設けられた第2の絶縁層と、
前記第1の半導体層、前記第2の半導体層、前記不純物半導体層、前記第2の導電層、及び前記第2の絶縁層を覆って設けられた第3の絶縁層と、
少なくとも、前記第3の絶縁層上に設けられた第3の導電層と、を有し、
前記第1の絶縁層及び前記第3の絶縁層には、前記第1の導電層の一部に達する第1の開口部が設けられており、
前記第2の絶縁層及び前記第3の絶縁層には、前記第2の導電層の一部に達する第2の開口部が設けられており、
前記第1の開口部の深さと前記第2の開口部の深さは等しいことを特徴とする半導体装置。 - 請求項1または請求項2において、
前記第3の絶縁層は、前記第1の絶縁層及び前記第2の絶縁層よりも薄いことを特徴とする半導体装置。 - 第1の導電層を覆って設けられた第1の絶縁層上に、第1の半導体層、第2の半導体層及び不純物半導体層がこの順に積層された薄膜積層体を形成し、
前記薄膜積層体を覆って、第2の導電層となる導電膜及び第2の絶縁層となる絶縁膜を形成し、
前記第2の絶縁層となる絶縁膜をエッチングすることで前記第2の絶縁層を形成し、
前記第2の導電層となる導電膜をエッチングすることで前記第2の導電層を形成し、
前記第2の導電層と重畳していない部分の前記不純物半導体層及び前記第2の半導体層を除去することで、前記第2の導電層と重畳していない部分の前記第1の半導体層を露出させて半導体素子を形成し、
前記半導体素子を覆って第3の絶縁層を形成し、
前記第1の絶縁層及び前記第3の絶縁層には、前記第1の導電層の一部に達する第1の開口部を形成し、
前記第2の絶縁層及び前記第3の絶縁層には、前記第2の導電層の一部に達する第2の開口部を形成し、
前記第1の絶縁層の厚さと前記第2の絶縁層の厚さは等しいことを特徴とする半導体装置の作製方法。 - 第1の導電層を覆って設けられた第1の絶縁層上に、第1の半導体層、第2の半導体層及び不純物半導体層がこの順に積層された薄膜積層体を形成し、
前記薄膜積層体を覆って、第2の導電層となる導電膜及び第2の絶縁層となる絶縁膜を形成し、
前記第2の絶縁層となる絶縁膜をエッチングすることで前記第2の絶縁層を形成し、
前記第2の導電層となる導電膜をエッチングすることで前記第2の導電層を形成し、
前記第2の導電層と重畳していない部分の前記不純物半導体層及び前記第2の半導体層を除去することで、前記第2の導電層と重畳していない部分の前記第1の半導体層を露出させて半導体素子を形成し、
前記半導体素子を覆って第3の絶縁層を形成し、
前記第1の絶縁層及び前記第3の絶縁層には、前記第1の導電層の一部に達する第1の開口部を形成し、
前記第2の絶縁層及び前記第3の絶縁層には、前記第2の導電層の一部に達する第2の開口部を形成し、
前記第1の開口部の深さと前記第2の開口部の深さは等しいことを特徴とする半導体装置の作製方法。 - 請求項4または請求項5において、
前記第2の絶縁層と前記第2の導電層は、同一のエッチング工程で形成されることを特徴とする半導体装置の作製方法。
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