JP5733517B2 - Demodulation method and apparatus - Google Patents

Description

  The present invention relates to a demodulation method and apparatus for demodulating an input signal digitally modulated by symbol data.

  2. Description of the Related Art Conventionally, a method for performing data communication by a digital modulation method such as a frequency shift keying (FSK) method is known. Further, in signal transmission by the FSK method, it is also known that a deviation, that is, a frequency offset, is generated in the frequency of a frequency detection signal in a receiving apparatus due to, for example, a deviation in oscillation frequency of a local oscillator of a transmitter or a receiver. Yes. In the receiving apparatus, the frequency of the frequency detection signal is compared with a predetermined threshold value and the data value is determined based on the comparison result. Therefore, when the frequency offset occurs, the data value cannot be accurately determined. Therefore, in general, the receiving apparatus includes a frequency offset removing unit such as automatic frequency control (AFC) for removing a frequency offset. For example, Patent Document 1 discloses a configuration in which a frequency offset is removed by detecting a zero-cross point of an input signal using a zero-cross pulse obtained by removing a DC offset of the input signal using a filter.

JP-A-11-298541

  However, in the case of the configuration disclosed in Patent Document 1, since a certain time is required until the DC offset is eliminated, there is a problem in that the frequency offset removal process is delayed.

  In addition, as another conventional technique, the data value of the frequency detection signal is obtained by using, as a data value determination threshold, an amplitude average value obtained by smoothing the frequency detection signal with a low-pass filter including a FIR filter (Finite Impulse Response Filter). A method for making a determination is also known. However, this method has the following problems. That is, since an average value is calculated in order to obtain the determination threshold value, a period of at least two symbols in the waveform representing the frequency detection signal is required until the calculation. Further, when the average value calculation period is increased in order to obtain a highly accurate determination threshold, the calculation period can be increased only in units of two symbols. Therefore, there is a problem that it takes a long time to calculate the determination threshold. In addition, for example, when the determination threshold value is calculated using a so-called preamble portion of the received signal, if the data length of the preamble portion is short, a highly accurate determination threshold value cannot be obtained, resulting in erroneous determination of the data value. There was a problem.

  The present invention has been made in view of the above problems, and an object thereof is to provide a signal demodulation method and apparatus capable of accurately demodulating a digital modulation signal.

The demodulation method according to the present invention is a demodulation method for demodulating an input signal digitally modulated by symbol data, a detection step of detecting the input signal to generate a detection signal, and the detection signal as one of the symbol data. a delay step of generating a delay signal by delaying by symbols, a timing detection step the difference between the analog signal level of the analog signal level and the delay signal of said detection signal to detect the timing of zero as a zero cross timing, the An analog signal level of the detection signal at the zero cross timing is acquired for a plurality of the zero cross timings, an averaging step of sequentially averaging the acquired analog signal levels of the detection signal and outputting an average value, and the zero cross timing at the zero cross timing Analog of detection signal Obtaining the determination threshold based on the average value of the No. levels demodulation and decision threshold holding step of holding this, the current symbol value indicating the detection signal based on the comparison of the analog signal level and the determination threshold value of the detection signal A determination output step of outputting as an output.

The demodulator according to the present invention is a demodulator that demodulates an input signal digitally modulated by symbol data, a detection circuit that detects the input signal and generates a detection signal, and the detection signal is converted into the symbol data. A delay circuit that generates a delayed signal by delaying by one symbol, and a timing detection circuit that detects a timing at which a difference between the analog signal level of the detected signal and the analog signal level of the delayed signal becomes zero as a zero cross timing, An averaging circuit that obtains an analog signal level of the detection signal at the zero-cross timing for a plurality of the zero-cross timings, sequentially averages the obtained analog signal levels of the detection signal, and outputs an average value; and the zero-cross timing Analog signal level of the detection signal at A determination threshold value holding circuit for holding this by obtaining a mean value of the determination threshold based on the output current symbol value indicating the detection signal based on the comparison of the analog signal level and the determination threshold value of the detection signal as a demodulated output And a determination output circuit.

  The demodulation method and apparatus according to the present invention can accurately demodulate a digital modulation signal.

It is a block diagram which shows the structure of the demodulation apparatus which is an Example of this invention. It is a figure which shows the frame format of the signal input into a demodulation apparatus. It is a flowchart which shows a determination threshold value setting process routine. It is a time chart which shows the signal which appears in the determination threshold value setting process.

  Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 shows the configuration of a demodulator 10 that is an embodiment of the present invention. The demodulator 10 can be included in, for example, a radio signal receiving terminal (not shown). The demodulator 10 may have a hardware configuration, but may be equivalently configured by software executed by a microprocessor, for example.

  The frequency detector 1 detects the frequency of the input signal F1 and outputs a frequency detection signal F2 having a signal level corresponding to the frequency. The input signal F1 is a wireless or wired signal that is modulated by a digital modulation method such as the FSK method.

  The delay circuit 2 delays the frequency detection signal F2 by one symbol and outputs a delay signal F3. When the frequency detection signal F2 is, for example, a sine wave, the delay for one symbol corresponds to the delay for a half cycle of the sine wave. One symbol data can be said to be a portion corresponding to the half cycle of a waveform that intersects a predetermined level every half cycle, such as a sine wave. The delay circuit 2 can be configured with, for example, an N-stage shift register. Here, N is the number of samplings per symbol and is a positive integer. When the sampling frequency is Fs and the symbol frequency is Fsym, the relationship is N = Fs / Fsym.

  The subtractor 3 obtains a difference between the analog signal level of the frequency detection signal F2 and the analog signal level of the delay signal F3, and outputs a subtraction signal F4 indicating the difference. The subtraction signal F4 indicates, for example, a value obtained by subtracting the analog signal level of the delay signal F3 from the analog signal level of the frequency detection signal F2.

  The positive / negative display signal generation circuit 4 determines the positive / negative sign of the analog signal level of the subtraction signal F4, and outputs a positive / negative display signal F5 that displays the determination result. The positive / negative display signal F5 is, for example, a rectangular wave that displays that the determined sign is negative by a signal level “0” and that the determined sign is positive by a signal level “1”.

  The change time detection circuit 5 detects the change time of the sign of the positive / negative display signal F5 and generates a change time display signal F6 including a pulse indicating the change time. Hereinafter, the detection time point is also referred to as zero cross timing. The change point of the positive / negative sign is detected, for example, by detecting the rising / falling edge of the waveform of the positive / negative display signal F5.

  By the operation of the configuration comprising the subtractor 3, the positive / negative display signal generation circuit 4 and the change point detection circuit 5 (hereinafter referred to as timing detection circuit), the analog signal level of the frequency detection signal F2 and the analog signal level of the delay signal F3 are Timing at which the difference becomes zero (hereinafter referred to as zero cross timing) is detected. In other words, the timing detection circuit detects the timing at which the analog signal level of the frequency detection signal F2 matches the analog signal level of the delay signal F3. In other words, the timing detection circuit detects the timing at which the waveform of the frequency detection signal F2 and the waveform of the delay signal F3 intersect. The timing detection circuit directly detects the zero cross timing by detecting the voltage value of the signal level of the frequency detection signal F2 and the voltage value of the signal level of the delay signal F3 and obtaining the difference between the voltage values. It may be configured to do so.

  The averaging circuit 6 sequentially acquires the analog signal level of the frequency detection signal F2 at the pulse generation time of the detection pulse signal F6, and calculates the average value of the acquired values. The averaging circuit 6 outputs an average value signal F7 indicating the average value. Note that the averaging circuit 6 outputs the one value as it is when only one value is acquired.

  The preamble detection circuit 7 supplies a preamble detection signal F8 indicating that a so-called preamble included in the input signal F1 has been detected to the determination threshold holding circuit 8. Limble can be detected by a known method. For example, the detection may be performed inside the demodulation device 10 or may be detected after the demodulation device 10.

  The determination threshold value holding circuit 8 holds the analog signal level of the average value signal F7 as a slice level, that is, a determination threshold value, when the preamble detection signal F8 is supplied, and outputs a slice level signal F9 indicating the determination threshold value.

  The determination output circuit 9 outputs a current symbol value F10 based on a comparison between the current value of the analog signal level of the frequency detection signal F2 and the determination threshold indicated by the slice level signal F9 output from the determination threshold holding circuit 8. For example, when the current value of the analog signal level of the frequency detection signal F2 is larger than the determination threshold indicated by the slice level signal F9, the determination output circuit 9 outputs “1” as the current symbol value F10, and the frequency detection signal F2 When the current value of the analog signal level is smaller than the determination threshold indicated by the slice level signal F9, “0” is output as the current symbol value F10.

  FIG. 2 shows the frame format of the input signal F1. A preamble is provided in front of the data. The preamble is composed of logical value alternating pattern data such as “1010...” In which the logical value “1” and the logical value “0” appear alternately, that is, repetitive pattern data.

  With reference to FIGS. 3 and 4, the operation of the determination threshold value setting process in the demodulator 10 will be described.

  First, the frequency detector 1 frequency-detects the input signal F1, and outputs a value corresponding to the frequency as the frequency detection signal F2 (step S1). Since the preamble in the frame format of the input signal F1 is composed of logical value alternating pattern data such as “1010...”, For example, the frequency detection signal F2 is, for example, a sine wave as shown in FIG.

  Next, the delay circuit 2 delays the frequency detection signal F2 by one symbol and outputs a delay signal F3 (step S2).

  As shown in FIG. 4, the frequency detection signal F2 which is a sine wave, for example, is delayed by a half cycle of the sine wave.

  Next, the subtracter 3 subtracts the analog signal level of the delay signal F3 from the analog signal level of the frequency detection signal F2, and outputs a subtraction signal F4 (step S3). Hereinafter, points Q1 to Q7 at which the subtraction signal F4 crosses the “0” level are referred to as zero cross points Q1 to Q7.

  Next, the positive / negative display signal generation circuit 4 determines the positive / negative sign of the analog signal level of the subtraction signal F4, and outputs a positive / negative display signal F5 that displays the determination result (step S4).

  As shown in FIG. 4, for example, the positive / negative display signal F5 is a rectangular wave. If the determined sign is negative, the signal level of the positive / negative display signal F5 is “0”, and the determined sign is positive. If so, the signal level of the positive / negative display signal F5 is “1”.

  Next, the change point detection circuit 5 detects the change point of the positive / negative sign of the positive / negative display signal F5, and generates a change point display signal F6 including a pulse indicating the detection point (step S5). As shown in FIG. 4, the change point display signal F6 includes a pulse indicating each of the positive and negative change points T1 to T7 indicated by the positive / negative display signal F5. In addition, each of T1-T7 shown by FIG. 4 is a zero cross timing, and the said pulse shows a zero cross timing.

  Next, the averaging circuit 6 sequentially acquires analog signal levels (hereinafter referred to as midpoint estimated values) P1 to P7 of the frequency detection signal F2 at each time point T1 to T7 of pulse generation of the detection pulse signal F6. Then, the averaging circuit 6 calculates the average value of the acquired midpoint estimated values each time the midpoint estimated value is acquired (step S6). For example, when the averaging circuit 6 acquires up to the midpoint estimated value P2, the average value of the midpoint estimated values P1 and P2 is calculated at time T2. Further, for example, when the midpoint estimated value P7 is acquired, the average value of the midpoint estimated values P1 to P7 is calculated at the time T7. The averaging circuit 6 outputs an average value signal F7 indicating the average value. If only the midpoint estimated value P1 is acquired, the averaging circuit 6 outputs the midpoint estimated value P1 as the average value signal F7 at time T1. As shown in FIG. 4, since the midpoint estimated values P1 to P7 are the same value, the average value signal F7 indicates a constant average value from the initial stage of the average value calculation.

  Next, the preamble detection circuit 7 supplies the preamble detection signal F8 to the determination threshold value holding circuit 8 when detecting the preamble included in the input signal F1 (step S7). The determination threshold value holding circuit 8 holds the value indicated by the average value signal F7 as a determination threshold value when the preamble detection signal F8 is supplied, and outputs a slice level signal F9 indicating the determination threshold value (step S8). That is, the determination threshold holding circuit 8 holds the average value signal F7 at the time when the preamble is detected as a determination threshold, and outputs a slice level signal F9 indicating the determination threshold. The preamble detection time can be any of times T1, T2,..., T7 depending on the preamble detection method. That is, for example, the preamble detection circuit 7 may determine that the preamble has been detected at time T1, or may determine that the preamble has been detected at time T7.

  As a result of this processing, at least a part of a preamble composed of logical value alternating pattern data such as “1010...” Is used for setting a determination threshold, and irregular pattern data following the preamble is not used. . Accordingly, an appropriate determination threshold value can be set, and subsequent data values indicated by the frequency detection signal can be appropriately determined.

  The determination output circuit 9 outputs, for example, “1” as the current symbol value F10 when the current value indicated by the frequency detection signal F2 is larger than the value indicated by the slice level signal F9, and is indicated by the frequency detection signal F2. When the current value is smaller than the value indicated by the slice level signal F9, for example, “0” is output as the current symbol value F10. By using the slice level signal F9, the frequency offset can be canceled and the correct data value determination can be performed.

  As described above, in the demodulator 10 of this embodiment, when determining the determination threshold, first, the frequency detection signal F2 is delayed by one symbol to generate the delayed signal F3. Then, the subtraction signal F4 is generated by subtracting the delay signal F3 from the frequency detection signal F2. Zero cross points Q1 to Q7 of the subtraction signal F4 for the preamble portion composed of the logical value alternating pattern data are generated for each symbol. Therefore, the midpoint estimated values P1 to P7 of the frequency detection signal F2 are sequentially acquired for each symbol. Therefore, an appropriate determination threshold can be set with at least one symbol. Further, when obtaining the determination threshold value from the average value of the midpoint estimated values, the number of acquired midpoint estimated values can be increased in units of one symbol. Therefore, according to the demodulator 10 of the present embodiment, even if the preamble of the input signal F1 is short, an appropriate data value determination threshold for canceling the frequency offset, that is, a determination threshold is calculated, and the frequency detection signal F2 is calculated. The data value represented by can be accurately determined. Also, the data value can be accurately determined in a short time after receiving the input signal F1.

  In this embodiment, the data used for setting the determination threshold is “preamble”, but it is not necessarily the data called “preamble”. That is, for example, logical value alternating pattern data composed of “1010...” Can be used for setting the determination threshold.

  In the present embodiment, the frequency detection signal F2 is a sine wave. However, the present invention is not limited to this, and the present invention is applied to a case where the size of one symbol is a constant waveform. Similar effects can be achieved. For example, a waveform such as a rectangular wave or a triangular wave having a constant half cycle is conceivable. In the present embodiment, the frequency detection signal F2 is delayed by one symbol, but the same effect can be obtained by delaying by an odd number of symbols such as three symbols.

  In this embodiment, processing of a frequency detection signal in frequency shift keying (FSK) has been described. However, an AM detection signal in amplitude shift keying (ASK) and phase shift keying (PSK) are described. For the phase detection signal in (Phase-Shift Keying), when the preamble of the original symbol data as the modulation signal is composed of the above-described logic value alternating pattern data, the same effect can be obtained by applying the present invention. Can do.

DESCRIPTION OF SYMBOLS 1 Frequency detector 2 Delay circuit 3 Subtractor 4 Positive / negative display signal generation circuit 5 Change point detection circuit 6 Averaging circuit 7 Preamble detection circuit 8 Judgment threshold holding circuit 9 Judgment output circuit 10 Demodulator

Claims (10)

A demodulation method for demodulating an input signal digitally modulated by symbol data,
A detection step of detecting the input signal to generate a detection signal;
A delay step of delaying the detection signal by one symbol of the symbol data to generate a delayed signal;
A timing detection step of detecting a timing at which a difference between the analog signal level of the detection signal and the analog signal level of the delay signal becomes zero as a zero cross timing;
An averaging step of acquiring the analog signal level of the detection signal at the zero-cross timing for a plurality of the zero-cross timings, sequentially averaging the acquired analog signal levels of the detection signal, and outputting an average value;
A determination threshold value holding step for obtaining a determination threshold value based on an average value of the analog signal level of the detection signal at the zero cross timing and holding the determination threshold value;
And a step of outputting a current symbol value indicated by the detection signal as a demodulation output based on a comparison between the analog signal level of the detection signal and the determination threshold value. A preamble detection step of detecting preamble data included in the input signal;
2. The demodulation method according to claim 1, wherein the determination threshold value holding step holds the determination threshold value when the preamble data is detected in the preamble detection step . The timing detection step includes
A subtraction step of calculating a difference between the analog signal level of the detection signal and the analog signal level of the delay signal and generating a subtraction signal indicating the difference;
A positive / negative display signal generating step for generating a positive / negative display signal for displaying the positive / negative of the difference indicated by the subtraction signal;
The demodulation method according to claim 1 , further comprising: a change time detection step of detecting a positive / negative change time of the positive / negative display signal and setting the change time as the zero cross timing . The demodulation method according to claim 2 or 3 , wherein the preamble data includes logical value alternating pattern data . 5. The input signal according to claim 1, wherein the input signal is a signal subjected to digital modulation processing of any one of frequency shift keying, amplitude shift keying, and phase shift keying. demodulation method according to one. A demodulator that demodulates an input signal digitally modulated by symbol data,
A detection circuit that detects the input signal and generates a detection signal;
A delay circuit that delays the detection signal by one symbol of the symbol data to generate a delay signal;
A timing detection circuit for detecting a timing at which a difference between the analog signal level of the detection signal and the analog signal level of the delay signal becomes zero as a zero cross timing;
An averaging circuit that acquires the analog signal level of the detection signal at the zero-cross timing for a plurality of the zero-cross timings, sequentially averages the acquired analog signal levels of the detection signal, and outputs an average value;
A determination threshold value holding circuit for obtaining a determination threshold value based on an average value of the analog signal level of the detection signal at the zero-cross timing and holding the determination threshold value;
An output circuit that outputs a current symbol value indicated by the detection signal as a demodulated output based on a comparison between an analog signal level of the detection signal and the determination threshold value; A preamble detection circuit for detecting preamble data included in the input signal;
7. The demodulator according to claim 6, wherein the determination threshold value holding circuit holds the determination threshold value when the preamble data is detected by the preamble detection circuit . The timing detection circuit includes:
A subtractor that calculates a difference between a value indicated by the detection signal and a value indicated by the delay signal and generates a subtraction signal indicating the difference;
A positive / negative display signal generation circuit for generating a positive / negative display signal for displaying the positive / negative of the difference indicated by the subtraction signal;
The demodulator according to claim 6 , further comprising: a change point detection circuit that detects a positive / negative change point of the positive / negative display signal and sets the change point as the zero cross timing. The demodulator according to claim 7 or 8, wherein the preamble data comprises logical value alternate pattern data . 10. The input signal according to claim 6, wherein the input signal is a signal that has been subjected to digital modulation processing of any one of frequency shift keying, amplitude shift keying, and phase shift keying. The demodulation apparatus as described in one .

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