JP5213580B2 - Carrier offset detection circuit and detection method, and information communication device - Google Patents

Description

  The present invention relates to a demodulation technique for demodulating an FSK (Frequency Shift Keying) modulated reception signal, and more particularly to a carrier offset detection technique for detecting a carrier frequency offset between a reception side and a transmission side.

  In recent years, wireless communication systems of various standards and systems have been proposed in order to transmit and receive data between a plurality of electronic devices. For example, in a Bluetooth communication system, a carrier wave is FSK modulated using digital modulation data having a binary value of 1 or 0. In such a wireless communication system, if a carrier frequency shift (carrier offset) occurs between the transmitter side and the receiver side, accurate demodulation becomes difficult. Therefore, a circuit for detecting the carrier offset is provided on the receiver side.

Japanese Patent Laid-Open No. 10-98500

  The present invention has been made in such a situation, and an object thereof is to provide a technique capable of detecting an accurate carrier offset in a short time.

  One embodiment of the present invention relates to a carrier offset detection circuit that is provided in a demodulation circuit that demodulates a reception signal that is FSK (Frequency Shift Keying) modulated and detects an offset between carrier frequencies on the reception side and the transmission side. The carrier offset detection circuit includes a zero-cross detection unit and an offset detection unit. The zero-cross detection unit receives a digital baseband signal representing the level of frequency shift of the received signal with reference to the carrier frequency on the receiving side, and generates a base delayed by one symbol from the baseband signal generated during the preamble period The zero cross point with the band signal is detected. The offset detection unit sets the value of the baseband signal at the detected zero-cross timing to the offset value of the carrier frequency.

  In a wireless communication system having a preamble in which 1 and 0 are alternately included, the zero crossing occurs at an intermediate timing between the transitions of 1 and 0, that is, a timing at which the frequency shift becomes 0. Therefore, according to the above aspect, the carrier offset can be detected in a short preamble period by acquiring the value of the baseband signal at the zero cross timing at which the frequency shift becomes zero.

  Another aspect of the present invention also relates to a carrier offset detection circuit that is provided in a demodulation circuit that demodulates an FSK (Frequency Shift Keying) modulated reception signal and detects an offset between carrier frequencies on the reception side and the transmission side. The carrier offset detection circuit includes a preamble detection unit and an offset detection unit. The preamble detection unit receives a digital baseband signal representing the level of frequency shift of the received signal with reference to the carrier frequency on the receiving side, and detects the preamble from the baseband signal. The offset detection unit smoothes the baseband signal, and sets the value of the smoothed baseband signal during the preamble period as an offset value.

  In a wireless communication system having a preamble in which 1 and 0 are alternately included, the average frequency shift during the preamble period should be 0 in the absence of a carrier offset. Conversely, if there is an average frequency shift during the preamble period, the value is the carrier offset. Therefore, according to the above aspect, the carrier offset can be detected in a short preamble period.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

  According to the carrier offset detection circuit of the present invention, the carrier offset can be detected in a short time.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In this specification, “the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are in an electrically connected state. Including the case of being indirectly connected through other members that do not affect the above. Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical connection. The case where it is indirectly connected through another member that does not affect the state is also included.

  FIG. 1 is a block diagram showing a configuration of receiver 1000 of the wireless communication system according to the embodiment. A transmitter (not shown) and a receiver 1000 in a wireless communication system transmit and receive a carrier wave modulated by FSK (Frequency Shift Keying). Hereinafter, the wireless communication system performs communication based on the Bluetooth standard. However, the present invention is not limited to this and can be applied to other standards. The receiver 1000 is mounted on various information communication devices such as mobile phone terminals, personal computers, digital cameras, and home appliances.

  The transmitter transmits a high-frequency signal (RF signal) Srf obtained by FSK modulation using a digital signal whose carrier wave is 1/0 as a modulation signal. The receiver 1000 receives the RF signal Srf transmitted from the transmitter and demodulates the digital signal from the RF signal. The receiver 1000 includes an antenna 2, a frequency conversion circuit 4, an FM detection circuit 6, and a carrier offset detection circuit (hereinafter referred to as an offset detection circuit) 8.

  The antenna 2 receives a reception RF signal (modulated wave) having a carrier frequency of 2.4 GHz subjected to FSK modulation. In practice, the carrier frequency changes from time to time due to frequency hopping. The frequency conversion circuit 4, the FM detection circuit 6, and the offset detection circuit 8 constitute a demodulation circuit and demodulate the RF signal Srf. The RF signal Srf is input to the frequency conversion circuit 4. The frequency conversion circuit 4 frequency-converts (down-converts) the 2.4 GHz RF signal and decomposes it into the in-phase component BB_I and the quadrature component BB_Q. The FM detection circuit 6 generates a digital baseband signal iq_avrg representing the level of frequency shift of the RF signal Srf based on the in-phase component BB_I and the quadrature component BB_Q. The symbol rate of Bluetooth is 1 MHz, and the baseband signal iq_avrg generated by the FM detection circuit 6 is sampled at 8 MHz. In this embodiment, the baseband signal iq_avrg has 9 bits. Further, the level of the frequency shift indicated by the baseband signal iq_avrg is quantized in units of 1.95 kHz.

  In a wireless communication system, the carrier frequency on the transmitter side and the carrier frequency used when the receiver 1000 demodulates do not completely match. Therefore, the offset detection circuit 8 detects a carrier frequency offset (carrier offset) between the reception side and the transmission side, and outputs an offset signal OFS_O indicating the carrier offset amount. The receiver 1000 reflects the offset amount detected by the offset detection circuit 8 in the demodulation process.

  The offset detection circuit 8 includes a delay buffer 100, a preamble detection unit 200, and an offset detection unit 300. The baseband signal iq_avrg and the access code detection signal ACCDET are input to the offset detection circuit 8. The access code detection signal ACCDET is a signal indicating an access code included in 72 bits from the head of the packet, is generated by a circuit (not shown), and is input together with the baseband signal iq_avrg. The access code detection signal ACCDET becomes low level during the first 72 bits of the baseband signal iq_avrg and then becomes high level.

  As described above, the baseband signal iq_avrg is a signal sampled at 8 MHz, which is eight times the symbol rate of 1 MHz. The delay buffer 100 includes a delay signal delay4 obtained by delaying the baseband signal iq_avrg by 4 sampling times, that is, 1/2 symbol, a delay signal delay8 delayed by 8 sampling times, that is, 1 symbol, and 12 sampling times. That is, a delay signal delay12 delayed by 3/2 symbols is generated. The delay buffer 100 can be composed of a shift register including a plurality of cascaded latch circuits (delay circuits). Alternatively, other configurations are possible.

  In digital wireless communication, a preamble including a predetermined bit pattern is arranged in the first few bits of packet data. In the Bluetooth system, the first 4 bits of a packet are a preamble and include 1010 or 0101 pattern data. The preamble detection unit 200 is a circuit that detects a preamble.

  Since the preamble is arranged at the head of the packet data, it is demodulated without carrier offset correction. Therefore, it is difficult to detect the preamble from the demodulated data. Therefore, the preamble detection unit 200 according to the present embodiment compares the reference baseband signal iq_avrg with a signal that is relatively shifted by one symbol relative to it, that is, the delay signal delay8, and compares the intersection of the two signals. (Zero cross point) is detected. When the pattern 1010 or 0101 exists, the zero cross point is detected according to a predetermined rule. The preamble detector 200 outputs a zero-cross signal zc_en that becomes a predetermined level (high level) at the timing of zero-cross. Details of the preamble detector 200 will be described later.

  The offset detection unit 300 latches the baseband signal iq_avrg at the timing of the zero cross signal zc_en. In an ideal state where the carrier offset between the transmitting side and the receiving side is 0, the frequency transition corresponding to the pattern data 1010 should be 0 at the intermediate timing when the data transitions between 1 and 0, that is, at the zero cross point. is there. In other words, in the state where the carrier offset exists, the value of the frequency shift at the timing of the zero crossing point where the data transitions between 1 and 0, that is, the value of the baseband signal iq_avrg indicates the carrier offset amount. Become. Therefore, the offset detection unit 300 outputs the value of the baseband signal iq_avrg latched at the zero cross timing as the offset value OFS_O of the carrier frequency.

  Further, from another viewpoint, the offset detection unit 300 performs the following processing. In an ideal state where there is no carrier offset, the time average value of the frequency shift (baseband signal iq_avrg) during the preamble period in which 1010 or 0101 is repeated should be zero. In other words, in the state where the carrier offset exists, the average value of the frequency shift indicates the carrier offset amount. Therefore, the offset detection unit 300 smoothes the baseband signal iq_avrg, and outputs the smoothed value as a carrier offset value OFS_O.

  The above is the overall configuration of the receiver 1000. Hereinafter, details of the configuration of the preamble detection unit 200 and the offset detection unit 300 will be described in order.

  2 and 3 are block diagrams showing the configuration of the preamble detector 200. As shown in FIG. The preamble detection unit 200 includes an initial zero cross detection unit 210, a ringing removal unit 220, a pattern detection unit 240, and an offset difference limiter unit 250. 2 shows in detail the configurations of the initial zero-cross detection unit 210 and the ringing removal unit 220, and FIG. 3 shows the configurations of the pattern detection unit 240 and the offset difference limiter unit 250 in detail. FIGS. 5A and 5B and FIGS. 6A and 6B are operation waveform diagrams of the preamble detection unit 200. FIG.

  The initial zero cross detection unit 210 detects a timing at which the difference between the baseband signal iq_avrg and the delay signal delay8 becomes zero as a zero cross. The initial zero-cross detection unit 210 generates a zero-cross signal zc_org3 that goes to a high level at the zero-cross timing. FIG. 5A is an operation waveform diagram of the initial zero cross detection unit 210.

  2 includes an adder 212, a latch circuit 214, and an XOR gate 216. The adder 212 subtracts the delay signal delay8 from the baseband signal iq_avrg. The latch circuit 214 uses the enable signal EN8M to latch the sign bit (most significant bit) S1 [9] of the 10-bit differential signal S1 [9: 0] output from the adder 212. The enable signal EN8M is an 8 MHz clock that matches the sampling frequency of the baseband signal iq_avrg. The clock CLK24M is a 24 MHz clock. The XOR gate 216 generates an exclusive OR (XOR) of the difference signal S1 from the adder 212 and the sign bit S1 [9] of the difference signal S1 latched by the latch circuit 214. The output of the XOR gate 216 becomes the zero cross signal zc_org3.

  The zero-cross signal zc_org3 detected by the initial zero-cross detection unit 210 includes an unnecessary zero-cross that occurs regardless of the 1010 (or 0101) preamble. The ringing removing unit 220 removes a pseudo zero cross caused by the ringing of the waveform among unnecessary zero crosses. FIG. 5B is an operation waveform diagram of the ringing removal unit 220.

  The zero crossing of the preamble period occurs during an amplitude change of 1010 (or 0101). Therefore, the difference between the value of the baseband signal iq_avrg at a certain timing near the zero cross and the value of the baseband signal iq_avrg at a timing slightly before (or slightly behind) should be large to some extent. On the contrary, in the pseudo zero cross erroneously detected by the ringing of the waveform, the difference in the value of the baseband signal iq_avrg tends to be small at a certain timing near the zero cross and the timing before that. Therefore, when the difference between the value of the baseband signal iq_avrg near a certain zero crossing point and the value of the baseband signal iq_avrg at a predetermined time before that is smaller than a predetermined threshold, Remove the zero cross point. By this processing, a pseudo zero cross point can be removed. The signal from which the pseudo zero cross point is removed is referred to as a zero cross signal zc_org2.

  The ringing removal unit 220 determines the value of the baseband signal iq_avrg (delayed signal delay4) ½ symbol (4 sampling times) before the zero cross and the baseband signal iq_avrg (12 sampling times) before the zero cross. When the difference from the value of the delay signal delay12) is smaller than the threshold value sub_thd, the zero cross point is removed.

  2 includes an adder 222, an absolute value circuit 224, a comparator 226, an AND gate 228, a 3-bit counter 230, a comparator 232, and an AND gate 234. The adder 222 subtracts the delay signal delay4 from the delay signal delay12. The absolute value circuit 224 generates an absolute value S3 as a subtraction result. The comparator 226 compares the absolute value S3 with the threshold value sub_thd. The output S4 of the comparator 226 becomes a mask signal.

  The AND gate 228 takes the logical product of the initial zero cross detection signal zc_org3 and the mask signal S4, and masks the initial zero cross detection signal zc_org3 using the mask signal S4. The output zc_org2 of the AND gate 228 has a zero cross caused by waveform ringing removed. In order to remove the residual unnecessary zero cross that cannot be removed by the mask signal S4, the ringing removal unit 220 further performs the following processing.

  Zero crossing in the preamble period occurs at a symbol rate, that is, a period of 1 MHz. Therefore, the AND gate 228 removes the back zero cross when the time interval between adjacent zero crosses is equal to or less than the predetermined threshold value. In the circuit of FIG. 2, when the time interval of the zero cross is 0.5 μs (1/2 symbol = 4 sampling time) or less, the zero cross is removed.

  The 3-bit counter 230 starts counting based on the enable signal EN8M every time the zero-cross signal zc_org2 becomes high level, that is, every zero-cross timing. The comparator 232 compares the count value zc_org2_cnt by the 3-bit counter 230 with a predetermined threshold value. In FIG. 2, the threshold value is 3 (3b011). The AND gate 234 removes the pseudo zero cross from the zero cross signal zc_org2 using the output S5 of the comparator 232 as a mask signal. The output of the AND gate 234 is output to the subsequent pattern detection unit 240 as a zero cross signal zc_org.

  Turning to FIG. A 0101/1010 pattern detection unit (hereinafter referred to as a pattern detection unit) 240 detects a preamble pattern 0101 (or 1010) with reference to the zero-cross signal zc_org. A zero cross occurs when data transition of 01 or 10 occurs in data other than the preamble. Therefore, the pattern detection unit 240 is provided to extract 1010 (or 0101) in the preamble.

  Focusing on the pattern 0101 (or 1010), a zero cross occurs for each symbol. In other words, a zero cross that does not occur continuously for every symbol can be determined as a zero cross that has occurred in another data period, not in the preamble.

  The pattern detection unit 240 in FIG. 3 masks and removes each pulse of the zero-cross signal zc_org that does not have a zero-cross pulse approximately one symbol before it. When the pattern detection unit 240 in FIG. 3 pays attention to a certain pulse, a range of ± 2 samples before and after 1 symbol before (8 samples before) (that is, a range from 10 samples to 6 samples before). If there is no pulse, remove the pulse.

  The pattern detection unit 240 includes ten latch circuits 242 that operate as delay circuits, an OR gate 244, and an AND gate 246. Each of the latch circuits 242 delays data input from the previous stage by one sample. The outputs of the latch circuits 242 in the sixth to tenth stages are signals obtained by delaying the zero cross signal zc_org by 6 to 10 samples, respectively.

  The OR gate 244 generates a logical sum of outputs of the sixth to tenth latch circuits 242. The AND gate 246 receives the zero-cross signal zc_org that is not delayed and the output zc_org_dly_en of the OR gate 244. The output zc_org_dly_en of the OR gate 244 becomes a high level when the high level is included in the range of 6 to 10 samples from the zero cross signal zc_org input to the AND gate 246 at the same time. Therefore, the AND gate 246 masks the zero cross signal zc_org when the high level does not appear 6 to 10 samples before the input zero cross signal zc_org. FIG. 6A is an operation waveform diagram of the pattern detection unit 240.

  The offset difference limiter unit 250 further masks pulses due to erroneous detection from the zero cross signal zc_en_org. Specifically, the offset signal ofs_org generated by the offset detection unit 300 of FIG. 1 is sampled for each pulse of the zero-cross signal zc_en_org (that is, for each zero-cross point), and the value sampled at the adjacent preceding zero-cross point Is greater than a predetermined threshold, the pulse of the zero cross signal zc_en_org is masked. The offset signal ofs_org is a signal obtained by smoothing the baseband signal iq_avrg.

The offset difference limiter unit 250 includes an AND gate 252, a latch circuit 254, an adder 256, an absolute value circuit 258, a comparator 260, and an AND gate 262.
The AND gate 252 outputs a logical product of the enable signal EN8M and the zero cross signal zc_en_org. The latch circuit 254 samples the offset signal ofs_org using the output of the AND gate 252. The latch circuit 254 delays the offset signal ofs_org by the pulse interval of the zero cross signal zc_en_org.

  The adder 256 subtracts the delayed signal seri_thd_ofs from the offset signal ofs_org to generate a difference seri_thd_diff_org. The absolute value circuit 258 generates an absolute value seri_thd_diff of the difference seri_thd_diff_org. The comparator 260 compares the absolute difference value seri_thd_diff with a predetermined threshold value S7. For example, the threshold value is set to 24 (equivalent to 46.8 kHz). The output S8 of the comparator 260 becomes a high level when the difference absolute value seri_thd_diff is smaller than the threshold value S7. The AND gate 262 uses the output S8 of the comparator 260 to mask the zero cross signal zc_en_org.

  The offset difference limiter unit 250 can remove a zero cross caused by a sudden change in carrier offset. The output zc_en from the offset difference limiter unit 250 is output to the offset detection unit 300 at the subsequent stage. FIG. 6B is an operation waveform diagram of the offset difference limiter unit 250.

  FIG. 4 is a block diagram illustrating a configuration of the offset detection unit 300. The offset detection unit 300 uses the zero-cross signal zc_en to sample data corresponding to the baseband signal iq_avrg, and detects a carrier offset. Thereby, the carrier offset during the preamble period can be suitably detected.

  The offset detection unit 300 includes an offset detection block 310 and an offset adjustment unit 340.

  The offset detection block 310 includes a smoothing circuit 311, a latch circuit 320, a selector 322, a selector 324, a latch circuit 326, and an adder 328. The smoothing circuit 311 smoothes the baseband signal iq_avrg. The smoothing circuit 311 includes an adder 312, an adder 316, and a divider 318.

  The adder 312 generates the sum of the baseband signal iq_avrg and the delay signal delay8 (substantially an average considering the subsequent divider 318). The three latch circuits 314 delay each input by one symbol. The adder 316 generates a sum of outputs from the adder 312 and the three latch circuits 314. The divider 318 divides the sum of the adder 316 by 8. The smoothing circuit 311 calculates a moving average S9 in units of symbol time of the baseband signal iq_avrg, and smoothes the baseband signal iq_avrg.

  Three latch circuits 320 delay the output of the divider 318 by three symbols. The delayed moving average S9 is output as an offset signal ofs_org to the offset difference limiter 250 of the preamble detector 200 described above.

  In the selector 322, the offset signal ofs_org is input to the input 1, and the output signal of the limiter 330 is input to the input 0. The selector 322 selects the offset signal ofs_org at the timing when the zero cross signal zc_en generated by the preamble detector 200 becomes high level.

  In the selector 324, the output signal of the selector 322 is input to the input 1, and the output signal of the limiter 330 is input to the input 0. Inverter 325 inverts access code detection signal ACCDET. The selector 324 selects the output of the selector 322 at the timing when the inverted access code detection signal ACCDET becomes high level.

  As described above, the access code detection signal ACCDET becomes a low level during the period of the access code of the first 72 bits of the packet and then becomes a high level. Therefore, the selectors 322 and 324 select the offset signal ofs_org while the zero-cross detection signal zc_en is at a high level and the access code detection signal ACCDET is at a low level. In other cases, the output of the selector 324 is the output S10 of the limiter 330. By providing the selector 324, it is possible to prevent the carrier offset from being detected by a zero cross that is erroneously detected other than the access code.

  The latch circuit 326 latches the output of the selector 324 and synchronizes timing. The output of the latch circuit 326 is output as an offset signal OFS_O indicating the amount of carrier offset.

  When the access code period ends, offset detection section 300 finely adjusts the carrier offset value based on the subsequent baseband signal iq_avrg value. The offset adjustment unit 340 generates a correction value adj_data for fine adjustment. The adder 328 of the offset detection block 310 adds the correction value adj_data to the offset signal OFS_O. The limiter 330 limits the output range of the adder 328. Specifically, the output of the limiter 330 is limited to a range of −256 to +256 (−500 kHz to +500 kHz). In the Bluetooth system, since the bandwidth of one channel is 1 MHz, it is possible to prevent the carrier offset from being adjusted beyond the bandwidth by providing the limiter 330.

  The offset adjustment unit 340 includes a slice / edge detection unit 350, a counter 360, and an adjustment data generation unit 370. FIG. 7 is an operation waveform diagram of the offset adjustment unit 340.

  The slice edge detection unit 350 slices the baseband signal iq_avrg using the offset signal OFS_O, and generates a count clear signal cnt8_clr that becomes high level every time the two signals intersect. The slice edge detection unit 350 measures the period time (pulse interval) of the count clear signal cnt8_clr and generates a carrier offset correction value adj_data according to the period time.

  The slice edge detection unit 350 includes a comparator 352, a latch circuit 354, and an XOR gate 356. The comparator 352 generates a signal iq_high that becomes a high level when the baseband signal iq_avrg is greater than the offset signal OFS_O. The latch circuit 354 delays the signal iq_high by one sample. The XOR gate 356 outputs an exclusive OR of the signals iq_high and iq_high_dly. The output (count clear signal) cnt8_clr of the XOR gate 356 becomes a high level at every level transition of the signal iq_high.

  The counter 360 is an octal counter, and is reset every time the count clear signal cnt8_clr becomes high level, and performs a count-up operation based on the enable signal EN8M. The count value cnt_8 of the counter 360 is input to the selector 372.

  Since the enable signal EN8M has a sampling frequency that is eight times the symbol rate of 1 MHz, if the count value cnt_8 is near 7, correction of the carrier offset is not necessary. The adjustment data generation unit 370 generates the correction value adj_data according to the count value cnt_8.

The adjustment data generation unit 370 includes a selector 372, a sign inverter 374, a selector 376, and a selector 378.
The selector 372 has eight inputs and selects one of the inputs according to the value of the count value cnt_8. The number of inputs of the selector 372 may be set according to the decimal number of the counter 360. As an example, when the count value cnt_8 is 0, 3, 6, 7, the correction amount is 0. When the count value cnt_8 is 1, 2, the correction amount is −1 (−1.95 kHz) When the value cnt_8 is 4 or 5, the correction amount is set to 1 (+1.95 kHz). The setting of the correction amount is an example, and may be arbitrarily adjusted.

  The sign inverter 374 and the selector 372 invert the value of the correction value S12 according to the value of the signal iq_high_dly. Specifically, the sign inverter 374 inverts the sign of the output of the selector 372. The input S1 of the selector 376 receives the output S12 of the selector 372, and the input 0 receives the output S13 of the sign inverter 374. The selector 376 selects the signal S12 when the signal iq_high_dly is at the high level, and selects the signal S13 whose sign is inverted otherwise.

  The signal S14 is input to the input 1 of the selector 378, and the value 0 is input to the input 0. The selector 378 outputs the signal S14 as the correction value adj_data every time the offset signal OFS_O and the baseband signal iq_avrg cross each other, that is, every time the count clear signal cnt8_clr becomes high level. The correction value adj_data is set to 0 at other timings. By providing the offset adjusting unit 340, it is possible to suitably follow even when the carrier offset changes in the middle of a packet.

  According to receiver 1000 according to the present embodiment, carrier offset OFS_O can be detected and reflected in demodulation processing during a short time of the preamble.

  In the embodiment, the setting of the logical value of the high level and the low level is an example, and can be freely changed by appropriately inverting it with an inverter or the like.

  Although the present invention has been described based on the embodiments, the embodiments merely illustrate the principle and application of the present invention, and the embodiments are intended to include the idea of the present invention defined in the claims. Many modifications and changes in arrangement are possible within the range not leaving.

It is a block diagram which shows the structure of the receiver of the radio | wireless communications system which concerns on embodiment. It is a block diagram which shows the structure of the preamble detection part of FIG. It is a block diagram which shows the structure of the preamble detection part of FIG. It is a block diagram which shows the structure of the offset detection part of FIG. 5A and 5B are operation waveform diagrams of the preamble detector shown in FIG. 6A and 6B are operation waveform diagrams of the preamble detector shown in FIG. FIG. 5 is an operation waveform diagram of the offset adjustment unit of FIG. 4.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1000 ... Receiver, 2 ... Antenna, 4 ... Frequency conversion circuit, 6 ... FM detection circuit, 8 ... Offset detection circuit, 100 ... Delay buffer, 200 ... Preamble detection part, 210 ... Initial zero cross detection part, 212 ... Adder, 214 ... Latch circuit, 216 ... XOR gate, 220 ... ringing removal unit, 222 ... adder, 224 ... absolute value circuit, 226 ... comparator, 228 ... AND gate, 230 ... 3-bit counter, 232 ... comparator, 234 ... AND gate, 240 ... pattern detection unit, 242 ... latch circuit, 244 ... OR gate, 246 ... AND gate, 250 ... offset difference limiter unit, 252 ... AND gate, 254 ... latch circuit, 256 ... adder, 258 ... absolute value Circuit 260... Comparator 262. AND gate 300 300 offset detector 31 ... offset detection block, 311 ... smoothing circuit, 312 ... adder, 314 ... latch circuit, 316 ... adder, 318 ... divider, 320 ... latch circuit, 322 ... selector, 324 ... selector, 326 ... latch circuit, 328 ... adder, 330 ... limiter, 340 ... offset adjuster, 350 ... slice edge detector, 352 ... comparator, 354 ... latch circuit, 356 ... XOR gate, 360 ... counter, 370 ... adjustment data generator, 372 ... Selector, 374... Sign inverter, 376... Selector, 378.

Claims (21)

A carrier offset detection circuit that is provided in a demodulation circuit that demodulates a reception signal modulated by FSK (Frequency Shift Keying) and detects an offset between carrier frequencies on the reception side and the transmission side,
A digital baseband signal representing the level of frequency shift of the received signal on the basis of the carrier frequency on the receiving side, and the baseband signal generated during the preamble period and a baseband signal delayed by one symbol; A zero-cross detector for detecting the zero-cross point of
An offset detector that sets the value of the baseband signal at the detected zero-crossing timing to the offset value of the carrier frequency;
With
The offset detection unit compares the baseband signal with an offset value of the current carrier frequency, detects a period in which the magnitude relationship changes, and corrects the offset value of the current carrier frequency based on the period. A characteristic carrier offset detection circuit.   The said offset detection part smoothes the said baseband signal, The value of the said smoothed baseband signal in the timing of the detected zero cross is set to the offset value of the said carrier frequency. Carrier offset detection circuit.   The carrier offset detection circuit according to claim 2, wherein the smoothing is a moving average process using a symbol time as a unit.   3. The carrier offset detection circuit according to claim 2, wherein the offset detection unit adds the baseband signal and a signal obtained by delaying the baseband signal by one symbol, and smoothes the added signal.   When the difference between the value of the baseband signal at the detected zero-cross point and the value of the baseband signal at a predetermined time before the zero-cross point is smaller than a predetermined threshold, the zero-cross detection unit The carrier offset detection circuit according to claim 1, further comprising a ringing removal unit that masks the signal.   The zero cross detection unit includes a ringing removal unit that masks the detected zero cross point when a time interval between the detected zero cross point and the preceding zero cross point is equal to or less than a predetermined threshold value. The carrier offset detection circuit according to 1.   The said zero cross detection part contains the pattern detection part which masks the said detected zero cross point, when a zero cross point does not exist in the timing of about 1 symbol time before the detected zero cross point. Carrier offset detection circuit. The zero-cross detection unit samples a signal obtained by smoothing the baseband signal at each detected timing of the zero-cross point, and when the difference from the value sampled at the preceding zero-cross point is larger than a predetermined threshold value, the detection The carrier offset detection circuit according to claim 1, further comprising an offset difference limiter circuit for masking the zero cross point.   The offset detection unit receives a detection signal indicating that the input baseband signal is an access code, and when the input code is an access code, the offset detection unit calculates the value of the baseband signal at the detected zero-cross timing as the carrier frequency. The carrier offset detection circuit according to claim 1, wherein the carrier offset detection circuit is set to the offset value. A carrier offset detection circuit that is provided in a demodulation circuit that demodulates a reception signal modulated by FSK (Frequency Shift Keying) and detects an offset between carrier frequencies on the reception side and the transmission side,
A preamble detection unit that receives a digital baseband signal representing a level of frequency shift of the received signal with reference to the carrier frequency on the receiving side, and detects a preamble from the baseband signal;
An offset detector configured to smooth the baseband signal and set a value of the smoothed baseband signal during the preamble period to an offset value of the carrier frequency;
With
The offset detection unit compares the baseband signal with an offset value of the current carrier frequency, detects a period in which the magnitude relationship changes, and corrects the offset value of the current carrier frequency based on the period. A characteristic carrier offset detection circuit. A zero-cross detector that detects a zero-cross point that occurs during a preamble period of the baseband signal and the baseband signal delayed by one symbol;
The carrier offset detection circuit according to claim 10, wherein the offset detection unit sets the smoothed baseband signal at a zero cross point to an offset value of the carrier frequency.   The carrier offset detection circuit according to claim 10, wherein the smoothing is a moving average process using a symbol time as a unit.   The carrier offset detection circuit according to claim 10, wherein the offset detection unit adds the baseband signal and a signal obtained by delaying the baseband signal by one symbol, and smoothes the added signal.   When the difference between the value of the baseband signal at the detected zero-cross point and the value of the baseband signal at a predetermined time before the zero-cross point is smaller than a predetermined threshold, the zero-cross detection unit The carrier offset detection circuit according to claim 11, further comprising a ringing removal unit that masks the signal.   The zero cross detection unit includes a ringing removal unit that masks the detected zero cross point when a time interval between the detected zero cross point and the preceding zero cross point is equal to or less than a predetermined threshold value. The carrier offset detection circuit according to 11.   The said zero cross detection part contains the pattern detection part which masks the said detected zero cross point, when a zero cross point does not exist in the timing of about 1 symbol time before the detected zero cross point. Carrier offset detection circuit. The zero-cross detection unit samples a signal obtained by smoothing the baseband signal at each detected timing of the zero-cross point, and when the difference from the value sampled at the preceding zero-cross point is larger than a predetermined threshold value, the detection The carrier offset detection circuit according to claim 11, further comprising an offset difference limiter circuit that masks the zero-cross point.   The offset detection unit receives a detection signal indicating that the input baseband signal is an access code, and when the input code is an access code, the offset detection unit calculates the value of the baseband signal at the detected zero-cross timing as the carrier frequency. The carrier offset detection circuit according to claim 11, wherein the carrier offset detection circuit is set to the offset value.   An information communication device comprising the carrier offset detection circuit according to claim 1. A method of detecting a carrier frequency offset between a receiving side and a transmitting side when demodulating a reception signal modulated by FSK (Frequency Shift Keying),
A digital baseband signal representing the level of frequency shift of the received signal is received on the basis of the carrier frequency at the receiving side, and is generated during the preamble period of the baseband signal and the baseband signal delayed by one symbol. Detecting a zero-cross point;
Setting the value of the baseband signal at the detected zero-crossing timing to the offset value of the carrier frequency;
Comparing the baseband signal with the offset value of the current carrier frequency, detecting a period when the magnitude relationship changes, and correcting the offset value of the current carrier frequency based on the period;
A carrier offset detection circuit comprising: A method of detecting a carrier frequency offset between a receiving side and a transmitting side when demodulating a reception signal modulated by FSK (Frequency Shift Keying),
Receiving a digital baseband signal representing a level of frequency shift of the received signal on the basis of the carrier frequency on the receiving side, and detecting a preamble from the baseband signal;
Smoothing the baseband signal and setting a value of the smoothed baseband signal during the preamble to an offset value of the carrier frequency;
Comparing the baseband signal with the offset value of the current carrier frequency, detecting a period when the magnitude relationship changes, and correcting the offset value of the current carrier frequency based on the period;
A carrier offset detection method comprising:

Images