JP4641927B2 - FSK demodulation circuit - Google Patents

Description

  The present invention relates to an FSK demodulation circuit that performs FSK (frequency shift keying) demodulation in wireless communication.

  Conventionally, a demodulation circuit using an FM detector, which is regarded as an analog FM (frequency modulation) signal, is often used for demodulating an FSK-modulated signal, and is not patented as a commonly used FM detector. There is something as shown in Document 1.

  FIG. 9 is a configuration diagram of a conventional FSK demodulator circuit using the FM detector shown in Non-Patent Document 1. The FSK demodulating circuit in FIG. 9 includes input terminals 11 and 12, an FM detector 13, a synchronization / determination circuit 91, and an output terminal 18, and the FM detector 13 further includes phase shift circuits 131 and 132, a multiplication circuit 133. , 134, a subtracting circuit 135, and an LPF (low-pass filter) 136.

The received FSK modulation signal is first converted into an in-phase and quadrature phase IF band signal using a quadrature mixer not shown in FIG. 9, and the in-phase and quadrature signal are input to input terminals 11 and 12, respectively. Is done. The FM detector 13 detects a signal having an amplitude corresponding to the frequency of the original FSK signal from these signals, and determines a threshold value of the signal amplitude at a period corresponding to a bit rate known in advance in the synchronization / determination circuit 91. As a result, the output data is output to the output terminal 18. In FIG. 9, the phase shift circuits 131 and 132 are used. However, as shown in Non-Patent Document 1, a similar detection signal can be obtained by using these as differential circuits.
P. Choi, et a1., “An Experimental Coin-Sized Radio for Extremely Low-Power WPAN (IEEE 802.15.4) Application at 2.4GHz”, IEEE Journa1 of Solid-State Circuits, Vo1.38, No.12, pp .2258-2268, December 2003

  FIG. 10 is an explanatory diagram of the operation of the synchronization / determination circuit 91 in the conventional FSK demodulating circuit, and the horizontal axis indicates time. (A) shows an output example of the FM detector 13 when there is no noise, and (b) shows an output example of the FM detector 13 when there is a large noise. The vertical axes of (a) and (b) indicate the signal amplitude. Further, (c) shows an example of a bit synchronization point at which the threshold determination of the signal amplitude in the synchronization / determination circuit 91 is performed, and the determination based on the data threshold value 0 is performed at the bit synchronization point indicated by the arrow. In the example of FIG. 10, the data can be correctly determined when there is no noise (a), but when there is a large noise (b), the margin for determining the threshold value of the data becomes small. In the example, a determination error occurs at time t3. Therefore, in the conventional FSK demodulator circuit, there is a possibility that a data error may occur when there is a large noise, and the communication performance deteriorates.

  The present invention has been made in view of the above points, and an object of the present invention is to provide an FSK demodulator circuit that is unlikely to cause a data determination error even when there is a large noise, and that does not easily deteriorate communication performance. It is.

In order to solve the above-described problem, the FSK demodulating circuit according to the first aspect of the present invention inputs a pair of IF signals after changing the FSK modulated signal into an in-phase and quadrature-phase IF signal, and outputs the frequency of the FSK modulated signal. An FM detector that outputs an FM detection signal having an amplitude corresponding to the sampling frequency, a sampling / polarity determination circuit that samples and polarizes the FM detection signal output from the FM detector and converts the FM detection signal into a digital FM detection signal, and the sampling A bit synchronization circuit that detects a bit synchronization point from a digital FM detection signal output from the polarity determination circuit, and the digital FM detection signal between the previous and next bit synchronization points based on the bit synchronization point detected by the bit synchronization circuit. The integration circuit newly integrating and the integration signal output from the integration circuit at the timing of the bit synchronization point are compared with the first threshold value. An FSK demodulating circuit having a data determining circuit for determining data, wherein the bit synchronization circuit includes a correlator that correlates a known bit pattern corresponding to a preamble and an input signal, and the correlator And a threshold value determination circuit for obtaining the bit synchronization point by comparing the output with a predetermined second threshold value.
According to a second aspect of the present invention, in the FSK demodulating circuit according to the first aspect, the correlator includes one or more stages of cascaded delay circuits that delay the input digital FM detection signal by one sample, and an input A plurality of multiplication circuits for multiplying each of the digital FM detection signal and the output of the delay circuit cascade-connected to one or more stages by a coefficient corresponding to the known bit pattern, and the plurality of multiplication circuits And an adder circuit that adds all the outputs of the threshold value, and the threshold value judgment circuit has a condition that the output of the correlator is “below the threshold value after being equal to or greater than a predetermined threshold value as an absolute value”. It is characterized by operating so that the timing to satisfy is a bit synchronization point.
According to a third aspect of the present invention, in the FSK demodulating circuit according to the first aspect, the bit synchronization circuit applies a ± 1 bipolar signal, which is the digital FM detection signal, to “0”, “ A bipolar / unipolar conversion circuit for converting the bit string signal to “1”, and the correlator delays the bit string signal input from the bipolar / unipolar conversion circuit by one bit or a plurality of cascaded delays. A plurality of exclusive ORs that perform an exclusive OR operation between the circuit and each of the input bit string signal and the output of the delay circuit cascade-connected to one or more stages and a bit coefficient corresponding to the known bit pattern A threshold value determination circuit comprising: an OR circuit; and an adder circuit that counts the number of “0” s output from the plurality of exclusive OR circuits. The timing when the output of the correlator satisfies the condition of “below the threshold value after becoming higher than the higher threshold value, or exceeding the threshold value after becoming equal to or lower than the lower threshold value”. Is a bit synchronization point.
According to a fourth aspect of the present invention, in the FSK demodulating circuit according to the second or third aspect, the first and second threshold determination circuits and the first and second threshold determination circuits are replaced by the threshold determination circuit. An OR circuit that selects an output, and sets a threshold value in the second threshold value determination circuit to be looser than a threshold value in the first threshold value determination circuit, and the OR circuit first determines the first threshold value determination. A circuit output is selected, and if there is no bit synchronization point in a predetermined period, the output of the second threshold value determination circuit is selected.
According to a fifth aspect of the present invention, in the FSK demodulating circuit according to the second or third aspect, the first and second correlators are provided in place of the correlator, and the threshold determination circuit includes the first and second correlators. The first correlator is configured to use the same bit pattern as that of the correlator and a signal to be input. The second correlator is configured to take a correlation between an expected bit pattern when there is a DC offset and an input signal.

  According to the present invention, after obtaining a correlation value with a known bit pattern such as a preamble in a correlator in a bit synchronization circuit, a threshold value determination circuit obtains a bit synchronization point by comparing and determining the correlation value with a threshold value, Since the data is restored by newly integrating the digital FM detection signal between the previous and next bit synchronization points in the integration circuit, the influence of noise is mitigated, and it is difficult to cause data judgment errors even when there is a large noise. Therefore, it is possible to realize an FSK demodulator circuit that hardly deteriorates communication performance. In addition, a bit synchronization point is obtained by switching between two threshold judgment circuits having different thresholds, or a correlator changed to a bit pattern considering a DC offset due to imperfection of the FM detector and the known bit pattern are used. By obtaining a bit synchronization point using two correlators, a correlator, a good bit synchronization point can be obtained even when there is a DC offset, and therefore communication performance is degraded even when there is a DC offset. An FSK demodulating circuit that is difficult to invite can be realized.

[First embodiment]
FIG. 1 is a block diagram showing a configuration of an FSK demodulating circuit according to a first embodiment of the present invention. The FSK demodulating circuit in FIG. 1 includes input terminals 11 and 12, an FM detector 13, a sampling / polarity determination circuit 14, a bit synchronization circuit 15, an integration circuit 16, a data determination circuit 17, and an output terminal 18, and further includes an FM. The detector 13 includes phase shift circuits 131 and 132, multiplication circuits 133 and 134, a subtraction circuit 135, and an LPF 136.

  The received FSK modulated signal is first converted into an in-phase and quadrature IF band signal using a quadrature mixer not shown in FIG. 1, and the in-phase and quadrature signals are input to input terminals 11 and 12, respectively. Is done. The FM detector 13 detects a signal having an amplitude corresponding to the frequency of the original FSK signal from these signals, and the sampling / polarity determination circuit 14 converts the output of the FM detector 13 into a digital signal.

  FIG. 2 is a block diagram illustrating a configuration example of the bit synchronization circuit 15. 2 includes an input terminal 21, a correlator 22, a threshold determination circuit 25, and an output terminal 26. The correlator 22 further includes delay circuits 221 to 227, multiplication circuits 230 to 237, and an addition circuit 240. Consists of. FIG. 2 shows a configuration when the number of taps is 8, as an example.

  In general, in wireless communication using FSK modulation, a known bit pattern called a preamble is transmitted prior to data in order to obtain bit synchronization. Here, a 2-bit repetitive pattern such as “01100110...” Is assumed as a preamble. It can be seen that the repetitive basic pattern is “0110”. Assuming that the sampling rate in the sampling / polarity determination circuit 14 is N times the bit rate, and that the bit “0” is determined to be positive (+1) and the bit “1” is determined to be negative (−1), It can be seen that the output of the basic pattern sampling / polarity determination circuit 14 appears as N patterns of +1, 2N of -1, and N of +1. For the sake of simplicity, the bit synchronization circuit 15 in FIG. 2 represents a configuration in which N = 2. In this case, the basic pattern for correlation in the correlator 22 is “+ 1 + 1-1-1-1-1 + 1 + 1”, and the number of taps in the correlator 22 is 8.

  FIG. 3 is an explanatory diagram of the operation of the bit synchronization circuit 15 in the FSK demodulation circuit of the present invention and the bit restoration operation by the integration circuit 16 and the data determination circuit 17, and the horizontal axis represents time. Further, in FIG. 3, the left half shows an example when there is no noise, and the right half shows an example when there is a large noise. (A) has shown the output example of the correlator 22, and the vertical axis | shaft represents the signal amplitude. The threshold determination circuit 25 that determines the correlation output with the positive and negative thresholds always checks whether or not the condition that “the absolute value becomes greater than or equal to a predetermined threshold and then becomes less than the threshold” is satisfied. A time position that is equal to or greater than the threshold value is used as a bit synchronization point, and the information is output to the output terminal 26. FIG. 3B shows the bit synchronization points obtained as described above by arrows.

  In the FSK demodulating circuit of the present invention shown in FIG. 1, the integrating circuit 16 is based on the bit synchronization point from the synchronization circuit 15, and the sampling / polarity determination circuit 14 of each time from the bit synchronization point to the next bit synchronization point. Newly integrates the output digital signal amplitude. Then, the data determination circuit 17 generates output data by performing threshold determination based on the integration result up to the bit synchronization point, and outputs the output data to the output terminal 18.

  3, (c) shows an output example of the FM detector 13, (d) shows an output example of the sampling / polarity determination circuit 14, (e) shows an output example of the integration circuit 16, and each vertical axis indicates the signal amplitude. Represents. As shown in the right half of FIG. 3, even when there is a large noise, it can be seen that the data determination circuit 17 can restore correct data by determining the polarity of (e) at the bit synchronization point.

[Second embodiment]
FIG. 4 is a block diagram showing a configuration example of the bit synchronization circuit 15 according to the second embodiment of the present invention. The bit synchronization circuit in FIG. 4 includes an input terminal 21, a bipolar / unipolar (B / U) conversion circuit 41, a correlator 42, a threshold determination circuit 45, and an output terminal 26. Further, the correlator 42 includes a delay circuit 421. To 427, exclusive OR circuits 430 to 437, and an adder circuit 440.

  In FIG. 4, the ± 1 output signal of the sampling / polarity determination circuit 14 input from the input terminal 21 is converted into a 1-bit signal of “0” or “1” in the B / U conversion circuit 41. Further, in the correlator 42, the multiplication circuit 230 to 237 in the correlator 22 of FIG. 2 is changed to the exclusive OR operation of the exclusive OR circuit 430 to 437, whereby the adder circuit 440 in the correlator 42 is changed. All the operations other than the above are performed by 1-bit operation, and the circuit can be expected to be miniaturized.

  FIG. 5 is an explanatory diagram of the operation of the bit synchronization circuit 15 shown in FIG. Similar to FIG. 3, the left half shows an example when there is no noise, and the right half shows an example when there is a large noise. (A) has shown the output example of the correlator 42, and the vertical axis | shaft represents the signal amplitude. Since the exclusive OR operation outputs “0” when two input values match and “1” when they do not match, the adder circuit 440 outputs “0” from the exclusive OR circuits 430 to 437. It operates to count the number of "0". For this reason, the amplitude of (a) takes only positive values from 0 when all do not match to 8 when all match. The threshold determination circuit 45 has two thresholds of high and low that are set in advance. “After being higher than the higher threshold, the threshold is less than this threshold. Alternatively, after being lower than the lower threshold, this threshold Whether or not the condition “exceeded” is satisfied is always checked, and the time position that is greater than or less than the threshold when this condition is met is set as the bit synchronization point, and the information is output to the output terminal 26. 5 (b) indicates the bit synchronization points obtained as described above by arrows.

[Third embodiment]
FIG. 6 is a block diagram showing a configuration example of the bit synchronization circuit 15 according to the third embodiment of the present invention. In FIG. 6, 61 and 62 are threshold determination circuits, 63 is an OR circuit, and the same reference numerals are given to the same components as in FIG.

  In the FSK demodulator circuit of the present invention shown in FIG. 1, a DC offset is generated in the output amplitude of the FM demodulator 13 due to imperfection in the realization of the FM demodulator 13, and at the output of the sampling / polarity determination circuit 14, Appears as a difference between positive and negative bit periods.

  FIG. 7 is an explanatory diagram of the operation of the bit synchronization circuit 15 when there is a DC offset, and is expressed in the same manner as FIG. The influence of the DC offset appears as a positive / negative imbalance at the output of the correlator 22 even when there is no noise. For example, in the case shown in FIG. 7, the positive amplitude is reduced. This effect becomes even more pronounced in the presence of large noise, and as seen in the second positive peak from the right in FIG. 7, the peak value does not exceed the threshold and therefore the bit sync point can be lost. There is sex.

  The bit synchronization circuit in FIG. 6 makes it possible to obtain bit synchronization information even in such a case, and the threshold determination circuits 61 and 62 perform the same condition determination as the threshold determination circuit 25 in FIG. In the OR circuit 63, the result of the strict threshold value is adopted when there is no noise, but when there is a large noise and the bit synchronization point cannot be obtained, the result of the gentle threshold value is adopted. It is.

[Fourth embodiment]
FIG. 8 is a block diagram showing a configuration example of the bit synchronization circuit 15 according to the fourth embodiment of the present invention. 8 includes an input terminal 21, correlators 81 and 84, a threshold determination circuit 87, and an output terminal 26. The correlator 81 further includes delay circuits 811 to 817, multiplier circuits 820 to 827, and an adder. The correlator 84 includes a delay circuit 841 to 847, a multiplier circuit 850 to 857, and an adder circuit 860.

  The correlators 81 and 84 both have the same configuration as that of the correlator 22 in FIG. 2, but the coefficients multiplied by the multiplier circuits 820 to 827 of the correlator 81 and the multiplier circuits 850 to 857 of the correlator 84 are different. ing. That is, the coefficients of the multiplier circuits 820 to 827 of the correlator 81 are suitable when there is no DC offset, while the coefficients of the multiplier circuits 850 to 857 of the correlator 84 cause a DC offset and have a positive / negative balance. It is suitable when it collapses. Specifically, in the example of FIG. 8, the second multiplier circuit 856 from the right of the correlator 84 has a coefficient different from that of the second multiplier circuit 856 from the right of the correlator 81, and the correlator 84 has a basic pattern due to the DC offset. Is assumed to change to “+ 1 + 1-1-1-1-1-1 + 1”.

  In the configuration of the bit synchronization circuit as shown in FIG. 6, since one of the two thresholds is relaxed in order to cope with the DC offset, the configuration is easily affected by noise. In the bit synchronization circuit having the configuration, it is not necessary to loosen the threshold in order to configure the correlator 84 in consideration of the DC offset, and a configuration strong against the influence of noise can be maintained. The threshold determination circuit 87 can obtain the bit synchronization point when any one of the correlators 81 and 84 satisfies the same condition as the threshold determination circuit 25 in FIG.

  The bit synchronization circuit shown in FIGS. 6 and 8 is configured to be resistant to DC offset based on the bit synchronization circuit shown in FIG. 2 using a multiplication circuit. Similarly, the exclusive OR circuit shown in FIG. 4 is used. The configuration can also be based on the bit synchronization circuit.

It is a block diagram which shows the structure of the FSK demodulation circuit of 1st Example of this invention. FIG. 2 is a block diagram illustrating a configuration example of a bit synchronization circuit of the FSK demodulation circuit in FIG. 1. FIG. 3 is a timing chart of the operation of the bit synchronization circuit of FIG. It is a block diagram which shows the structural example of the bit synchronization of 2nd Example. 5 is a timing chart of the operation of the bit synchronization circuit of FIG. It is a block diagram which shows the structural example of the bit synchronous circuit of a 3rd Example. It is a timing chart of the operation of the bit synchronization circuit when there is a DC offset. It is a block diagram which shows the structural example of the bit synchronous circuit of a 4th Example. It is a block diagram which shows the structure of the conventional FSK demodulation circuit. It is a timing chart of the operation | movement of the synchronous / determination circuit in the conventional FSK demodulation circuit.

Explanation of symbols

  11, 12: Input terminal, 13: FM detector, 14: Sampling / polarity determination circuit, 15: Bit synchronization circuit, 16: Integration circuit, 17: Data determination circuit, 18: Output terminal, 21: Input terminal, 22: Correlator, 25: threshold determination circuit, 26: output terminal, 41: B / U conversion circuit, 42: correlator, 45: threshold determination circuit, 61, 62: threshold determination circuit, 63: OR circuit, 81, 84 : Correlator, 87: Threshold judgment circuit, 91: Synchronization / determination circuit, 131, 132: Phase shift circuit, 133, 134: Multiplication circuit, 135: Subtraction circuit, 136: LPF, 221-227: Delay circuit, 230- 237: multiplication circuit, 240: addition circuit, 421 to 427: delay circuit, 430 to 437: exclusive logic circuit, 440: addition circuit, 811 to 817: delay circuit, 820 to 827: multiplication times , 830: adder circuit, 841-847: delay circuit, 850-857: multiplication circuit, 860: adder circuit.

Claims (5)

An FM detector that inputs a pair of IF signals after changing the FSK modulation signal to an in-phase and quadrature-phase IF signal and outputs an FM detection signal having an amplitude corresponding to the frequency of the FSK modulation signal; and the FM detection A sampling / polarity determination circuit for sampling and polarity determination of an FM detection signal output from the detector and converting it to a digital FM detection signal, and bit synchronization for detecting a bit synchronization point from the digital FM detection signal output from the sampling / polarity determination circuit Circuit, an integration circuit that newly integrates the digital FM detection signal between the previous and next bit synchronization points based on the bit synchronization point detected by the bit synchronization circuit, and an output from the integration circuit at the timing of the bit synchronization point An FSK demodulating circuit having a data determining circuit that compares the integrated signal to be compared with a first threshold value to determine data. ,
The bit synchronization circuit includes a correlator that correlates a known bit pattern corresponding to a preamble and an input signal, and compares the output of the correlator with a predetermined second threshold value to determine the bit synchronization point. An FSK demodulating circuit comprising a threshold determination circuit to be obtained. The FSK demodulator circuit according to claim 1,
The correlator includes one or more stages of cascaded delay circuits that delay the input digital FM detection signal by one sample, and the input digital FM detection signals and one or more stages of cascaded delay circuits. A plurality of multiplication circuits for multiplying each of the outputs by a coefficient corresponding to the known bit pattern, and an addition circuit for adding all the outputs of the plurality of multiplication circuits,
The threshold determination circuit operates so that a timing that satisfies the condition that the output of the correlator becomes less than the threshold after being equal to or greater than a predetermined threshold as an absolute value is set as a bit synchronization point. FSK demodulator circuit. The FSK demodulator circuit according to claim 1,
The bit synchronization circuit includes a bipolar / unipolar conversion circuit that converts a ± 1 bipolar signal, which is the digital FM detection signal, into a bit string signal of “0” and “1” before the correlator,
The correlator includes one or more stages of cascaded delay circuits that delay the bit string signal input from the bipolar / unipolar conversion circuit by one bit, and the input bit string signals and the one or more stages dependent A plurality of exclusive OR circuits for performing an exclusive OR operation on each of the outputs of the connected delay circuits and the bit coefficient corresponding to the known bit pattern; and outputs of the plurality of exclusive OR circuits An adder circuit that counts the number of “0”,
The threshold judgment circuit states that the output of the correlator is “below the threshold value after becoming higher than the higher threshold value, or exceeds the threshold value after becoming equal to or lower than the lower threshold value”. An FSK demodulating circuit which operates so as to use a timing when a condition is satisfied as a bit synchronization point. In the FSK demodulating circuit according to claim 2 or 3,
Instead of the threshold determination circuit, a first and second threshold determination circuit and an OR circuit for selecting the outputs of the first and second threshold determination circuits are provided, and the threshold in the second threshold determination circuit is set. The logical sum circuit first selects the output of the first threshold value judgment circuit and sets the second threshold value when there is no bit synchronization point in a predetermined period. An FSK demodulating circuit configured to select an output of the threshold value judging circuit. In the FSK demodulating circuit according to claim 2 or 3,
In place of the correlator, a first correlator and a second correlator are provided, and the threshold determination circuit uses the bit sync point of the output of one of the first and second correlators as a bit sync point. Configured to
The first correlator is configured to correlate an input signal with the same known bit pattern as the correlator;
The FSK demodulating circuit, wherein the second correlator is configured to take a correlation between a bit pattern expected when there is a DC offset and an input signal.

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