JP5713182B2 - Silicon electrode plate for plasma etching - Google Patents
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- JP5713182B2 JP5713182B2 JP2011019180A JP2011019180A JP5713182B2 JP 5713182 B2 JP5713182 B2 JP 5713182B2 JP 2011019180 A JP2011019180 A JP 2011019180A JP 2011019180 A JP2011019180 A JP 2011019180A JP 5713182 B2 JP5713182 B2 JP 5713182B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
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- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
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Description
この発明は、プラズマエッチングの面内均一性が向上するプラズマエッチング用シリコン電極板に関するものである。 The present invention relates to a silicon electrode plate for plasma etching that improves the in-plane uniformity of plasma etching.
一般に、半導体集積回路を製造する工程において使用するシリコンウエハをエッチングするためのプラズマエッチング装置は、図１に示すように、真空容器１内にシリコン電極板２および架台３が間隔をおいて設けられている。このプラズマエッチング装置では、架台３の上にシリコンウエハ４を載置し、エッチングガス７をシリコン電極板２に設けられた貫通細孔５を通してシリコンウエハ４に向って流しながら高周波電源６により電極板２と架台３との間に高周波電圧を印加し、高周波電圧の印加によりシリコン電極板２と架台３との間の空間にプラズマ１０を発生させ、このプラズマ１０による物理反応と、シリコン−エッチングガス７による化学反応とにより、シリコンウエハ４の表面をエッチングする（特許文献１参照）。
In general, in a plasma etching apparatus for etching a silicon wafer used in a process of manufacturing a semiconductor integrated circuit, as shown in FIG. 1, a silicon electrode plate 2 and a pedestal 3 are provided in a vacuum container 1 with a space therebetween. ing. In this plasma etching apparatus, a silicon wafer 4 is placed on a gantry 3, and an electrode plate is applied by a high
従来、シリコン電極板２はカーボンで構成された電極板が使用されたこともあったが、近年、主として単結晶シリコン、多結晶シリコンまたは柱状晶シリコンからなるシリコン電極板が使用されている。 Conventionally, an electrode plate made of carbon has been used as the silicon electrode plate 2, but in recent years, a silicon electrode plate mainly made of single crystal silicon, polycrystalline silicon or columnar crystal silicon has been used.
上記従来の技術には、以下の課題が残されている。
従来のシリコン電極板では、プラズマエッチング時に対向する被エッチング物との間に生じたプラズマによって表面が徐々に消耗して凹凸が生じ、この凹凸によって異常放電が生じるおそれがあった。異常放電が生じると、エッチングの均一性が悪化してしまうという不都合がある。
このようなプラズマエッチングによる表面の凹凸は、平面内において比抵抗値にバラツキが存在しているため、対向する被エッチング物との間のプラズマ密度が不均一になって生じると考えられる。したがって、表面の凹凸を抑えるためには、比抵抗値の面内バラツキを抑える必要があるが、ドーパント含有量に面内差があるため、比抵抗値の面内バラツキを抑えることは困難であった。特に、高比抵抗値では、ドーパント含有量の面内差が大きく影響するため、比抵抗値の面内バラツキを抑えることが難しい。このように従来では、被エッチング物との間のプラズマ密度を均一に保持することが困難なため、被エッチング物であるウエハ面内のエッチングレートを均一化させることが難しいという問題があった。
The following problems remain in the conventional technology.
In the conventional silicon electrode plate, the surface is gradually consumed by the plasma generated between the object to be etched at the time of plasma etching, and irregularities are generated, which may cause abnormal discharge. When abnormal discharge occurs, there is a disadvantage that the uniformity of etching deteriorates.
Such unevenness of the surface due to plasma etching is considered to be caused by nonuniform plasma density between the object to be etched because the specific resistance value varies in a plane. Therefore, in order to suppress the unevenness of the surface, it is necessary to suppress the in-plane variation of the specific resistance value. However, since there is an in-plane difference in the dopant content, it is difficult to suppress the in-plane variation of the specific resistance value. It was. In particular, at a high specific resistance value, the in-plane difference of the dopant content greatly affects, so it is difficult to suppress the in-plane variation of the specific resistance value. As described above, conventionally, since it is difficult to uniformly maintain the plasma density with the object to be etched, there is a problem that it is difficult to make the etching rate within the wafer surface, which is the object to be etched, uniform.
本発明は、前述の課題に鑑みてなされたもので、プラズマエッチングによって生じる表面の凹凸を抑制し、均一なエッチングが可能になるプラズマエッチング用シリコン電極板を提供することを目的とする。 The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a silicon electrode plate for plasma etching that can suppress surface unevenness caused by plasma etching and enables uniform etching.
本発明者等は、比抵抗値の面内均一性が良好でプラズマエッチングに際してエッチングレートの面内均一性が向上するシリコン電極板を得るべく研究を行った。その結果、シリコン中にＢと共にＡｌをドーピングすることで、プラズマエッチングにおいて表面における凹凸の発生を抑制可能なことを見出した。 The inventors of the present invention have studied to obtain a silicon electrode plate having good in-plane uniformity of specific resistance and improved in-plane uniformity of etching rate during plasma etching. As a result, it was found that the formation of irregularities on the surface can be suppressed in plasma etching by doping Al together with B in silicon.
したがって、本発明は、上記知見から得られたものであり、前記課題を解決するために以下の構成を採用した。すなわち、本発明のプラズマエッチング用シリコン電極板は、ＢとＡｌとがドーパントとして添加された単結晶シリコンで構成され、Ａｌの濃度が、１×１０１３ａｔｏｍｓ／ｃｍ３以上であることを特徴とする。 Therefore, the present invention has been obtained from the above findings, and the following configuration has been adopted in order to solve the above problems. That is, the silicon electrode plate for plasma etching according to the present invention is composed of single crystal silicon to which B and Al are added as dopants, and the concentration of Al is 1 × 10 13 atoms / cm 3 or more. To do.
このプラズマエッチング用シリコン電極板では、Ｂ（ボロン）とＡｌとがドーパントとして添加された単結晶シリコンで構成されているので、単結晶シリコンの電気特性が面内で均一化され、プラズマエッチングにおいて表面が消耗する際に凹凸を極めて少なくすることができる。これは、Ｂに比べて拡散係数の大きいＡｌが添加されると、ＢよりもＡｌが拡散し易く、比抵抗値の面内均一性が向上するためである。このように比抵抗値の面内均一性が向上したことにより、被エッチング物との間のプラズマ密度が均一化して、表面の消耗状態も均一化されて凹凸がほとんど生じないことから、異常放電の発生を抑制してエッチングの均一化を図ることができる。また、添加されるＡｌの共有結合半径が、Ｓｉとほぼ同等であることから、不純物添加による格子歪みが生じ難く、内在する歪みを抑制でき、割れを防止できる。
なお、添加するＡｌの濃度を上記下限値以上に設定した理由は、１×１０１３ａｔｏｍｓ／ｃｍ３未満であると、上述した比抵抗値の面内均一性の効果が明確に現れないためである。
Since this silicon electrode plate for plasma etching is composed of single crystal silicon to which B (boron) and Al are added as dopants, the electrical characteristics of the single crystal silicon are made uniform in the plane, and the surface in plasma etching is As a result, the unevenness can be extremely reduced. This is because when Al having a larger diffusion coefficient than B is added, Al diffuses more easily than B and the in-plane uniformity of the specific resistance value is improved. Since the in-plane uniformity of the specific resistance value is improved in this way, the plasma density with the object to be etched is made uniform, the surface wear state is also made uniform, and irregularities are hardly generated. Etching can be suppressed and etching can be made uniform. Further, since the covalent bond radius of Al to be added is substantially the same as that of Si, lattice distortion due to the addition of impurities hardly occurs, the inherent distortion can be suppressed, and cracking can be prevented.
The reason why the concentration of Al to be added is set to be equal to or higher than the lower limit value is that the effect of in-plane uniformity of the specific resistance value described above does not clearly appear when the concentration is less than 1 × 10 13 atoms / cm 3. is there.
また、本発明のプラズマエッチング用シリコン電極板は、Ａｌの濃度が、５×１０１３ａｔｏｍｓ／ｃｍ３以下であることが好ましい。
すなわち、このプラズマエッチング用シリコン電極板では、Ａｌの濃度が、５×１０１３ａｔｏｍｓ／ｃｍ３以下であるので、単結晶化率の低下を抑制することができる。添加するＡｌの濃度を上記上限値以下に設定した理由は、５×１０１３ａｔｏｍｓ／ｃｍ３を超えるとＳｉ単結晶化の阻害要因となり単結晶化率（インゴット中の単結晶部の割合）が小さくなってしまい、製造歩留まりが低下するためである。
The silicon electrode plate for plasma etching according to the present invention preferably has an Al concentration of 5 × 10 13 atoms / cm 3 or less.
That is, in this silicon electrode plate for plasma etching, since the Al concentration is 5 × 10 13 atoms / cm 3 or less, a decrease in the single crystallization rate can be suppressed. The reason why the concentration of Al to be added is set to the upper limit value or less is that if it exceeds 5 × 10 13 atoms / cm 3 , it becomes an obstacle to Si single crystallization, and the single crystallization rate (ratio of the single crystal portion in the ingot) is This is because the manufacturing yield is reduced.
本発明によれば、以下の効果を奏する。
すなわち、本発明に係るプラズマエッチング用シリコン電極板によれば、ＢとＡｌとがドーパントとして添加された単結晶シリコンで構成されているので、単結晶シリコンの電気特性が面内で均一化され、プラズマエッチングによって生じる表面の凹凸を極めて少なくすることができると共に、内在歪みを抑えることができる。したがって、本発明のプラズマエッチング用シリコン電極板をプラズマエッチング装置に採用することによって、異常放電を抑制することができ、面内均一性の高いプラズマエッチングが可能になると共に、割れや欠けの発生を抑制することができる。
The present invention has the following effects.
That is, according to the silicon electrode plate for plasma etching according to the present invention, since it is composed of single crystal silicon to which B and Al are added as dopants, the electrical characteristics of the single crystal silicon are made uniform in the plane, The unevenness of the surface caused by the plasma etching can be extremely reduced and the inherent distortion can be suppressed. Therefore, by adopting the silicon electrode plate for plasma etching of the present invention in a plasma etching apparatus, abnormal discharge can be suppressed, plasma etching with high in-plane uniformity can be achieved, and cracking and chipping can be prevented. Can be suppressed.
以下、本発明に係るプラズマエッチング用シリコン電極板の一実施形態を、その製造方法と共に説明する。 Hereinafter, an embodiment of a silicon electrode plate for plasma etching according to the present invention will be described together with a manufacturing method thereof.
本実施形態のプラズマエッチング用シリコン電極板１２は、例えば図１に示されるように、複数の貫通細孔５が形成され、プラズマエッチング装置の真空容器１内の架台３上に載置されたシリコンウエハ４の上方に対向状態で配される。
このプラズマエッチング装置では、貫通細孔５を通してエッチングガス７をシリコンウエハ４に向って流しながら高周波電源６によりシリコン電極板１２と架台３との間に高周波電圧を印加し、高周波電圧の印加によりシリコン電極板１２と架台３との間の空間にプラズマ１０を発生させ、このプラズマ１０による物理反応と、シリコン−エッチングガス７による化学反応とにより、シリコンウエハ４の表面をエッチングする。
For example, as shown in FIG. 1, the silicon electrode plate for plasma etching 12 of the present embodiment has a plurality of through-
In this plasma etching apparatus, a high-
本実施形態のプラズマエッチング用シリコン電極板１２は、Ｂ(ボロン）とＡｌとがドーパントとして添加された単結晶シリコンで構成され、Ａｌの濃度が、１×１０１３ａｔｏｍｓ／ｃｍ３以上に設定されている。また、Ａｌの濃度は、５×１０１３ａｔｏｍｓ／ｃｍ３以下とされることが好ましい。 The silicon electrode plate for plasma etching 12 of the present embodiment is made of single crystal silicon to which B (boron) and Al are added as dopants, and the concentration of Al is set to 1 × 10 13 atoms / cm 3 or more. ing. Further, the concentration of Al is preferably 5 × 10 13 atoms / cm 3 or less.
この本実施形態のプラズマエッチング用シリコン電極板１２の製造方法について以下に具体的に説明する。
まず、石英ルツボ中でＳｉを溶解させるが、この際にＢと共にＡｌを上記の所定濃度となるように添加する。なお、Ａｌの添加量は微量であるため、Ｓｉ中にＡｌを高濃度（１×１０１６〜１×１０１７ａｔｏｍｓ／ｃｍ３程度）で含有した多結晶Ｓｉ塊を予め作製し、この多結晶Ｓｉ塊を破砕してＡｌ含有多結晶Ｓｉ粉末とし、該Ａｌ含有多結晶Ｓｉ粉末を必要なＡｌ濃度となるように秤量して石英ルツボ中のＳｉに添加する。
The manufacturing method of the silicon electrode plate for plasma etching 12 of this embodiment will be specifically described below.
First, Si is dissolved in a quartz crucible. At this time, Al is added together with B so as to have the above-mentioned predetermined concentration. Since the addition amount of Al is very small, a polycrystalline Si lump containing Al in Si at a high concentration (about 1 × 10 16 to 1 × 10 17 atoms / cm 3 ) is prepared in advance. The Si lump is crushed into Al-containing polycrystalline Si powder, and the Al-containing polycrystalline Si powder is weighed so as to have a required Al concentration and added to Si in the quartz crucible.
次に、例えば上記石英ルツボから得た直径：３００ｍｍの単結晶シリコンインゴットを用意し、このインゴットをダイヤモンドバンドソーにより厚さ：４ｍｍに輪切り切断して円盤状の単結晶シリコン基板を作製する。上記単結晶シリコンインゴットは、Ｂ（ボロン）が１×１０１４〜５×１０１４ａｔｏｍｓ／ｃｍ３のドーパント濃度で添加されていると共に、Ａｌが１×１０１３〜５×１０１３ａｔｏｍｓ／ｃｍ３のドーパント濃度で添加されて結晶成長されたものである。なお、全体としてｐ型となるようにＢとＡｌとのドーパント濃度が調整されている。この単結晶シリコン基板は、所定のＢ濃度を有するシリコン基板をＡｌと接触させて加熱し、Ａｌを熱拡散させることによって得てもよい。 Next, for example, a single crystal silicon ingot having a diameter of 300 mm obtained from the above-described quartz crucible is prepared, and this ingot is cut and cut into a thickness of 4 mm with a diamond band saw to produce a disk-shaped single crystal silicon substrate. In the single crystal silicon ingot, B (boron) is added at a dopant concentration of 1 × 10 14 to 5 × 10 14 atoms / cm 3 , and Al is 1 × 10 13 to 5 × 10 13 atoms / cm 3. The crystal is grown by adding a dopant concentration of. Note that the dopant concentrations of B and Al are adjusted so as to be p-type as a whole. This single crystal silicon substrate may be obtained by heating a silicon substrate having a predetermined B concentration in contact with Al and thermally diffusing Al.
さらに、この単結晶シリコン基板の上下面を平面研削し、反りを除去して厚みを整えた後、取付穴および貫通細孔５を加工する。例えば、内径：０．５ｍｍの貫通細孔５を孔間ピッチ：８ｍｍで形成する。この後、さらに平面研削を施して製品の所定厚みとする。
Further, the upper and lower surfaces of the single crystal silicon substrate are ground to remove warpage and adjust the thickness, and then the attachment holes and the through-
このように作製した本実施形態のプラズマエッチング用シリコン電極板１２では、Ｂ（ボロン）とＡｌとがドーパントとして添加された単結晶シリコンで構成されているので、単結晶シリコンの電気特性が面内で均一化され、プラズマエッチングにおいて表面が消耗する際に凹凸を極めて少なくすることができる。これは、Ｂに比べて拡散係数の大きいＡｌが添加されると、ＢよりもＡｌが拡散し易く、比抵抗値の面内均一性が向上するためである。 The plasma etching silicon electrode plate 12 of the present embodiment thus fabricated is composed of single crystal silicon to which B (boron) and Al are added as dopants, so that the electrical characteristics of the single crystal silicon are in-plane. When the surface is consumed in plasma etching, unevenness can be extremely reduced. This is because when Al having a larger diffusion coefficient than B is added, Al diffuses more easily than B and the in-plane uniformity of the specific resistance value is improved.
このように比抵抗値の面内均一性が向上したことにより、被エッチング物（シリコンウエハ４）との間のプラズマ密度が均一化して、表面の消耗状態も均一化されて凹凸がほとんど生じないことから、異常放電の発生を抑制してエッチングの均一化を図ることができる。また、添加されるＡｌの共有結合半径が、Ｓｉとほぼ同等であることから、不純物添加による格子歪みが生じ難く、内在する歪みを抑制でき、割れを防止できる。
また、Ａｌの濃度が、１×１０１３〜５×１０１３ａｔｏｍｓ／ｃｍ３であるので、良好な比抵抗値の面内均一性が得られると共に、単結晶化率が小さくなり、製造歩留まりが低下するのを抑制することができる。
Thus, by improving the in-plane uniformity of the specific resistance value, the plasma density with the object to be etched (silicon wafer 4) is uniformed, the surface wear state is also uniformed, and unevenness hardly occurs. Therefore, it is possible to make etching uniform by suppressing the occurrence of abnormal discharge. Further, since the covalent bond radius of Al to be added is substantially the same as that of Si, lattice distortion due to the addition of impurities hardly occurs, the inherent distortion can be suppressed, and cracking can be prevented.
In addition, since the Al concentration is 1 × 10 13 to 5 × 10 13 atoms / cm 3 , good in-plane uniformity of specific resistance can be obtained, the single crystallization rate is reduced, and the production yield is reduced. It can suppress that it falls.
次に、上記本実施形態に基づいて作製したシリコン電極板の実施例について評価した結果を説明する。 Next, the result of evaluating the examples of the silicon electrode plate produced based on the present embodiment will be described.
本発明のシリコン電極板の実施例は、表１に示すように、Ａｌの添加量を変えて作製し、比抵抗値の面内分布と、加工中の割れ枚数（１００枚中の割れ枚数）と、Ｓｉ単結晶化率とについてそれぞれ調べた。これらの結果を表１に示す。また、比較例として、Ａｌが１×１０１３ａｔｏｍｓ／ｃｍ３よりも少なく添加されたシリコン電極板も作製して同様に評価した結果も表１に併せて示す。なお、いずれの実施例および比較例も、Ｂの添加量を２×１０１４ａｔｏｍｓ／ｃｍ３とした。 Examples of the silicon electrode plate of the present invention were prepared by changing the amount of Al added, as shown in Table 1, the in-plane distribution of specific resistance values, and the number of cracks during processing (number of cracks in 100 sheets). And the Si single crystallization rate were examined. These results are shown in Table 1. In addition, as a comparative example, a silicon electrode plate to which Al was added in an amount less than 1 × 10 13 atoms / cm 3 was also produced and the results of evaluation were also shown in Table 1. In all of the examples and comparative examples, the amount of B added was set to 2 × 10 14 atoms / cm 3 .
この評価結果から判るように、比較例に対して本発明の実施例はいずれも比抵抗値の面内分布の数値が半分程度に小さくなっている。また、加工中の割れ数においても、比較例に対して本実施例はいずれも大幅に低減されている。なお、Ａｌの添加量（Ａｌ濃度）が５×１０１３ａｔｏｍｓ／ｃｍ３を超えて多い実施例４では、比較例や他の実施例よりもＳｉ単結晶化率が低下しているが、５×１０１３ａｔｏｍｓ／ｃｍ３以下の実施例１〜３については、９３％以上の高いＳｉ単結晶化率が得られている。
このように本実施例のシリコン電極板では、比抵抗値の高い面内均一性を有していると共に、加工中の割れを少なく抑えることができる。
As can be seen from this evaluation result, the numerical value of the in-plane distribution of the specific resistance value is reduced to about half in all of the examples of the present invention compared to the comparative example. Also, in this example, the number of cracks during processing is greatly reduced compared to the comparative example. In Example 4 in which the amount of Al added (Al concentration) exceeds 5 × 10 13 atoms / cm 3 , the Si single crystallization rate is lower than in the comparative example and other examples, but 5 For Examples 1 to 3 of × 10 13 atoms / cm 3 or less, a high Si single crystallization ratio of 93% or more was obtained.
Thus, the silicon electrode plate of the present embodiment has in-plane uniformity with a high specific resistance value, and can suppress cracks during processing.
なお、本発明の技術範囲は上記実施形態および上記実施例に限定されるものではなく、本発明の趣旨を逸脱しない範囲において種々の変更を加えることが可能である。 The technical scope of the present invention is not limited to the above-described embodiments and examples, and various modifications can be made without departing from the spirit of the present invention.
１…真空容器、２，１２…シリコン電極板、３…架台、４…シリコンウエハ、５…貫通細孔、６…高周波電源、７…プラズマエッチングガス、１０…ブラズマ DESCRIPTION OF SYMBOLS 1 ... Vacuum container, 2,12 ... Silicon electrode plate, 3 ... Mount, 4 ... Silicon wafer, 5 ... Through-hole, 6 ... High frequency power supply, 7 ... Plasma etching gas, 10 ... Plasma
Claims (2)
ＢとＡｌとがドーパントとして添加された単結晶シリコンで構成され、
Ａｌの濃度が、１×１０１３ａｔｏｍｓ／ｃｍ３以上であり、
全体としてｐ型となっていることを特徴とするプラズマエッチング用シリコン電極板。 A silicon electrode plate for plasma etching disposed in an opposed state above an object to be etched placed on a base in a vacuum vessel of a plasma etching apparatus,
It is composed of single crystal silicon to which B and Al are added as dopants,
The concentration of Al is state, and are 1 × 10 13 atoms / cm 3 or more,
A silicon electrode plate for plasma etching, which is p-type as a whole .
Ａｌの濃度が、５×１０１３ａｔｏｍｓ／ｃｍ３以下であることを特徴とするプラズマエッチング用シリコン電極板。 In the silicon electrode plate for plasma etching according to claim 1,
A silicon electrode plate for plasma etching, wherein the concentration of Al is 5 × 10 13 atoms / cm 3 or less.
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| JP2011019180A JP5713182B2 (en) | 2011-01-31 | 2011-01-31 | Silicon electrode plate for plasma etching |
| CN2011104153549A CN102623285A (en) | 2011-01-31 | 2011-12-13 | Silicon electrode plate for plasma etching |
| US13/330,110 US20120193030A1 (en) | 2011-01-31 | 2011-12-19 | Silicon electrode plate for plasma etching |
| TW100147384A TWI547981B (en) | 2011-01-31 | 2011-12-20 | Silicon electrode plate for plasma etching |
| KR1020120009230A KR101926859B1 (en) | 2011-01-31 | 2012-01-30 | Silicon electrode plate for plasma etching |
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| KR (1) | KR101926859B1 (en) |
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| JP5630710B2 (en) * | 2011-01-31 | 2014-11-26 | 三菱マテリアル株式会社 | Silicon electrode plate for plasma etching |
| US9472380B2 (en) * | 2012-12-27 | 2016-10-18 | Mitsubishi Materials Corporation | Silicon part for plasma etching apparatus and method of producing the same |
| JP6766678B2 (en) * | 2017-02-17 | 2020-10-14 | 三菱マテリアル株式会社 | Electrode plate for plasma processing equipment and its manufacturing method |
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| JPS54149463A (en) * | 1978-05-15 | 1979-11-22 | Matsushita Electric Ind Co Ltd | Selective diffusion method aluminum |
| JPH08250488A (en) * | 1995-01-13 | 1996-09-27 | Seiko Epson Corp | Device and method for plasma treatment |
| JP3728021B2 (en) * | 1996-06-28 | 2005-12-21 | 日清紡績株式会社 | Plasma etching electrode and manufacturing method thereof |
| JP2000138206A (en) * | 1998-11-04 | 2000-05-16 | Mitsubishi Materials Corp | Electrode plate for plasma etching system enabling formation of uniformly etched surface |
| FR2803090B1 (en) * | 1999-12-22 | 2003-07-11 | St Microelectronics Sa | ALUMINUM IMPLANTATION PROCESS |
| JP3411539B2 (en) * | 2000-03-06 | 2003-06-03 | 株式会社日立製作所 | Plasma processing apparatus and plasma processing method |
| US20020127853A1 (en) * | 2000-12-29 | 2002-09-12 | Hubacek Jerome S. | Electrode for plasma processes and method for manufacture and use thereof |
| JP4862221B2 (en) * | 2001-04-03 | 2012-01-25 | 信越半導体株式会社 | N-type silicon single crystal wafer and manufacturing method thereof |
| JP2003051491A (en) * | 2001-08-03 | 2003-02-21 | Mitsubishi Materials Corp | Electrode plate for plasma-etching apparatus |
| JP3868341B2 (en) * | 2002-04-22 | 2007-01-17 | 日清紡績株式会社 | Plasma etching electrode with excellent heat resistance and dry etching apparatus equipped with the same |
| JP4403919B2 (en) * | 2004-04-01 | 2010-01-27 | 株式会社Ｓｕｍｃｏ | Durable silicon electrode plate for plasma etching |
| JP4832067B2 (en) * | 2005-02-01 | 2011-12-07 | 東京エレクトロン株式会社 | Silicon member and manufacturing method thereof |
| JP2009018967A (en) * | 2007-07-12 | 2009-01-29 | Sharp Corp | Fusing method for solid raw material and method for growing crystal |
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| US20120193030A1 (en) | 2012-08-02 |
| JP2012160570A (en) | 2012-08-23 |
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| KR101926859B1 (en) | 2018-12-07 |
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