JP2012028482A - Silicon electrode plate for plasma etching - Google Patents

Silicon electrode plate for plasma etching Download PDF

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JP2012028482A
JP2012028482A JP2010164523A JP2010164523A JP2012028482A JP 2012028482 A JP2012028482 A JP 2012028482A JP 2010164523 A JP2010164523 A JP 2010164523A JP 2010164523 A JP2010164523 A JP 2010164523A JP 2012028482 A JP2012028482 A JP 2012028482A
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plasma etching
electrode plate
silicon
silicon electrode
etching
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Takashi Yonehisa
孝志 米久
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Mitsubishi Materials Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a silicon electrode plate for plasma etching which eliminates surface asperities due to plasma etching enabling a uniform etching.SOLUTION: The silicon electrode plate for plasma etching comprises a single crystal silicon to which B and Fe are added as dopants and a heat treatment with temperature of 500 to 800°C is applied. In this silicon electrode plate for plasma etching, an electric characteristic of the single crystal silicon is uniformed in a plane and surface asperities are highly eliminated when the surface is damaged during the plasma etching.

Description

この発明は、プラズマエッチングの面内均一性が向上するプラズマエッチング用シリコン電極板に関するものである。   The present invention relates to a silicon electrode plate for plasma etching that improves the in-plane uniformity of plasma etching.

一般に、半導体集積回路を製造する工程において使用するシリコンウエハをエッチングするためのプラズマエッチング装置は、図2に示されるように、真空容器1内にシリコン電極板2および架台3が間隔をおいて設けられており、架台3の上にシリコンウエハ4を載置し、エッチングガス7をシリコン電極板2に設けられた貫通細孔5を通してシリコンウエハ4に向って流しながら高周波電源6により電極板2と架台3の間に高周波電圧を印加し、高周波電圧の印加によりシリコン電極板2と架台3の間の空間にプラズマ10を発生させ、このプラズマ10による物理反応と、シリコン−エッチングガス7による化学反応により、シリコンウエハ4の表面をエッチングする装置であることは知られている(特許文献1参照)。   In general, in a plasma etching apparatus for etching a silicon wafer used in a process of manufacturing a semiconductor integrated circuit, as shown in FIG. 2, a silicon electrode plate 2 and a pedestal 3 are provided in a vacuum container 1 at intervals. The silicon wafer 4 is placed on the gantry 3, and the etching gas 7 is flown toward the silicon wafer 4 through the through-holes 5 provided in the silicon electrode plate 2, and the electrode plate 2 is connected to the electrode plate 2 by the high frequency power source 6. A high frequency voltage is applied between the gantry 3 and a plasma 10 is generated in the space between the silicon electrode plate 2 and the gantry 3 by the application of the high frequency voltage. A physical reaction by the plasma 10 and a chemical reaction by the silicon-etching gas 7 are generated. Thus, it is known that the apparatus etches the surface of the silicon wafer 4 (see Patent Document 1).

シリコン電極板2はカーボンで構成された電極板が使用されたこともあったが、近年、主として単結晶シリコン、多結晶シリコンまたは柱状晶シリコンからなるシリコン電極板が使用されている。   Although an electrode plate made of carbon has been used as the silicon electrode plate 2, in recent years, a silicon electrode plate mainly made of single crystal silicon, polycrystalline silicon or columnar crystal silicon has been used.

特開2003−51491号公報JP 2003-51491 A

上記従来の技術には、以下の課題が残されている。
従来のシリコン電極板では、プラズマエッチング時に対向する被エッチング物との間に生じたプラズマによって表面が徐々に消耗して凹凸が生じ、この凹凸によって異常放電が生じるおそれがあった。異常放電が生じると、エッチングの均一性が悪化してしまうという不都合がある。
このようなプラズマエッチングによる表面の凹凸は、平面内において比抵抗値にバラツキが存在しているため、対向する被エッチング物との間のプラズマ密度が不均一になって生じると考えられる。したがって、表面の凹凸を抑えるためには、比抵抗値の面内バラツキを抑える必要があるが、ドーパント含有量に面内差があるため、比抵抗値の面内バラツキを抑えることは困難であった。特に、高比抵抗値では、ドーパント含有量の面内差が大きく影響するため、比抵抗値の面内バラツキを抑えることが難しい。このように従来では、被エッチング物との間のプラズマ密度を均一に保持することが困難なため、被エッチング物であるウエハ面内のエッチングレートを均一化させることが難しいという問題があった。
The following problems remain in the conventional technology.
In the conventional silicon electrode plate, the surface is gradually consumed by the plasma generated between the object to be etched at the time of plasma etching, and irregularities are generated, which may cause abnormal discharge. When abnormal discharge occurs, there is a disadvantage that the uniformity of etching deteriorates.
Such unevenness of the surface due to plasma etching is considered to be caused by nonuniform plasma density between the object to be etched because the specific resistance value varies in a plane. Therefore, in order to suppress the unevenness of the surface, it is necessary to suppress the in-plane variation of the specific resistance value. However, since there is an in-plane difference in the dopant content, it is difficult to suppress the in-plane variation of the specific resistance value. It was. In particular, at a high specific resistance value, the in-plane difference of the dopant content greatly affects, so it is difficult to suppress the in-plane variation of the specific resistance value. As described above, conventionally, since it is difficult to uniformly maintain the plasma density with the object to be etched, there is a problem that it is difficult to make the etching rate within the wafer surface, which is the object to be etched, uniform.

本発明は、前述の課題に鑑みてなされたもので、プラズマエッチングによって生じる表面の凹凸を抑制し、均一なエッチングが可能になるプラズマエッチング用シリコン電極板を提供することを目的とする。   The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a silicon electrode plate for plasma etching that can suppress surface unevenness caused by plasma etching and enables uniform etching.

本発明者等は、比抵抗値の面内均一性が良好でプラズマエッチングに際してエッチングレートの面内均一性が向上するシリコン電極板を得るべく研究を行った。その結果、シリコン中にFeをドーピングしたものを特定の温度で熱処理することで、表面に凹凸がほとんど生じずにプラズマエッチングが可能になることを見出した。   The inventors of the present invention have studied to obtain a silicon electrode plate having good in-plane uniformity of specific resistance and improved in-plane uniformity of etching rate during plasma etching. As a result, it was found that plasma etching can be performed with almost no irregularities on the surface by heat-treating silicon doped with Fe at a specific temperature.

したがって、本発明は、上記知見から得られたものであり、前記課題を解決するために以下の構成を採用した。すなわち、本発明のプラズマエッチング用シリコン電極板は、B(ボロン)とFeとがドーパントとして添加され500〜800℃で熱処理された単結晶シリコンで構成されていることを特徴とする。   Therefore, the present invention has been obtained from the above findings, and the following configuration has been adopted in order to solve the above problems. That is, the silicon electrode plate for plasma etching of the present invention is characterized in that it is composed of single crystal silicon that is heat treated at 500 to 800 ° C. with B (boron) and Fe added as dopants.

このプラズマエッチング用シリコン電極板では、BとFeとがドーパントとして添加され500〜800℃で熱処理された単結晶シリコンで構成されているので、単結晶シリコンの電気特性が面内で均一化され、プラズマエッチングにおいて表面が消耗する際に凹凸を極めて少なくすることができる。これは、ドーピングしたFeとBとが結合して生じたFe−Bペアが、熱処理により解離し、拡散係数の大きいドナーとしてのFeが面内に不均一に分布していたアクセプターのBに対してキャリアの補償を行い、面内の比抵抗値を均一化させていると考えられる。このように比抵抗値の面内均一性が向上したことにより、被エッチング物との間のプラズマ密度が均一化して、表面の消耗状態も均一化されて凹凸がほとんど生じないことから、異常放電の発生を抑制してエッチングの均一化を図ることができる。   In this silicon electrode plate for plasma etching, B and Fe are added as dopants and are composed of single crystal silicon that is heat-treated at 500 to 800 ° C., so that the electrical characteristics of the single crystal silicon are made uniform in the plane, When the surface is consumed in plasma etching, unevenness can be extremely reduced. This is because Fe-B pairs formed by the combination of doped Fe and B are dissociated by heat treatment, and Fe as a donor having a large diffusion coefficient is distributed unevenly in the plane. Thus, it is considered that the carrier is compensated to uniform the in-plane specific resistance value. Since the in-plane uniformity of the specific resistance value is improved in this way, the plasma density with the object to be etched is made uniform, the surface wear state is also made uniform, and irregularities are hardly generated. Etching can be suppressed and etching can be made uniform.

なお、上記熱処理の温度範囲を500〜800℃とした理由は、500℃未満では、内在する酸素原子がドナー化し、狙いの比抵抗値から変動してしまうと共に、比抵抗値の面内分布が悪化してしまうためであり、800℃を超えると、Fe原子のゲッタリング現象が生じ、Feを添加した効果が消失してしまうためである。   The reason for setting the temperature range of the heat treatment to 500 to 800 ° C. is that if it is less than 500 ° C., the existing oxygen atoms become donors and change from the target specific resistance value, and the in-plane distribution of the specific resistance value is This is because when the temperature exceeds 800 ° C., a gettering phenomenon of Fe atoms occurs, and the effect of adding Fe disappears.

本発明によれば、以下の効果を奏する。
すなわち、本発明に係るプラズマエッチング用シリコン電極板によれば、BとFeとがドーパントとして添加され500〜800℃で熱処理された単結晶シリコンで構成されているので、単結晶シリコンの電気特性が面内で均一化され、プラズマエッチングによって生じる表面の凹凸を極めて少なくすることができる。したがって、本発明のプラズマエッチング用シリコン電極板をプラズマエッチング装置に採用することによって、異常放電を抑制することができ、面内均一性の高いプラズマエッチングが可能になる。
The present invention has the following effects.
That is, according to the silicon electrode plate for plasma etching according to the present invention, it is composed of single crystal silicon that is heat-treated at 500 to 800 ° C. with B and Fe added as dopants. The surface unevenness caused by the plasma etching can be extremely reduced by being uniformed in the plane. Therefore, by adopting the silicon electrode plate for plasma etching of the present invention in a plasma etching apparatus, abnormal discharge can be suppressed and plasma etching with high in-plane uniformity can be achieved.

本発明に係るプラズマエッチング用シリコン電極板の実施例および比較例において、プラズマエッチング後の表面状態を示す拡大写真である。In the Example and comparative example of the silicon electrode plate for plasma etching which concern on this invention, it is an enlarged photograph which shows the surface state after plasma etching. 従来のプラズマエッチング装置の断面説明図である。It is sectional explanatory drawing of the conventional plasma etching apparatus.

以下、本発明に係るプラズマエッチング用シリコン電極板の一実施形態を、その製造方法と共に説明する。   Hereinafter, an embodiment of a silicon electrode plate for plasma etching according to the present invention will be described together with a manufacturing method thereof.

まず、本実施形態のプラズマエッチング用シリコン電極板の製造方法について以下に具体的に説明する。
例えば、直径:300mmの単結晶シリコンインゴットを用意し、このインゴットをダイヤモンドバンドソーにより厚さ:4mmに輪切り切断して円盤状の単結晶シリコン基板を作製する。上記単結晶シリコンインゴットは、B(ボロン)が2×1014cm−3〜3×1014cm−3のドーパント濃度で添加されていると共に、Feが2×1013cm−3〜3×1013cm−3のドーパント濃度で添加されて結晶成長されたものである。なお、全体としてp型となるようにBとFeとのドーパント濃度が調整されている。
First, a method for manufacturing the silicon electrode plate for plasma etching according to the present embodiment will be specifically described below.
For example, a single crystal silicon ingot having a diameter of 300 mm is prepared, and the ingot is cut into a thickness of 4 mm using a diamond band saw to produce a disk-shaped single crystal silicon substrate. In the single crystal silicon ingot, B (boron) is added at a dopant concentration of 2 × 10 14 cm −3 to 3 × 10 14 cm −3 , and Fe is 2 × 10 13 cm −3 to 3 × 10. The crystal was grown by adding a dopant concentration of 13 cm −3 . Note that the dopant concentrations of B and Fe are adjusted so as to be p-type as a whole.

次に、この単結晶シリコン基板を、大気雰囲気中において、500〜800℃で1〜2時間の熱処理を施し、急冷する。
さらに、この単結晶シリコン基板の上下面を平面研削し、反りを除去して厚みを整えた後、取付穴および貫通細孔を加工する。例えば、内径:0.5mmの貫通細孔を孔間ピッチ:8mmで形成する。この後、さらに平面研削を施して製品の所定厚みとする。
Next, this single crystal silicon substrate is subjected to heat treatment at 500 to 800 ° C. for 1 to 2 hours in an air atmosphere, and then rapidly cooled.
Further, the upper and lower surfaces of the single crystal silicon substrate are surface ground, the warp is removed and the thickness is adjusted, and then the attachment hole and the through hole are processed. For example, through pores having an inner diameter of 0.5 mm are formed with an inter-hole pitch of 8 mm. Thereafter, surface grinding is further performed to obtain a predetermined thickness of the product.

なお、本実施形態では、ドーパントのFeを予め結晶成長時に添加して単結晶シリコンインゴットを得ているが、Bのみ結晶成長時に添加した単結晶シリコンインゴットから切断し上記加工を行ったシリコン基板に、Feを含有したFe含有塗料を表面に塗布した後、上記熱処理を施すことで、Fe含有塗料中のFeをシリコン基板内に拡散させて結晶中に添加しても構わない。なお、この際のFe含有塗料は、Fe以外の成分として、熱処理中にシリコン基板中に拡散せずに蒸発するものが採用され、例えばC(炭素)とFeとの混合塗料等が採用される。   In this embodiment, the dopant Fe is added in advance during crystal growth to obtain a single crystal silicon ingot. However, only B is cut from the single crystal silicon ingot added during crystal growth and processed into the above-described silicon substrate. The Fe-containing paint containing Fe may be applied to the surface, and the heat treatment may be performed to diffuse the Fe in the Fe-containing paint into the silicon substrate and add it to the crystal. In this case, as the Fe-containing paint, a component that evaporates without being diffused into the silicon substrate during the heat treatment is adopted as a component other than Fe, for example, a mixed paint of C (carbon) and Fe is adopted. .

このように作製した本実施形態のプラズマエッチング用シリコン電極板では、BとFeとがドーパントとして添加され500〜800℃で熱処理された単結晶シリコンで構成されているので、単結晶シリコンの電気特性が面内で均一化され、プラズマエッチングにおいて表面が消耗する際に凹凸を極めて少なくすることができる。したがって、プラズマエッチング時に表面の消耗状態も均一化されて凹凸がほとんど生じないことから、異常放電の発生を抑制してエッチングの均一化を図ることができる。   Since the silicon electrode plate for plasma etching according to the present embodiment manufactured in this way is composed of single crystal silicon in which B and Fe are added as dopants and heat-treated at 500 to 800 ° C., the electrical characteristics of the single crystal silicon Can be made uniform in the surface, and unevenness can be extremely reduced when the surface is consumed in plasma etching. Therefore, the surface wear state during plasma etching is made uniform and unevenness is hardly generated, so that the occurrence of abnormal discharge can be suppressed and the etching can be made uniform.

次に、上記本実施形態に基づいて実際に作製したシリコン電極板の実施例を、プラズマエッチング装置にセットし、以下の条件でプラズマエッチングを行った。なお、被エッチング物としては、シリコンウエハを用いた。また、比較例として、Feが添加されておらず、Bのみ添加されたシリコン電極板を採用して同様にプラズマエッチングを行った。   Next, an example of the silicon electrode plate actually produced based on the above-described embodiment was set in a plasma etching apparatus, and plasma etching was performed under the following conditions. Note that a silicon wafer was used as an object to be etched. Further, as a comparative example, plasma etching was similarly performed by adopting a silicon electrode plate to which Fe was not added and only B was added.

<エッチング条件>
チャンバー内圧力:13Pa
エッチングガス組成:90sccmCHF3 +4sccmO2 +150sccmHe
高周波電力:2kW
周波数:20kHz
<Etching conditions>
Chamber pressure: 13Pa
Etching gas composition: 90 sccm CHF 3 +4 sccm O 2 +150 sccm He
High frequency power: 2kW
Frequency: 20kHz

このプラズマエッチング後に、本実施例および比較例の両シリコン電極板の表面を観察した拡大写真を、図2に示す。
これらの拡大写真からわかるように、Feが添加されていない比較例では、プラズマエッチングにより表面に多数の穴が形成されて多くの凹凸が生じているのに対し、Feを添加した本実施例では、表面に穴がほとんどなく、エッチング後も平坦面を維持している。
FIG. 2 shows an enlarged photograph of the surface of both the silicon electrode plates of this example and the comparative example observed after this plasma etching.
As can be seen from these enlarged photographs, in the comparative example in which no Fe was added, a number of holes were formed on the surface by plasma etching and many irregularities were formed, whereas in this example in which Fe was added, The surface has few holes, and a flat surface is maintained after etching.

なお、本発明の技術範囲は上記実施形態および上記実施例に限定されるものではなく、本発明の趣旨を逸脱しない範囲において種々の変更を加えることが可能である。   The technical scope of the present invention is not limited to the above-described embodiments and examples, and various modifications can be made without departing from the spirit of the present invention.

1…真空容器、2…電極板、3…架台、4…シリコンウエハ、5…貫通細孔、6…高周波電源、7…プラズマエッチングガス、10…ブラズマ   DESCRIPTION OF SYMBOLS 1 ... Vacuum container, 2 ... Electrode plate, 3 ... Mount, 4 ... Silicon wafer, 5 ... Through-hole, 6 ... High frequency power supply, 7 ... Plasma etching gas, 10 ... Plasma

Claims (1)

BとFeとがドーパントとして添加され500〜800℃で熱処理された単結晶シリコンで構成されていることを特徴とするプラズマエッチング用シリコン電極板。   A silicon electrode plate for plasma etching, characterized in that it is composed of single crystal silicon in which B and Fe are added as dopants and heat-treated at 500 to 800 ° C.
JP2010164523A 2010-07-22 2010-07-22 Silicon electrode plate for plasma etching Pending JP2012028482A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012160571A (en) * 2011-01-31 2012-08-23 Mitsubishi Materials Corp Silicon electrode plate for plasma etching
JP2018036670A (en) * 2013-07-10 2018-03-08 デクセリアルズ株式会社 Polarizer and manufacturing method of polarizer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1017393A (en) * 1996-06-28 1998-01-20 Nisshinbo Ind Inc Plasma etching electrode and its manufacture
JP2002068885A (en) * 2000-08-28 2002-03-08 Shin Etsu Chem Co Ltd Silicon component and method of measuring amount of metal impurity on its surface

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1017393A (en) * 1996-06-28 1998-01-20 Nisshinbo Ind Inc Plasma etching electrode and its manufacture
JP2002068885A (en) * 2000-08-28 2002-03-08 Shin Etsu Chem Co Ltd Silicon component and method of measuring amount of metal impurity on its surface

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012160571A (en) * 2011-01-31 2012-08-23 Mitsubishi Materials Corp Silicon electrode plate for plasma etching
JP2018036670A (en) * 2013-07-10 2018-03-08 デクセリアルズ株式会社 Polarizer and manufacturing method of polarizer

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