JP5705867B2 - ２次置換多項式インタリーバを備えたｌｔｅターボ・デコーダのためのａｐｐ（ａｐｒｉｏｒｉｐｒｏｂａｂｉｌｉｔｙ：先験確率）ストレージ設計 - Google Patents

２次置換多項式インタリーバを備えたｌｔｅターボ・デコーダのためのａｐｐ（ａｐｒｉｏｒｉｐｒｏｂａｂｉｌｉｔｙ：先験確率）ストレージ設計 Download PDF

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JP5705867B2
JP5705867B2 JP2012537113A JP2012537113A JP5705867B2 JP 5705867 B2 JP5705867 B2 JP 5705867B2 JP 2012537113 A JP2012537113 A JP 2012537113A JP 2012537113 A JP2012537113 A JP 2012537113A JP 5705867 B2 JP5705867 B2 JP 5705867B2
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JP2013509824A (ja
JP2013509824A5 (enExample
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パン、ハンファン
ウェイ、ヨンビン
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Qualcomm Inc
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Qualcomm Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0055—MAP-decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0052—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Mobile Radio Communication Systems (AREA)
JP2012537113A 2009-10-29 2010-10-29 ２次置換多項式インタリーバを備えたｌｔｅターボ・デコーダのためのａｐｐ（ａｐｒｉｏｒｉｐｒｏｂａｂｉｌｉｔｙ：先験確率）ストレージ設計 Expired - Fee Related JP5705867B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/608,919 US8255759B2 (en) 2009-10-29 2009-10-29 APP (a priori probability) storage design for LTE turbo decoder with quadratic permutation polynomial interleaver
US12/608,919 2009-10-29
PCT/US2010/054703 WO2011059813A2 (en) 2009-10-29 2010-10-29 App (a priori probability) storage design for lte turbo decoder with quadratic permutation polynomial interleaver

Publications (3)

Publication Number Publication Date
JP2013509824A JP2013509824A (ja) 2013-03-14
JP2013509824A5 JP2013509824A5 (enExample) 2015-02-12
JP5705867B2 true JP5705867B2 (ja) 2015-04-22

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JP2012537113A Expired - Fee Related JP5705867B2 (ja) 2009-10-29 2010-10-29 ２次置換多項式インタリーバを備えたｌｔｅターボ・デコーダのためのａｐｐ（ａｐｒｉｏｒｉｐｒｏｂａｂｉｌｉｔｙ：先験確率）ストレージ設計

Country Status (7)

Country Link
US (1) US8255759B2 (enExample)
EP (1) EP2494728A2 (enExample)
JP (1) JP5705867B2 (enExample)
KR (1) KR101454301B1 (enExample)
CN (1) CN102577205B (enExample)
TW (1) TW201131991A (enExample)
WO (1) WO2011059813A2 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8811452B2 (en) * 2009-12-08 2014-08-19 Samsung Electronics Co., Ltd. Method and apparatus for parallel processing turbo decoder
US8996948B2 (en) * 2009-12-23 2015-03-31 Intel Corporation Methods, systems, and apparatus for tail termination of turbo decoding
US8983008B2 (en) * 2009-12-23 2015-03-17 Intel Corporation Methods and apparatus for tail termination of turbo decoding
US8930791B2 (en) 2009-12-23 2015-01-06 Intel Corporation Early stop method and apparatus for turbo decoding
US8719658B2 (en) * 2010-09-09 2014-05-06 Qualcomm Incorporated Accessing memory during parallel turbo decoding
US8819517B1 (en) 2011-01-06 2014-08-26 Intel Corporation Systems and methods for a turbo decoder in a universal mobile telecommunication system (UMTS)
US8495455B1 (en) 2011-01-06 2013-07-23 Mindspeed Technologies, Inc. Systems and methods for parallel dual-mode turbo decoders
US9001593B2 (en) 2012-12-21 2015-04-07 Apple Inc. Apparatus to suppress concurrent read and write word line access of the same memory element in a memory array
CN109861694B (zh) 2013-11-20 2021-10-26 华为技术有限公司 极化码的处理方法和设备
CN103888224B (zh) * 2014-04-04 2017-05-10 中国科学院自动化研究所 一种用于LTE系统Turbo码内交织的并行实现方法及装置
US10810119B2 (en) * 2018-09-21 2020-10-20 Micron Technology, Inc. Scrubber driven wear leveling in out of place media translation

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1310434C (zh) * 2001-04-06 2007-04-11 华为技术有限公司 特博码阵列解码器
JP3898574B2 (ja) * 2002-06-05 2007-03-28 富士通株式会社 ターボ復号方法及びターボ復号装置
CN1585321A (zh) * 2004-06-07 2005-02-23 北京交通大学 一种基于Turbo编解码的数字信息抗干扰软加密方法及系统
KR100912156B1 (ko) * 2005-02-03 2009-08-14 파나소닉 주식회사 병렬 인터리버, 병렬 디인터리버 및 인터리브 방법
US8065588B2 (en) * 2007-01-17 2011-11-22 Broadcom Corporation Formulaic flexible collision-free memory accessing for parallel turbo decoding with quadratic polynomial permutation (QPP) interleave
CN101034951A (zh) * 2007-04-10 2007-09-12 中兴通讯股份有限公司 一种Turbo码内交织器的实现方法
JP4743156B2 (ja) * 2007-04-27 2011-08-10 ソニー株式会社 復号装置
US8051239B2 (en) * 2007-06-04 2011-11-01 Nokia Corporation Multiple access for parallel turbo decoder
JP4874312B2 (ja) * 2007-09-20 2012-02-15 三菱電機株式会社 ターボ符号復号装置、ターボ符号復号方法及び通信システム
US8140932B2 (en) * 2007-11-26 2012-03-20 Motorola Mobility, Inc. Data interleaving circuit and method for vectorized turbo decoder
US20090274248A1 (en) 2008-05-01 2009-11-05 Interdigital Patent Holdings, Inc. Method and apparatus for contention-free interleaving using a single memory

Also Published As

Publication number Publication date
WO2011059813A3 (en) 2011-07-21
JP2013509824A (ja) 2013-03-14
CN102577205B (zh) 2015-11-25
EP2494728A2 (en) 2012-09-05
US20110107019A1 (en) 2011-05-05
KR101454301B1 (ko) 2014-10-27
WO2011059813A2 (en) 2011-05-19
CN102577205A (zh) 2012-07-11
KR20120088781A (ko) 2012-08-08
TW201131991A (en) 2011-09-16
US8255759B2 (en) 2012-08-28

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