JP5689266B2 - PFETチャネルSiGeを有する金属ゲート及び高k誘電体デバイス - Google Patents
PFETチャネルSiGeを有する金属ゲート及び高k誘電体デバイス Download PDFInfo
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- JP5689266B2 JP5689266B2 JP2010197286A JP2010197286A JP5689266B2 JP 5689266 B2 JP5689266 B2 JP 5689266B2 JP 2010197286 A JP2010197286 A JP 2010197286A JP 2010197286 A JP2010197286 A JP 2010197286A JP 5689266 B2 JP5689266 B2 JP 5689266B2
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- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims description 44
- 229910052751 metal Inorganic materials 0.000 title claims description 26
- 239000002184 metal Substances 0.000 title claims description 26
- 239000010410 layer Substances 0.000 claims description 100
- 238000000034 method Methods 0.000 claims description 29
- 229910021332 silicide Inorganic materials 0.000 claims description 22
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 239000011229 interlayer Substances 0.000 claims description 2
- 229910052746 lanthanum Inorganic materials 0.000 claims description 2
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 description 16
- 230000008021 deposition Effects 0.000 description 10
- 238000012545 processing Methods 0.000 description 9
- 125000006850 spacer group Chemical group 0.000 description 8
- 230000008901 benefit Effects 0.000 description 7
- 230000001681 protective effect Effects 0.000 description 5
- 239000000203 mixture Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000012212 insulator Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000005457 optimization Methods 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 229910000676 Si alloy Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000010348 incorporation Methods 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 108091006149 Electron carriers Proteins 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- -1 HfSiON Inorganic materials 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Description
11:第1の高k誘電体
12:第1の金属
13:ポリシリコン
14:保護カバー
14’:保護キャップ層
15:第1のシーケンスの層
21:ゲートスタック
22:ゲート誘電体
30:基板
31:NFETソース/ドレイン
32:PFETソース/ドレイン
33:PFETスペーサ
34:NFETスペーサ
35、37:シリサイド
36:支持層
39:Si主面
41:内面
51:第2のシーケンスの層
52:第2の金属
53:第2の高k誘電体
98:ウェル
99:浅いトレンチ
Claims (11)
- 回路構造体を製造する方法であって、
基板のSi主面上にNFETデバイス用及びPFETデバイス用の部分を画定するステップと、
ブランケット・エピタキシャル成長を用いて前記部分の上にSiGe層を堆積させるステップと、
前記SiGe層の上に、第1の高k誘電体及び第1の金属を含む第1のシーケンスの層をブランケット配置するステップと、
前記第1のシーケンスの層を前記NFETデバイス及び前記PFETデバイスの両方に組み込むステップであって、前記第1の高k誘電体は第1のゲート誘電体に含まれ、前記第1の金属は第1のゲートスタックに含まれる、前記組み込むステップと、
前記NFETデバイス内の、前記第1のゲートスタック、前記第1のゲート誘電体、及び前記SiGe層を除去し、第2の高k誘電体及び第2の金属を含む第2のシーケンスの層を配置して、前記NFETデバイスの第2のゲート誘電体及び第2のゲートスタックを形成するステップと
を含む、方法。 - 前記NFETデバイス及び前記PFETデバイスの両方のソース/ドレイン領域の上に前記SiGe層に接触するシリサイドを形成するステップをさらに含む、請求項1に記載の方法。
- 前記PFETデバイスにおいて、前記ソース/ドレイン領域の上に前記シリサイドを形成するのと同時に、前記第1のゲートスタックの頂部に前記シリサイドを形成するステップをさらに含む、請求項2に記載の方法。
- 前記NFETデバイス内の前記第1のゲートスタックを除去する前に、ブランケット配置されて前記NFETデバイス内の前記第1のゲートスタックの頂面と同じ高さまで平坦化される層間誘電体(ILD)を形成するステップをさらに含む、請求項1に記載の方法。
- 前記ILDを酸化物であるように選択するステップをさらに含む、請求項4に記載の方法。
- 前記第1のシーケンスの層において、前記第1の高k誘電体がHfO2を含むように、及び、前記第1の金属がTiNを含むように選択するステップをさらに含む、請求項1に記載の方法。
- 前記部分の上に前記第2のシーケンスの層をブランケット配置することにより前記第2のシーケンスの層を前記配置するステップを実施し、前記NFETデバイス内の前記第2のゲートスタックの外側の前記第2のシーケンスの層を除去するように研磨するステップをさらに含む、請求項1に記載の方法。
- 前記第2のシーケンスの層において、前記第2の高k誘電体がHfO2を含むように、及び、前記第2の金属がランタン(La)を含むように選択するステップをさらに含む、請求項7に記載の方法。
- 前記第1のシーケンスの層を前記PFETデバイスの所望のデバイス・パラメータ値をもたらすように選択し、前記第2のシーケンスの層を前記NFETデバイスの所望のデバイス・パラメータ値をもたらすように選択するステップをさらに含む、請求項1に記載の方法。
- 前記NFETデバイス及び前記PFETデバイスの両方の前記所望のデバイス・パラメータ値としてしきい値電圧値を選択するステップをさらに含む、請求項9に記載の方法。
- 前記回路構造体をCMOS回路となるように選択するステップをさらに含む、請求項1に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/563,032 US8298882B2 (en) | 2009-09-18 | 2009-09-18 | Metal gate and high-K dielectric devices with PFET channel SiGe |
US12/563032 | 2009-09-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011066406A JP2011066406A (ja) | 2011-03-31 |
JP5689266B2 true JP5689266B2 (ja) | 2015-03-25 |
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Application Number | Title | Priority Date | Filing Date |
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JP2010197286A Expired - Fee Related JP5689266B2 (ja) | 2009-09-18 | 2010-09-03 | PFETチャネルSiGeを有する金属ゲート及び高k誘電体デバイス |
Country Status (3)
Country | Link |
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US (2) | US8298882B2 (ja) |
JP (1) | JP5689266B2 (ja) |
KR (1) | KR20110031103A (ja) |
Families Citing this family (16)
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US8471343B2 (en) | 2011-08-24 | 2013-06-25 | International Bussiness Machines Corporation | Parasitic capacitance reduction in MOSFET by airgap ild |
US8377773B1 (en) * | 2011-10-31 | 2013-02-19 | Globalfoundries Inc. | Transistors having a channel semiconductor alloy formed in an early process stage based on a hard mask |
US8648388B2 (en) * | 2012-02-15 | 2014-02-11 | International Business Machines Corporation | High performance multi-finger strained silicon germanium channel PFET and method of fabrication |
US9029959B2 (en) | 2012-06-29 | 2015-05-12 | International Business Machines Corporation | Composite high-k gate dielectric stack for reducing gate leakage |
US8946035B2 (en) * | 2012-09-27 | 2015-02-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Replacement channels for semiconductor devices and methods for forming the same using dopant concentration boost |
KR20140047920A (ko) | 2012-10-15 | 2014-04-23 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
CN103915342B (zh) * | 2013-01-08 | 2016-08-31 | 中芯国际集成电路制造(上海)有限公司 | 无结晶体管和互补无结晶体管的形成方法 |
US20140246734A1 (en) * | 2013-03-01 | 2014-09-04 | Globalfoundries Inc. | Replacement metal gate with mulitiple titanium nitride laters |
US9012956B2 (en) * | 2013-03-04 | 2015-04-21 | Globalfoundries Inc. | Channel SiGe removal from PFET source/drain region for improved silicide formation in HKMG technologies without embedded SiGe |
KR20140121617A (ko) * | 2013-04-08 | 2014-10-16 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US8927363B2 (en) | 2013-05-17 | 2015-01-06 | International Business Machines Corporation | Integrating channel SiGe into pFET structures |
US9484266B1 (en) | 2015-08-04 | 2016-11-01 | International Business Machines Corporation | Complementary heterogeneous MOSFET using global SiGe substrate and hard-mask memorized germanium dilution for nFET |
CN106549016B (zh) * | 2015-09-21 | 2019-09-24 | 中国科学院微电子研究所 | 半导体器件及其制作方法 |
CN106558552B (zh) * | 2015-09-28 | 2019-06-11 | 中国科学院微电子研究所 | Cmos制作方法 |
CN106558553A (zh) * | 2015-09-28 | 2017-04-05 | 中国科学院微电子研究所 | Cmos制作方法 |
CN106558554A (zh) * | 2015-09-28 | 2017-04-05 | 中国科学院微电子研究所 | Cmos制作方法 |
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JP4085051B2 (ja) * | 2003-12-26 | 2008-04-30 | 株式会社東芝 | 半導体装置およびその製造方法 |
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-
2009
- 2009-09-18 US US12/563,032 patent/US8298882B2/en active Active
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2010
- 2010-09-03 JP JP2010197286A patent/JP5689266B2/ja not_active Expired - Fee Related
- 2010-09-10 KR KR1020100088851A patent/KR20110031103A/ko not_active Application Discontinuation
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2012
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US20110068369A1 (en) | 2011-03-24 |
KR20110031103A (ko) | 2011-03-24 |
US8796773B2 (en) | 2014-08-05 |
JP2011066406A (ja) | 2011-03-31 |
US8298882B2 (en) | 2012-10-30 |
US20120267685A1 (en) | 2012-10-25 |
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